Post on 10-May-2022
Marvell’s Carrier Optimized Networking Switches
Introducing latest Prestera® Switches
December 8, 2020
© 2020 Marvell. All rights reserved. 2
Storage#1 in HDD and SSD
controllers, Fibre Channel
Security#1 in security processors
Networking#2 in Switches and PHYs
Most complete data infrastructure portfolioSemiconductor solutions that move, store, process, secure the world’s data faster and more reliably than anyone else
Processors#1 in baseband and
data plane processors
© 2020 Marvell. All rights reserved. 3
Marvell Switches - Networking, done right
20 years of customer-driven innovation and leadership#1 in Access Switching | #1 in Multi-Gigabit PHYs
Carrier Data CenterEnterprise SMB / Industrial
© 2020 Marvell. All rights reserved. 4
Market drivers for carrier optimized networking
Comprehensive switching silicon offering 400G connectivity,
integrated security, small footprint, low power, 5G data plane
and Marvell IQ software for carrier optimized networking
Analytics
and AI
Security Connectivity Timing and
network slicing
Multi-Cloud
5G
© 2020 Marvell. All rights reserved. 5
Announcement summary
▪ Industry’s first low density 50G PAM4 switching silicon (1.2T/16.T) for Carrier Optimized Networking
▪ New devices enable low power, low density, feature rich switching for Mobile Edge Computing and 5G Fronthaul Networks
▪ Accelerating Data Center Interconnect (DCI) transformation to Ethernet Switching with integrated security (MACsec) and pluggable 400G coherent optics
© 2020 Marvell. All rights reserved. 6
Carrier optimized networking
State-of-the-art switch silicon-based on 50G PAM4
for service providers and edge data centers
New Prestera 7K series: ▪ 98DX7312: 300G (12 x 25G SerDes)
▪ 98DX7325: 1.2T (24x 50G SerDes)
▪ 98DX7335: 1.6T (32x 50G SerDes)
Key use cases:▪ Edge switch for 5G fronthaul networking
▪ Metro Access switch for 400G backhaul
▪ Small footprint switch for Mobile Edge Computing
▪ Data Center Interconnects (DCI) with 400G & MACsec
1.2T 1.6T
Introducing new Prestera 7K, optimized for Carrier and DC Edge switching
Timing(TSN)
I/O(400G)
Telemetry (OAM)
Low Power
Data Plane (SRv6)
Security (MACsec)
0.3T
98DX733598DX7312 98DX7325
© 2020 Marvell. All rights reserved. 7
Prestera 7K: Switches for Radio & Metro Access
Fronthaul gateways, Carrier Ethernet switch, Edge connectivity
Backhaul access
Fronthaul
Prestera 7K
Metro access switch
Fronthaul Switch
Edge DC
BBU Server
Prestera 7K
© 2020 Marvell. All rights reserved. 8
Edge POPshub-sites
Fronthaul gateway
SFP28
SFP28
ROE/eCPRI
10/25G eCPRI
2x100G-R4
Dual
CPRI /
eCPRI
eCPRI
5G NR
RRH
4G LTE
RRH
5G BBU
Aldrin2’s4G BBU
Aldrins4G BB
DU
5G BB
DU
5G BBU
Aldrin2’svBB
DU
WAN Router
Backh
au
l Serv
ice
Pro
vid
er N
etw
ork
Competitive advantages
▪ Edge optimized: Smaller footprint, lower
power, lower solution cost
▪ Integrated security: MACsec, Secure Boot
▪ Advanced networking: Segment routing
O-RAN fronthaul switching with integrated timing, security & telemetry
Spine Switch Prestera 8K
Spine Switch Prestera 8K
Aldrin3/S/XL Aldrin3/S/XLLeaf SwitchPrestera 7K
Leaf SwitchPrestera 7K
OCTEON FUSION®
Prestera 7K
Scalable and secure O-RAN fronthaul switching
© 2020 Marvell. All rights reserved. 9
Metro access switch with secure 400G interfaces
Access/
Fronthaul
Aggregation
network
Prestera 7K Benefits
Precise 5G Timing: PTP Class C/SyncE, 802.1CM
Integrated Security: MACsec, Secure Boot
Scalable I/O: 1/2.5/5/10/25G/100/400G interfaces
Comprehensive Telemetry & Hardware OAM
Advanced Networking: L2/L3, MPLS, SRv6
Metroaccess switch
100G
(4x25G)
CPU
PCIe &
1G/10G100G
(4x25G)
Prestera 7K 400G-ZR
400G-ZRQSFP28
QSFP28
400G 400G
400G 400G
Metroaccess switch
400G
CPU
PCIe &
1G/10G
400G
Prestera 7K
QSFP56
QSFP56100G
100G
Metro
access
ring
Ethernet switching in metro networks powered by 400G coherent pluggable optics
Metroaccess switch
100G
(4x25G)
CPU
PCIe &
1G/10G100G
(4x25G)
Prestera 7K
QSFP28
QSFP28
Metr
oaccess
sw
itch
100G
(4x25G
)
CP
U
PC
Ie&
1G
/10G
100G
(4x25G
)
Pre
ste
ra7K
QS
FP
28
QS
FP
28
Target Markets
Broadband services: OLT, Cable access
Data Center Interconnect (DCI)
© 2020 Marvell. All rights reserved. 10
Marvell end-to-end portfolio
PerformanceService assurance 5G network timing
SecurityZero-Trust AccessMACsec encryption
VisibilityActionable Analytics
IntelligenceAI EnablementSmart TE (SRv6)
5G
IoT
Aggregation and Core Switches
AccessSwitches
2T, 4T, 12.8T
0.3T, 1.2T, 1.6T
© 2020 Marvell. All rights reserved. 11
Visibility for actionable analytics
Smartautomation
Root-causeanalysis
Flexible integration
In-band streaming (IOAM)
Line-ratetelemetry
Anomalydetection
Predictivehealth reporting
Application awareness
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001010100011101110100101010100
0101010001110111010010101010
10101000111011101000111010
0100100010010001011101
01001000100100010
101001000
TrackIQ
© 2020 Marvell. All rights reserved. 12
Zero-trust integrated security
End-to-end
256bit MACsec
Threat management
Security sensors
Secure boot and storage
Group policies
Security zonesSecure-AI apps, traffic analytics
Embeddedsafeguards
Softwareupdate scam
Encrypted
SecureIQ
10100100010
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10001001000
11101010101
00011100010
10100100010
01000100101
10001001000
11101010101
00011100010
© 2020 Marvell. All rights reserved. 13
AI application enablement
Infrastructure automation
Autonomous networks
enablement
Smart services offload
In-networkcomputing
Smart Traffic Engineering
(Segment Routing)
Intelligent processing acceleration
NetIQ
Edge-Processing Optimized
© 2020 Marvell. All rights reserved. 14
400GbE edge optimized
switch
Inline programmability at Network Edge
Timing (PTP/SnycE/TSN) for 5G fronthaul
Rich Data Plane for Carrier Access (L3/MPLS/SRv6)
End-to-end high performance and resiliency
1G 2.5G 5/10G
10G 25G 100G
40G 100G 400G
© 2020 Marvell. All rights reserved. 15
Scalable Prestera architecture
▪ Programmable feature-rich processing pipeline
▪ Flow-aware data processing and traffic management
▪ Integrated MACsec, secure boot and storage
▪ Security sensors for traffic anomaly detection
▪ Line-rate telemetry collection and flexible reporting
▪ Multi-core Arm®-based CPUs to run embedded software
▪ Accurate timing synchronization for SyncE / PTP
Traffic Manager Egress Queues
SecuredARM CPU
MACs, MACsec Engine, Timing SyncE/PTP
Marvell SerDes
Hi-Performance Packet Buffer
Forwarding DB
IngressPipeline
Programmable Engines
Flow DB
Telemetry Data
EgressPipeline
Programmable Engines
Common architecture across access to core switches minimizes customer development costs and time-to-market
© 2020 Marvell. All rights reserved. 16
Multiple software offerings enabling customers
Disrupting status quo with key innovations and eco-system partners
Edge to cloud
infrastructure
eco-system
Industry standard
application interfaces
Software
Development Kit
(SDK)
NOS
partners
Industry
proven Network
Operating Systems
© 2020 Marvell. All rights reserved. 17
Marvell optimizing the Edge
1 Industry-leading edge optimized networking portfolio
2 State-of-the-art telemetry and visibility
3 Built-in intelligence and AI capabilities for smart services
4 Best-in-class timing and slicing features for 5G edge
5 Optimized embedded security for edge and access networks
6 Broad software support for most comprehensive networking portfolio
Q&A