Post on 06-May-2020
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© 2001
Managing High-Speed Clocks & DataManaging High-Speed Clocks & Data
Greg SteinkeDirector, Component Applications
Greg SteinkeDirector, Component Applications
© 2001
Managing High-Speed ClocksManaging High-Speed Clocks
� Higher System Performance Requires Innovative Clocking Schemes
� What Are The Possibilities?
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© 2001
High-Speed Clocking SchemesHigh-Speed Clocking Schemes
� Synchronous Clocking� Source-Synchronous Clocking� Clock-Data Synchronization (CDS)� Clock-Data Recovery (CDR)
© 2001
High-Speed Clocking SchemesHigh-Speed Clocking Schemes
� Synchronous Clocking� Source-Synchronous Clocking� Clock-Data Synchronization (CDS)� Clock-Data Recovery (CDR)
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© 2001
Synchronous ClockingSynchronous Clocking
� One Clock Drives All Devices in System� fMAX Limited by tCO, tPD & tSU
ClockClock
DataData
DataData DestinationDestinationSourceSource
© 2001
High-Speed Clocking SchemesHigh-Speed Clocking Schemes
� Synchronous Clocking� Source-Synchronous Clocking� Clock-Data Synchronization (CDS)� Clock-Data Recovery (CDR)
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© 2001
Source-Synchronous ClockingSource-Synchronous Clocking� Clock Signal Transmitted with Data
� Board Skew Reduces System Performance
ClockClock
DataData
ClockClock
DataData DestinationDestinationSourceSource
© 2001
Source-Synchronous BenefitSource-Synchronous Benefit� Source-Synchronous Clocking Enables
Data Transfer at High Speeds− Performance No Longer Limited by tCO,
tPD & tSU
− Maximum Performance Factors� Edge Rate of Driver� Skew between Data Signals & Clock Signals
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© 2001
Source-Synchronous DrawbacksSource-Synchronous Drawbacks� Every Chip-to-Chip Data Transfer
Introduces New Clock Domain− Receiver Must Manage Multiple Clock Domains
� Performance Affected by Board Skew− Skew Reduction Complicates Board Design
© 2001
Source-Synchronous Timing AnalysisSource-Synchronous Timing Analysis
� Transmitter Skew, Board Skew & Clock Jitter Reduce System Performance
ClockClock
Data
Data
Board Skew
Clock Jitter
Transmitter Skew
DestinationDestinationSourceSource
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© 2001
Source-Synchronous ParametersSource-Synchronous Parameters� Parameters Required for Timing
Analysis− Time-Unit Interval (TUI)
�Bit Period: 2 ns for 500-Mbit Transfer
− Channel-to-Channel Skew (TCCS) � Skew between Transmitter Outputs
© 2001
Timing ParametersTiming Parameters
� Sampling Window (SW)− Time During Which Data Is Sampled at
Receiver
� Receiver Skew Margin (RSKM)− Remaining Margin to Accommodate Board
Skew & PLL Jitter
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© 2001
0 0 0 10 1 1 1 01
Successful Data TransferSuccessful Data Transfer
0 0 0 10 1 1 1 01
0 0 0 10 1 1 1 0
Data Must Be Valid During Sampling WindowData Must Be Valid During Sampling Window
105-MHz Clock105-MHz Clock
840-MHz Internally Generated Clock840-MHz Internally Generated Clock
Channel 0Channel 0
Channel 1Channel 1
Channel 2Channel 2
Receiver Samples Data on Clock Falling EdgeReceiver Samples Data on Clock Falling Edge
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TCCS & Board Skew Change Data to Clock AlignmentTCCS & Board Skew Change Data to Clock Alignment
© 2001
0 0 0 10 1 1 1 01
Excessive TCCS Or Board SkewExcessive TCCS Or Board Skew
0 0 0 10 1 1 11
0 0 0 10 1 1 1 01
Excessive Skew Causes Invalid Data During Sampling WindowExcessive Skew Causes Invalid Data During Sampling Window
105-MHz Clock105-MHz Clock
840-MHz Internally Generated Clock840-MHz Internally Generated Clock
Channel 0Channel 0
Channel 1Channel 1
Channel 2Channel 2
TCCS & Board Skew Change Data to Clock AlignmentTCCS & Board Skew Change Data to Clock Alignment
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© 2001
Quantifying Timing BudgetQuantifying Timing Budget� Example: 840-Mbps Data Transfer
− TUI = 1/840 Mbps = 1190 ps
− TCCS = 400 ps
− SW = 440 ps
− RSKM = ½ (TUI - SW - TCCS) = 175 ps
TimeTime--Unit Interval Unit Interval (TUI)(TUI)
TCCSTCCS TCCSTCCSRSKMRSKM RSKMRSKMSWSW
Sampling Clock EdgeSampling Clock Edge
© 2001
High-Speed Clocking SchemesHigh-Speed Clocking Schemes
� Synchronous Clocking� Source-Synchronous Clocking� Clock-Data Synchronization (CDS)� Clock-Data Recovery (CDR)
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© 2001
Tx1
CDS Expands Clock PossibilitiesCDS Expands Clock Possibilities� Entire System Can Operate Using Single Clock
− Eases Printed Circuit Board (PCB) Layout Requirements− Permits More Flexible Clocking Topologies− Unlimited Skew Tolerance
Clock
Channel N
Channel 1
InternallySynchronizes
Data to System Clock
InternallySynchronizes
Data to System Clock
•••
•••
TxN
SkewSkewRx
© 2001
CDS OptionsCDS Options
� Single-Bit Clock-Data Synchronization (CDS)− Used for Point-to-Point Connections− Compensates for Board Skew up to 50% of
TUI
� Multi-Bit CDS− Compensates for Any Board Skew− Enables Multi-Point Applications
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© 2001
Single-Bit CDS ImplementationSingle-Bit CDS Implementation� CDS Circuitry Selects Appropriate Clock Phase
Independently at Each Channel
� Calibrated with Training Pattern
D
D
D
DRX RX
PhasePhase--Locked Locked
Loop (PLL)Loop (PLL)
Serial Input Data
0° Output
90° Output
Control Logic Selects Register with Expected Pattern
SynchronizedData
System Clock
© 2001
-180ºInternal Clock
0ºInternal Clock
� Selects 1 of 5 Clock Strobes Covering Bit Period� Maintains Byte Alignment
0 0 0 10 1 1 1
SelectedClock Phase
01
105 MHz Clock
Data Channel
-90ºInternal Clock
90ºInternal Clock
180ºInternal Clock
Single-Bit CDS ImplementationSingle-Bit CDS Implementation
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© 2001
Multi-Bit CDSMulti-Bit CDS� Compensates for Unlimited Board Skew
− RSKM Doesn’t Limit Performance− Uses Eight Clock Strobes
� Cover Two Bit Periods � Capture Data with Any Skew
� Byte Alignment Performed in Logic Elements
© 2001
Multi-Bit CDS ImplementationMulti-Bit CDS Implementation
Serial Data
System Logic
Dedicated CircuitDedicated Circuit
APEX™ II DeviceAPEX™ II Device
CDS Bit
Alignment Circuit
Serial-Parallel
Converter
Byte Alignment
Circuit
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© 2001
� Implement Bit & Byte Alignment by Using Two Stages of Training Patterns
� CDS Circuit Recognizes First Training Pattern for Bit Alignment
� Logic Recognizes Second Training Pattern for Byte Alignment
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Multi-Bit CDS AlignmentMulti-Bit CDS Alignment
© 2001
ClockClock
Data BData B
ClockClock
N:1 N:1 TopologyTopology
Data AData A
ClockClock
Dat
a C
Dat
a C
ClockClockControl Signal Initiates CDS Pattern
Control Signal Initiates Byte Alignment Pattern
Control Circuitry & Pattern Detect Logic for Every RX Channel
�������
Master
�������
��������������
� Data Received at Master Is Skewed by Transmitter tCO Variation & Board Skew
� Multi-Bit CDS Compensates for Skew
System Using Multi-Bit CDSSystem Using Multi-Bit CDS
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© 2001
� Benefits− Calibrates Receiving Device for Transmitter or
Board Skew− Receiver Does Not Need to Manage Multiple
Clock Domains
� Drawbacks− Transmitters Must Be Clocked from Same
System Clock− Need Training Pattern− Multi-Bit CDS Requires Byte Alignment Logic
CDS TradeoffsCDS Tradeoffs
© 2001
� Synchronous Clocking� Source-Synchronous Clocking� Clock-Data Synchronization (CDS)� Clock-Data Recovery (CDR)
High-Speed Clocking SchemesHigh-Speed Clocking Schemes
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© 2001
CDRCDR� Reference Clock Is Used
� Trace Lengths Need Not Match
� Each Source & Destination May Have Individual Clock
ClockClock
DataData
DataData
ClockClock
DestinationDestinationSourceSource
© 2001
CDR ImplementationCDR Implementation
� Clock Encoded into Data Stream� PLL Recovers Clock from Data Transitions
ClockRecovery
PLL
Reference Clock
Recovered Clock to System
SystemClock
Serial-to-Parallel FIFO
Clock Divider
1.25GHz
1.25 GBit 125 MHz
10-Bit Bus
125 MHz
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© 2001
CDR BenefitsCDR Benefits
� Receiver Recovers Individual Clocks from Each Incoming Data Channel− Each Channel Can Have Phase Variation
� Transmitters Can Operate on Multiple Crystals− Each Channel Can Have Limited Frequency
Variation
© 2001
CDR DrawbacksCDR Drawbacks
� Encoding Schemes Used to Ensure Maximum Run Length− Transitions Required for Clock Recovery− Some Data Channel Bandwidth Used to
Encode the Data− 1.25-Gbit Bandwidth Used for 1.00-Gbit
Data
� Data Buffering Required to Accommodate Frequency Variation
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© 2001
SourceSource--SynchronousSynchronous
CDSCDS CDRCDR
Higher Performance � Board Skew Not an Issue
� Receiver Has OneClock Domain
� Board Skew Not an Issue
� Clock Source Flexibility
Benefits Easy to Design
� Must Use Training Pattern
� Must Use Byte Alignment Circuit
APEX II
� Must EncodeData
� Encoding Scheme Consumes Bandwidth
Mercury
� Must Control Board Skew
� Must Design with Multiple Clock Domains
APEX 20KE, APEX 20KC, APEX II, Mercury™
SynchronousSynchronous
Disadvantages
Device Support
Lower Performance
All
Clocking Scheme SummaryClocking Scheme Summary