Post on 22-Mar-2021
Technical Support Line: 1-800-LATTICE or (408) 428-6414EXPERT-ML 7.01
Macro Library Reference Manual
Version 7.0
Macro Library Reference Manual 2
Copyright
This document may not, in whole or part, be copied, photocopied, reproduced,translated, or reduced to any electronic medium or machine-readable form withoutprior written consent from Lattice Semiconductor Corporation.
The software described in this manual is copyrighted and all rights are reserved byLattice Semiconductor Corporation. Information in this document is subject to changewithout notice.
The distribution and sale of this product is intended for the use of the originalpurchaser only and for use only on the computer system specified. Lawful users ofthis product are hereby licensed only to read the programs on the disks, cassettes, ortapes from their medium into the memory of a computer solely for the purpose ofexecuting them. Unauthorized copying, duplicating, selling, or otherwise distributingthis product is a violation of the law.
Trademarks
The following trademarks are recognized by Lattice Semiconductor Corporation:
Generic Array Logic, ISP, ispANALYZER, ispATE, ispCODE, ispDCD,ispDOWNLOAD, ispDS, ispDS+, ispEXPERT, ispGDS, ispGDX, ispHDL, ispJTAG,ispSmartFlow, ispStarter, ispSTREAM, ispTA, ispTEST, ispTURBO, ispVECTOR,ispVerilog, ispVHDL, Latch-Lock, LHDL, pDS+, RFT, and Twin GLB are trademarks ofLattice Semiconductor Corporation.
E2CMOS, GAL, ispGAL, ispLSI, pDS, pLSI, Silicon Forest, and UltraMOS areregistered trademarks of Lattice Semiconductor Corporation.
Microsoft, Windows, and MS-DOS are registered trademarks of MicrosoftCorporation.
IBM is a registered trademark of International Business Machines Corporation.
Lattice Semiconductor Corporation5555 NE Moore Ct.Hillsboro, OR 97124
(503) 681-0118
September 1998
Table of Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Purpose and Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Module Macro Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Pin Labeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Logic Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Using the NOMIN Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Quick Reference Macro Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Programmable Macro Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Arithmetic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
ADDF1, ADDF2, F3ADD, ADDF4, ADDF8, ADDF8A & ADDF16A . . . . . . . . . . . . . . . . . . . . . 50ADDH1, ADDH2, ADDH3, ADDH4, ADDH8, ADDH8A, & ADDH16A . . . . . . . . . . . . . . . . . . 65
Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78CMP2, CMP4, and CMP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78MAG2, MAG4, and MAG8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81MULT24 and MULT44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Propagate-Generate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85PG1, PG2, PG3, & PG4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Subtractors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91SUBF1, SUBF2, F3SUB, SUBF4, SUBF8, SUBF8A, & SUBF16A . . . . . . . . . . . . . . . . . . . . . 91SUBH1, SUBH2, SUBH3, SUBH4, SUBH8, SUBH8A, & SUBH16A . . . . . . . . . . . . . . . . . . 102
Coders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
BIN27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116DEC2 and DEC2E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118DEC3 and DEC3E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119DEC4 and DEC4E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121PREN8 and PREN8E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121PREN10 and PREN10E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122PREN16 & PREN16E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124Binary Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
CBD11, CBD12, CBD14, and CBD18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125CBD21, CBD22, CBD24, and CBD28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131CBD31, CBD32, CBD34, and CBD38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137CBD41, CBD42, CBD44, and CBD48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144CBD516 and CBD616 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151CBU11, CBU12, CBU14, and CBU18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161CBU21, CBU22, CBU24, and CBU28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167CBU31, CBU32, CBU34, and CBU38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173CBU41, CBU42, CBU44, and CBU48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180CBU516 and CBU616 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187CBU716 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196CBUD1, CBUD2, CBUD4, and CBUD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202CDD14 and CDD18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212CDD24 and CDD28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218CDD34 and CDD38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224CDD44 and CDD48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Decade Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234CDU14 and CDU18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234CDU24 and CDU28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240CDU34 and CDU38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246CDU44 and CDU48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252CDUD4 and CDUD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258CDUD4c and CDUD8c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Gray Code Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278CGD14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278CGD24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281CGU14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284CGU24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288CGUD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295Bidirectional Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
BI11, BI14, and BI18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296BI21, BI24, and BI28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297BI31, BI34, and BI38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298BI41, BI44, and BI48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299BIID11, BIID14, and BIID18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300BIID21, BIID24, and BIID28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301BIID31, BIID34, and BIID38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302BIID41, BIID44, and BIID48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303BIID51, BIID54, and BIID58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304BIID61, BIID64, and BIID68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305BIID71, BIID74, and BIID78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306BIID81, BIID84, and BIID88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307BIIL11, BIIL14, and BIIL18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308BIIL21, BIIL24, and BIIL28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
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BIIL31, BIIL34, and BIIL38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310BIIL41, BIIL44, and BIIL48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311BIIL51, BIIL54, and BIIL58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312BIIL61, BIIL64, and BIIL68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313BIIL71, BIIL74, and BIIL78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314BIIL81, BIIL84, and BIIL88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316IB11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316ID11, ID14, and ID18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317ID21, ID24, and ID28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318IL11, IL14, and IL18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319IL21, IL24, and IL28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321OB11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321OB21, OB24, and OB28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322OT11, OT14, and OT18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323OT21, OT24, and OT28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324OT31, OT34, and OT38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325OT41, OT44, and OT48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
AND2 Through AND18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328BUF and INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329NAND2 Through NAND12 & NAND16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330NOR2 Through NOR12 & NOR16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331OR2 Through OR12 and OR16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332XNOR2, XNOR3, XNOR4, XNOR7, XNOR8, and XNOR9 . . . . . . . . . . . . . . . . . . . . . . . . . . 333XOR2, LXOR2, XOR3, XOR4, XOR8, and XOR9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
MUX/DMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
MUX2 and MUX2E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336MUX4 and MUX4E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337MUX8 and MUX8E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338MUX16 and MUX16E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339MUX22 and MUX22E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343MUX24 and MUX24E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344MUX42 and MUX42E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345MUX44 and MUX44E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346MUX44A and MUX44AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349MUX82 and MUX82E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Demultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351DMUX2 and DMUX2E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351DMUX4 and DMUX4E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352DMUX22 and DMUX22E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353DMUX24 and DMUX24E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354DMUX42 and DMUX42E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
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DMUX44 and DMUX44E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356DMUX82 & DMUX82E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358D Flip-flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
FD11, FD14, and FD18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359FD21, FD24, and FD28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360FD31, FD34, and FD38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361FD41, FD44, and FD48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362FD51, FD54, and FD58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363FD61, FD64, and FD68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364FD71, FD74, and FD78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365FD81, FD84, and FD88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366FD91, FD94, and FD98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367FDA1, FDA4, and FDA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
JK Flip-flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369FJK11 and FJK21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369FJK31 and FJK41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370FJK51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Toggle Flip-flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372FT11 and FT21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
D Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373LD11, LD14, and LD18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373LD21, LD24, and LD28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374LD31, LD34, and LD38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375LD41, LD44, and LD48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376LD51, LD54, and LD58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377LD61, LD64, and LD68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378LD71, LD74, and LD78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379LD81, LD84, and LD88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380LD91, LD94, and LD98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381LDA1, LDA4, and LDA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
SR Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383LSR1 and LSR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384SRR11, SRR14, and SRR18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384SRR21, SRR24, and SRR28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388SRR31, SRR34, and SRR38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392SRR41, SRR44, and SRR48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396SRRL1, SRRL4, and SRRL8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Module Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405Control Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
ALECTRL8, ALECTRL9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406ALFCTRL8, ALFCTRL9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407PSCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408POLCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409CAOCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
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Timer/Counter Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411C4R4AL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411C4R4PL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413T4R4AL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415T4R4PL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417T4R4CPV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
RAM Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421RAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421RAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423RAM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424RAM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426RAM5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427RAM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429RAM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430RAM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432RAM9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434RAM10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436RAM11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438RAM12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
FIFO Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442FIFO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442FIFO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444FIFO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445FIFO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446FIFO4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
Register File Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450PSSR8X16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450SSSR128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452SPSR8X16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453RF8X16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
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Preface
OverviewThis Preface contains information on the following topics:
■ Purpose and Scope
■ Documentation Conventions
■ Quick Reference Macro Table
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Purpose and ScopeThe Macro Library Reference Manual documents the features, capabilities, and useof the library macros provided with the pLSI and ispLSI Development System fromLattice Semiconductor Corporation (LSC). This reference manual provides thefollowing information about each macro:
Function The purpose and use of the macro.
Availability Whether the macro is available in pDS, ispDS, and ispDS+, or inispDS and ispDS+, or in pDS only.
Symbol The representation of a macro within a schematic.
Type Macro types are as follows:
LogicThese are the building blocks of macros.
PrimitiveAND, NAND, OR, NOR, and XOR gates, and the FD11 andFD12 D-type flip-flops are logic primitives.
HardLSC ensures the performance and logic utilization of hardmacros. These macros use entire GLBs. You cannot edit thesemacros.
SoftThese macros are editable, so you can develop more complexfunctions based on them. If a soft macro uses only part of a GLB,you can add additional logic to that GLB.
Logic Resources The number of product terms (PTs), Generic Logic Blocks(GLBs), GLB outputs, and GLB levels a macro requires (pDSonly – values for pDS+ macros are approximate).
Equation Entry The format of the equation you enter that represents the macro(pDS only, but shows the pDS+ pin order).
Truth Table The table that shows the relationships between all the possibleinputs and outputs for the macro.
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Documentation ConventionsThe following sections describe the conventions used for signal names, truth tables,pin labeling, and logic resources. A quick reference table is also included which givesa brief description of each macro and its availability.
Signal Names
A0..An-1,B0..Bn-1 .... inputsZ0..Zn-1................... outputsZN0 ........................ output of inverted gateXI0.......................... external input pinXO0........................ external output pinOE.......................... Output EnableXB0 ........................ external bidirectional pinCLK ........................ Clock lineD0..Dn-1.................. input to D flip-flop/latch; input to T flip-flop; load inputs for counters
and shift registersQ0..Qn-1 ................. output of flip-flop or latchQ0’..Qn-1’................ previous output of flip-flop or latchTE........................... Test Enable input for scan flip-flopsTI0..TIn-1................. Test Inputs for scan flip-flops and latchesG ............................ Gate for latchTG .......................... Test Gate for scan latchLD........................... parallel Load for shift registers and countersCD.......................... Clear Direct (asynchronous)PS .......................... Preset SynchronousCS .......................... Clear SynchronousPD .......................... Preset Direct (only on latches)J0,K0...................... inputs to JK flip-flopS0,S1,R0,R1 .......... inputs to SR latchS0..Sn-1 .................. select lines – multiplexors/demultiplexors, decoders/priority
encodersEN .......................... Enable for multiplexors and countersCI............................ Carry In for addersCO.......................... Carry Out for addersBI............................ Borrow In for subtractorsBO.......................... Borrow Out for subtractorsEQ.......................... A equals B output for comparatorsGT .......................... A greater than B output for comparatorsLT ........................... A Less Than B output for comparatorsEQI ......................... Cascade input of EQ from previous stage for mag comparatorsGTI ......................... Cascade input of GT from previous stage for mag comparatorsLTI .......................... Cascade input of LT from previous stage for mag comparators
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CAI ......................... shift registers: serial input; counters: CAscade InCAIR....................... shift right serial inputCAIL ....................... shift left serial inputRL........................... shift Right/shift Left control for SRRL shift registersCAO ....................... CAscade Out for countersDNUP..................... count Down/count UP control for up-down counters
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Truth Tablesx ...................don’t careX...................X (unknown) stateZ...................high impedance stated ...................any pattern of 1s and 0s on an input or set of inputsd ...................the inverse of d↑ ...................rising clock edge↓ ...................falling clock edge- ....................appears in output column if a bidirectional pin acts as an input pin
For macros such as the MUX2 and the MUX2E, which are identical except for theenable feature on the MUX2E, table cells in gray represent the additional truth tablerow and column that apply only to the macro with the enable. For example, the truthtable for the MUX2 and MUX2E appears as follows:
By disregarding the gray cells in the truth table shown above, you can see the truthtable for the MUX2.
Some truth tables show input and output information for several macros that performthe same function but handle a different number of bits. For example, LD11 and LD14have one-bit and four-bit D latches, respectively. In these truth tables, you see 0~n-1,which indicates that the column represents bits 0 through n-1, where n is the numberof bits in the macro of interest. The truth table for LD11 and LD14 looks like:
Input Output
EN S0 Z01 0 A01 1 A10 x 0
Input Output
S0 Z0
0 A0
1 A1
Input Output
D0~Dn-1 G Q0~Qn-1
d 1 d
x 0 Q0~Qn-1
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The truth table for LD11 alone would look like this:
Module Macro Truth Tables*.............. These inputs, once set are fixed and can only be connected to VCC/GND‡ ............. Refer to the User Programmable Features table† ............. Refer to the section on Control Blocks for functionality** ............ ADI, ADO are required to share I/O pins so must be conttected to bidirecitonal
pins§ ............. Data-in can only be external input signals. No logic can be connected§§ ........... Data-out can only be external output signals. No logic can be connected
Input Output
D0 G Q0
d 1 d
x 0 Q0
Macro Library Reference Manual 13
Pin LabelingTwo formats for describing groups of pins–logic diagrams and equation entry lines–are included in this manual. Both of these formats are shown in the followingexample:
Both of these examples refer to pins Q0 through Q7. The expressions [Q0..Q7] andQ0,Q1,Q2,Q3,Q4,Q5,Q6,Q7 are equivalent.
Equation formats apply to pDS only. They are included for pDS+ macros becausethey show the pin order of the macros.
Overline characters such as A0 indicate pin inversion. For the first pin in thesequence of a macro declaration statement, an exclamation point signifies an activelow condition; for example,
AND12(!Z0,[A0..A11]);
CBUD8
CBUD8([Q0..Q7] ,CAO,[D0..D7],CAI,CLK,PS,LD,EN,DN
Equation Entry
Logic Symbol
DN/UP
PS
CSCD
D0
D1
D2
D3
D4
D5
D6
LD
D7
CAI
EN
Q7
Q6
Q5
Q4
Q3
Q2
Q1
CAO
Q0
Macro Library Reference Manual 14
Logic ResourcesThe logic resources of each macro are described as follows:
Product Terms (PTs) The number of gates in the AND array of theGLBs used by the macro. Add one product termif you use the Product Term Clock option withthe macro or if the macro has an asynchronousclear (CD). If “/out” follows the number ofproduct terms, it means the “number of productterms per output.”
Generic Logic Blocks(GLB) The number of GLBs that the macro uses.
GLB Outputs (Outputs) The number of GLB outputs the macro uses,including outputs internal to the macro. A GLBoutput is also called an Output Logic Macrocell(OLMC).
GLB Levels (Levels) The number of levels of GLBs (not gates) used.
For example, this is the logic resource summary for MUX24 and MUX24E:
A dash (-) indicates that the amount of the resource the macro uses depends on howthe macro is used or how the partitioner in pDS+ arranges the macro in the device.
Logic resources for most of the logic primitive macros are not listed. These macrosare rarely used by themselves, and when used with other macros, they are placed inspace left over by other macros.
Logic resource information only applies to pDS. For pDS+ macros, this information isapproximate because the partitioner may use different resources for a given macrodepending on the rest of the design.
Macro PT GLBs Outputs Levels
MUX24 4/out .5 2 1
MUX24E 4/out .5 2 1
Macro Library Reference Manual 15
Using the NOMIN AttributeCalling some macros and specifying the NOMIN attribute for a specific pin results inerror 5319 being issued to indicate a problem fitting the logic. The following table liststhe macros and the pin that cannot be assigned the NOMIN attribute.
Macro ParameterF3ADD_2 P012
ADDF8A_2 P012ADDF8A_5 P345ADDF16A_2 P012ADDF16A_4 P345ADDF16A_6 P678ADDF16A_8 P911
ADDF16A_10 P1214ADDH8A_4 P345
ADDH16A_4 P345ADDH16A_6 P678ADDH16A_8 P911ADDH16A_10 P1214
CMP8 EQMULT44_6 P345F3SUB_2 P012
SUBF8A_2 P012SUBF8A_5 P345
SUBF16A_2 P012SUBF16A_4 P345SUBF16A_6 P678SUBF16A_8 P911
SUBF16A_10 P1214SUBH8A_4 P345
SUBH16A_4 P345SUBH16A_6 P678SUBH16A_8 P911SUBH16A_10 P1214
Macro Library Reference Manual 16
Quick Reference Macro Table
Quick Reference Macro TableThe following table lists the macros available from LSC for use with the pDS andisPDS or ispDS+ design solutions. The table also indicates if the macro can be usedwith the LS C 1000, 2000, or 3000 family of parts.
Macro Description 1K 2K 3K pDSispDS/ispDS+
ADDF1 1-bit full adder (page 50) X X X X X
ADDF2 2-bit full adder (page 50) X X X X X
F3ADD 3-bit full adder withpropagate-generate(page 50)
X X X X X
ADDF4 4-bit full adder (page 50) X X X X X
ADDF8 8-bit full adder (page 50) X X X X X
ADDF8A 8-bit full adder withpropagate-generatesubmacros (page 50)
X X X X X
ADDF16A 16-bit full adder withpropagate-generatesubmacros (page 50)
X X X X X
ADDH1 1-bit half adder (page 65) X X X X X
ADDH2 2-bit half adder (page 65) X X X X X
ADDH3 3-bit half adder (page 65) X X X X X
ADDH4 4-bit half adder (page 65) X X X X X
ADDH8 8-bit half adder (page 65) X X X X X
ADDH8A 8-bit half adder built withpropagate-generatesubmacros (page 65)
X X X X X
ADDH16A 16-bit half adder built withpropagate-generatesubmacros (page 65)
X X X X X
AND2 throughAND12 andAND16
2 to 12-input AND gatesand 16-input AND gate(page 328)
X X X X X
AND13 throughAND15, AND17,and AND18
13 to 15-input AND gatesand 17 to 18-input ANDgates (page 328)
X X X X
Macro Library Reference Manual 17
Quick Reference Macro Table
BI11 1-bit bidirect pin(page 296)
X X X X X
BI14 Four BI11s with commonOutput Enable (page 296)
X X X X
BI18 Eight BI11s with commonOutput Enable (page 296)
X X X X
BI21 1-bit bidirect pin withinverted output (page 297)
X X X X X
BI24 Four BI21s with commonOutput Enable (page 297)
X X X X
BI28 Eight BI21s with commonOutput Enable (page 297)
X X X X
BI31 1-bit bidirect pin with activelow Output Enable(page 298)
X X X X X
BI34 Four BI31s with commonOutput Enable (page 298)
X X X X
BI38 Eight BI31s with commonOutput Enable (page 298)
X X X X
BI41 1-bit bidirect pin withinverted output and activelow Output Enable(page 299)
X X X X X
BI44 Four BI41s with commonOutput Enable (page 299)
X X X X
BI48 Eight BI41s with commonOutput Enable (page 299)
X X X X
BIID11 1-bit bidirect pin withregistered input(page 300)
X X X X
BIID14 Four BIID11s withcommon clock and OutputEnable (page 300)
X X X
BIID18 Eight BIID11s withcommon clock and OutputEnable (page 300)
X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 18
Quick Reference Macro Table
BIID21 1-bit bidirect pin withregistered input andinverted output (page 301)
X X X X
BIID24 Four BIID21s withcommon clock and OutputEnable (page 301)
X X X
BIID28 Eight BIID21s withcommon clock and OutputEnable (page 301)
X X X
BIID31 1-bit bidirect pin withregistered input and activelow enable (page 302)
X X X X
BIID34 Four BIID31s withcommon clock and OutputEnable (page 302)
X X X
BIID38 Eight BIID31s withcommon clock and OutputEnable (page 302)
X X X
BIID41 1-bit bidirect pin withregistered input, invertedoutput, and active lowenable (page 303)
X X X X
BIID44 Four BIID41s withcommon clock and OutputEnable (page 303)
X X X
BIID48 Eight BIID41s withcommon clock and OutputEnable (page 303)
X X X
BIID51 1-bit bidirect pin withregistered input andinverted clock (page 304)
X X X
BIID54 Four BIID51s withcommon clock and OutputEnable (page 304)
X X
BIID58 Eight BIID51s withcommon clock and OutputEnable (page 304)
X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 19
Quick Reference Macro Table
BIID61 1-bit bidirect pin withregistered input, invertedoutput, and inverted clock(page 305)
X X X
BIID64 Four BIID61s withcommon clock and OutputEnable (page 305)
X X
BIID68 Eight BIID61s withcommon clock and OutputEnable (page 305)
X X
BIID71 1-bit bidirect pin withregistered input, active lowenable, and inverted clock(page 306)
X X X
BIID74 Four BIID71s withcommon clock and OutputEnable (page 306)
X X
BIID78 Eight BIID71s withcommon clock and OutputEnable (page 306)
X X
BIID81 1-bit bidirect pin withregistered input, invertedoutput, active low enable,and inverted clock(page 307)
X X X
BIID84 Four BIID81s withcommon clock and OutputEnable (page 307)
X X
BIID88 Eight BIID81s withcommon clock and OutputEnable (page 307)
X X
BIIL11 1-bit bidirect pin withlatched input (page 308)
X X X X
BIIL14 Four BIIL11s with commonG and Output Enable(page 308)
X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 20
Quick Reference Macro Table
BIIL18 Eight BIIL11s withcommon G and OutputEnable (page 308)
X X X
BIIL21 1-bit bidirect pin withlatched input and invertedoutput (page 309)
X X X X
BIIL24 Four BIIL21s with commonG and Output Enable(page 309)
X X X
BIIL28 Eight BIIL21s withcommon G and OutputEnable (page 309)
X X X
BIIL31 1-bit bidirect pin withlatched input and activelow enable (page 310)
X X X X
BIIL34 Four BIIL31s with commonG and Output Enable(page 310)
X X X
BIIL38 Eight BIIL31s withcommon G and OutputEnable (page 310)
X X X
BIIL41 1-bit bidirect pin withlatched input, invertedoutput, and active lowenable (page 311)
X X X X
BIIL44 Four BIIL41s with commonG and Output Enable(page 311)
X X X
BIIL48 Eight BIIL41s withcommon G and OutputEnable (page 311)
X X X
BIIL51 1-bit bidirect pin withlatched input, and invertedG (page 312)
X X X
BIIL54 Four BIIL51s with commonG and Output Enable(page 312)
X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 21
Quick Reference Macro Table
BIIL58 Eight BIIL51s withcommon G and OutputEnable (page 312)
X X
BIIL61 1-bit bidirect pin withlatched input, invertedoutput, and inverted G(page 313)
X X X
BIIL64 Four BIIL61s with commonG and Output Enable(page 313)
X X
BIIL68 Eight BIIL61s withcommon G and OutputEnable (page 313)
X X
BIIL71 1-bit bidirect pin withlatched input, active lowenable, and inverted G(page 314)
X X X
BIIL74 Four BIIL71s with commonG and Output Enable(page 314)
X X
BIIL78 Eight BIIL71s withcommon G and OutputEnable (page 314)
X X
BIIL81 1-bit bidirect pin withlatched input, invertedoutput, active low enable,and inverted G (page 315)
X X X
BIIL84 Four BIIL81s with commonG and Output Enable(page 315)
X X
BIIL88 Eight BIIL81s withcommon G and OutputEnable (page 315)
X X
BIN27 Binary-7-segment decoderwith enable (page 116)
X X X X X
BUF Single input buffer(page 329)
X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 22
Quick Reference Macro Table
CBD11 1-bit down counter withasync clear, CAI, and CAO(page 125)
X X X X X
CBD12 2-bit down counter withasync clear, CAI, and CAO(page 125)
X X X X X
CBD14 4-bit down counter withasync clear, CAI, and CAO(page 125)
X X X X X
CBD18 8-bit down counter withasync clear, CAI, and CAO(page 125)
X X X X X
CBD21 1-bit down counter withasynchronous clear,enable, CAI, and CAO(page 131)
X X X X X
CBD22 2-bit down counter withasynchronous clear,enable, CAI, and CAO(page 131)
X X X X X
CBD24 4-bit down counter withasynchronous clear,enable, CAI, and CAO(page 131)
X X X X X
CBD28 8-bit down counter withasynchronous clear,enable, CAI, and CAO(page 131)
X X X X X
CBD31 1-bit down counter withasynchronous clear,enable, parallel data load,sync preset, CAI, and CAO(page 137)
X X X X X
CBD32 2-bit down counter withasynchronous clear,enable, parallel data load,sync preset, CAI, and CAO(page 137)
X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 23
Quick Reference Macro Table
CBD34 4-bit down counter withasynchronous clear,enable, parallel data load,sync preset, CAI, and CAO(page 137)
X X X X X
CBD38 8-bit down counter withasynchronous clear,enable, parallel data load,sync preset, CAI, and CAO(page 137)
X X X X X
CBD41 1-bit down counter withsynchronous clear, enable,parallel data load,synchronous preset, CAI,and CAO (page 144)
X X X X X
CBD42 2-bit down counter withsynchronous clear, enable,parallel data load,synchronous preset, CAI,and CAO (page 144)
X X X X X
CBD44 4-bit down counter withsynchronous clear, enable,parallel data load,synchronous preset, CAI,and CAO (page 144)
X X X X X
CBD48 8-bit down counter withsynchronous clear, enable,parallel data load,synchronous preset, CAI,and CAO (page 144)
X X X X X
CBD516 16-bit down counter withasynchronous clear andenable (page 151)
X X X X X
CBD616 16-bit down counter withasynchronous clear, CAO,and enable (page 151)
X X X X X
CBU11 1-bit up counter withasynchronous clear, CAI,and CAO (page 161)
X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 24
Quick Reference Macro Table
CBU12 2-bit up counter withasynchronous clear, CAI,and CAO (page 161)
X X X X X
CBU14 4-bit up counter withasynchronous clear, CAI,and CAO (page 161)
X X X X X
CBU18 8-bit up counter withasynchronous clear, CAI,and CAO (page 161)
X X X X X
CBU21 1-bit up counter withasynchronous clear,enable, CAI, and CAO(page 167)
X X X X X
CBU22 2-bit up counter withasynchronous clear,enable, CAI, and CAO(page 167)
X X X X X
CBU24 4-bit up counter withasynchronous clear,enable, CAI, and CAO(page 167)
X X X X X
CBU28 8-bit up counter withasynchronous clear,enable, CAI, and CAO(page 167)
X X X X X
CBU31 1-bit up counter withasynchronous clear,enable, parallel data load,synchronous preset, CAI,and CAO (page 173)
X X X X X
CBU32 2-bit up counter withasynchronous clear,enable, parallel data load,synchronous preset, CAI,and CAO (page 173)
X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 25
Quick Reference Macro Table
CBU34 4-bit up counter withasynchronous clear,enable, parallel data load,synchronous preset, CAI,and CAO (page 173)
X X X X X
CBU38 8-bit up counter withasynchronous clear,enable, parallel data load,synchronous preset, CAI,and CAO (page 173)
X X X X X
CBU41 1-bit up counter withsynchronous clear, enable,parallel data load,synchronous preset, CAI,and CAO (page 180)
X X X X X
CBU42 2-bit up counter withsynchronous clear, enable,parallel data load,synchronous preset, CAI,and CAO (page 180)
X X X X X
CBU44 4-bit up counter withsynchronous clear, enable,parallel data load,synchronous preset, CAI,and CAO (page 180)
X X X X X
CBU48 8-bit up counter withsynchronous clear, enable,parallel data load,synchronous preset, CAI,and CAO (page 180)
X X X X X
CBU516 16-bit up counter withasynchronous clear andenable (page 187)
X X X X X
CBU616 16-bit up counter withasynchronous clear,enable, and CAO(page 187)
X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 26
Quick Reference Macro Table
CBU716 16-bit up counter withasynchronous clear,enable, parallel data loadand carry out for 3000device (page 196)
X X X
CBUD1 1-bit up/down counter withasync clear, sync clear,enable, parallel data load,sync preset, CAI, and CAO(page 202)
X X X X X
CBUD2 2-bit up/down counter withasync clear, sync clear,enable, parallel data load,sync preset, CAI, and CAO(page 202)
X X X X X
CBUD4 4-bit up/down counter withasync clear, sync clear,enable, parallel data load,sync preset, CAI, and CAO(page 202)
X X X X X
CBUD8 8-bit up/down counter withasync clear, sync clear,enable, parallel data load,sync preset, CAI, and CAO(page 202)
X X X X X
CDD14 4-bit decade down counterwith async clear, enable,and parallel data load(page 212)
X X X X X
CDD18 8-bit decade down counterwith async clear, enable,and parallel data load(page 212)
X X X X X
CDD24 4-bit decade down counterwith sync clear, enable,and parallel data load(page 218)
X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 27
Quick Reference Macro Table
CDD28 8-bit decade down counterwith sync clear, enable,and parallel data load(page 218)
X X X X X
CDD34 4-bit decade down counterwith asynchronous clear,enable, and parallel dataload, CAI, and CAO(page 224)
X X X X X
CDD38 8-bit decade down counterwith asynchronous clear,enable, and parallel dataload, CAI, and CAO(page 224)
X X X X X
CDD44 4-bit decade down counterwith synchronous clear,enable, parallel data load,CAI, and CAO (page 230)
X X X X X
CDD48 8-bit decade down counterwith synchronous clear,enable, parallel data load,CAI, and CAO (page 230)
X X X X X
CDU14 4-bit decade up counterwith async clear, enable,and parallel data load(page 234)
X X X X X
CDU18 8-bit decade up counterwith async clear, enable,and parallel data load(page 234)
X X X X X
CDU24 4-bit decade up counterwith sync clear, enable,and parallel data load(page 240)
X X X X X
CDU28 8-bit decade up counterwith sync clear, enable,and parallel data load(page 240)
X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 28
Quick Reference Macro Table
CDU34 4-bit decade up counterwith asynchronous clear,enable, parallel data load,CAI, and CAO (page 246)
X X X X X
CDU38 8-bit decade up counterwith asynchronous clear,enable, parallel data load,CAI, and CAO (page 246)
X X X X X
CDU44 4-bit decade up counterwith synchronous clear,enable, parallel data load,CAI, and CAO (page 252)
X X X X X
CDU48 4-bit decade up counterwith synchronous clear,enable, parallel data load,CAI, and CAO (page 252)
X X X X X
CDUD4 4-bit up/down decadecounter with async clear,sync clear, enable, andparallel data load(page 258)
X X X X X
CDUD8 8-bit up/down decadecounter with async clear,sync clear, enable, andparallel data load(page 258)
X X X X X
CDUD4c 4-bit up/down decadecounter with async clear,sync clear, enable, andparallel data load, CAI,and CAO (page 268)
X X X X X
CDUD8c 8-bit up/down decadecounter with async clear,sync clear, enable, paralleldata load, CAI, and CAO(page 268)
X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 29
Quick Reference Macro Table
CGD14 4-bit grey code downcounter with asynchronousclear, synchronous preset,enable, and parallel dataload (page 278)
X X X X X
CGD24 4-bit grey code downcounter with synchronousclear, synchronous preset,enable, and parallel dataload (page 281)
X X X X X
CGU14 4-bit grey code up counterwith asynchronous clear,synchronous preset,enable, and parallel dataload (page 284)
X X X X X
CGU24 4-bit grey code up counterwith synchronous clear,synchronous preset,enable, and parallel dataload (page 288)
X X X X X
CGUD4 4-bit grey code up/downcounter with async clear,sync clear and preset,enable, and parallel dataload (page 291)
X X X X X
CMP2 2-bit equality comparator(page 78)
X X X X X
CMP4 4-bit equality comparator(page 78)
X X X X X
CMP8 8-bit equality comparator(page 78)
X X X X X
DEC2 1-2 decoder (page 118) X X X X X
DEC2E 1-2 decoder with enable(page 118)
X X X X X
DEC3 1-3 decoder (page 119) X X X X X
DEC3E 1-3 decoder with enable(page 119)
X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 30
Quick Reference Macro Table
DEC4 1-4 decoder (page 120) X X X X X
DEC4E 1-4 decoder with enable(page 120)
X X X X X
DMUX2 1 of 2 output dmux(page 336)
X X X X X
DMUX2E 1 of 2 output dmux withenable (page 336)
X X X X X
DMUX4 1 of 4 output dmux(page 337)
X X X X X
DMUX4E 1 of 4 output dmux withenable (page 337)
X X X X X
DMUX22 Dual 1 of 2 output dmuxwith common select line(page 353)
X X X X X
DMUX22E Dual 1 of 2 output dmuxwith common select lineand enable (page 353)
X X X X X
DMUX24 Dual 1 of 4 output dmuxwith common select line(page 354)
X X X X X
DMUX24E Dual 1 of 4 output dmuxwith common select lineand enable (page 354)
X X X X X
DMUX42 Quad 1 of 2 output dmuxwith common select line(page 355)
X X X X X
DMUX42E Quad 1 of 2 output dmuxwith common select lineand enable (page 355)
X X X X X
DMUX44 Quad 1 of 4 output dmuxwith common select line(page 356)
X X X X X
DMUX44E Quad 1 of 4 output dmuxwith common select lineand enable (page 356)
X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 31
Quick Reference Macro Table
DMUX82 Octal 1 of 2 output dmuxwith common select line(page 357)
X X X X X
DMUX82E Octal 1 of 2 output dmuxwith common select lineand enable (page 357)
X X X X X
F3SUB 3-bit full subtractor withpropagate-generate(page 91)
X X X X X
FD11 1-bit D flip-flop (page 359) X X X X X
FD14 4-bit D flip-flop (page 359) X X X X X
FD18 8-bit D flip-flop (page 359) X X X X
FD21 1-bit D flip-flop with asyncclear (page 360)
X X X X X
FD24 4-bit D flip-flop with asyncclear (page 360)
X X X X X
FD28 8-bit D flip-flop with asyncclear (page 360)
X X X X
FD31 1-bit D flip-flop with syncpreset (page 361)
X X X X X
FD34 4-bit D flip-flop with syncpreset (page 361)
X X X X X
FD38 8-bit D flip-flop with syncpreset (page 361)
X X X X
FD41 1-bit D flip-flop withasynchronous cleardominant over sync preset(page 362)
X X X X X
FD44 4-bit D flip-flop withasynchronous cleardominant over sync preset(page 362)
X X X X X
FD48 8-bit D flip-flop with asyncclear dominant over syncpreset (page 362)
X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 32
Quick Reference Macro Table
FD51 1-bit D flip-flop with syncpreset dominant over syncclear (page 363)
X X X X X
FD54 4-bit D flip-flop with syncpreset dominant over syncclear (page 363)
X X X X X
FD58 8-bit D flip-flop withsynchronous presetdominant oversynchronous clear(page 363)
X X X X
FD61 1-bit flip-flop with scan(page 364)
X X X X
FD64 4-bit flip-flop with scan(page 364)
X X X X
FD68 8-bit flip-flop with scan(page 364)
X X X X
FD71 1-bit D flip-flop with scanand asynchronous clear(page 365)
X X X X
FD74 4-bit D flip-flop with scanand asynchronous clear(page 365)
X X X X
FD78 8-bit D flip-flop with scanand asynchronous clear(page 365)
X X X X
FD81 1-bit D flip-flop with scanand synchronous preset(page 366)
X X X X
FD84 4-bit D flip-flop with scanand synchronous preset(page 366)
X X X X
FD88 8-bit D flip-flop with scanand synchronous preset(page 366)
X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 33
Quick Reference Macro Table
FD91 1-bit D flip-flop with scanand async clear dominantover sync preset(page 367)
X X X X
FD94 4-bit D flip-flop with scanand async clear dominantover sync preset(page 367)
X X X X
FD98 8-bit D flip-flop with scanand async clear dominantover sync preset(page 367)
X X X X
FDA1 1-bit D flip-flop with scanand sync preset dominantover async clear(page 368)
X X X X
FDA4 4-bit D flip-flop with scanand sync preset dominantover async clear(page 368)
X X X X
FDA8 8-bit D flip-flop with scanand sync preset dominantover async clear(page 368)
X X X X
FJK11 JK flip-flop (page 369) X X X X X
FJK21 JK flip-flop with asyncclear (page 369)
X X X X X
FJK31 JK flip-flop with scan(page 370)
X X X X
FJK41 JK flip-flop with scan andasync clear (page 370)
X X X X
FJK51 JK flip-flop with asyncclear and sync preset(page 371)
X X X X X
FT11 Toggle flip-flop with asyncclear (page 372)
X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 34
Quick Reference Macro Table
FT21 Toggle flip-flop with syncclear and preset, presetdominant (page 372)
X X X X X
IB11 1-bit input pin (page 316) X X X X X
ID11 1-bit registered input pin(page 317)
X X X X
ID14 Four ID11s with commonclock (page 317)
X X X
ID18 Eight ID11s with commonclock (page 317)
X X X
ID21 1-bit registered input pinwith inverted clock(page 318)
X X X
ID24 Four ID21s with commonclock (page 318)
X X
ID28 Eight ID21s with commonclock (page 318)
X X
IL11 1-bit input pin with D latchon input (page 319)
X X X X
IL14 Four IL11s with common G(page 319)
X X X
IL18 Eight IL11s with commonG (page 319)
X X X
IL21 1-bit input pin with D latchon input, inverted enable(page 320)
X X X
IL24 Four IL21s with common G(page 320)
X X
IL28 Eight IL21s with commonG (page 320)
X X
INV Single input inverter(page 329)
X X X X X
LD11 1-bit D latch (page 373) X X X X X
LD14 4-bit D latch (page 373) X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 35
Quick Reference Macro Table
LD18 8-bit D latch (page 373) X X X X
LD21 1-bit D latch with asyncclear (page 374)
X X X X X
LD24 4-bit D latch with asyncclear (page 374)
X X X X X
LD28 8-bit D latch with asyncclear (page 374)
X X X X
LD31 1-bit D latch with asyncpreset (page 375)
X X X X X
LD34 4-bit D latch with asyncpreset (page 375)
X X X X X
LD38 8-bit D latch with asyncpreset (page 375)
X X X X
LD41 1-bit D latch with asyncclear dominant over asyncpreset (page 376)
X X X X X
LD44 4-bit D latch with asyncclear dominant over asyncpreset (page 376)
X X X X X
LD48 8-bit D latch with asyncclear dominant over asyncpreset (page 376)
X X X X
LD51 1-bit D latch with asyncpreset dominant overasync clear (page 377)
X X X X X
LD54 4-bit D latch with asyncpreset dominant overasync clear (page 377)
X X X X X
LD58 8-bit D latch with asyncpreset dominant overasync clear (page 377)
X X X X
LD61 1-bit D latch with scan(page 378)
X X X X
LD64 4-bit D latch with scan(page 378)
X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 36
Quick Reference Macro Table
LD68 8-bit D latch with scan(page 378)
X X X X
LD71 1-bit D latch with scan andasynchronous clear(page 379)
X X X X
LD74 4-bit D latch with scan andasynchronous clear(page 379)
X X X X
LD78 8-bit D latch with scan andasynchronous clear(page 379)
X X X X
LD81 1-bit D latch with scan andasynchronous preset(page 380)
X X X X
LD84 4-bit D latch with scan andasynchronous preset(page 380)
X X X X
LD88 8-bit D latch with scan andasynchronous preset(page 380)
X X X X
LD91 1-bit D latch with scan andasync clear dominant overasync preset (page 381)
X X X X
LD94 4-bit D latch with scan andasync clear dominant overasync preset (page 381)
X X X X
LD98 8-bit D latch with scan andasync clear dominant overasync preset (page 381)
X X X X
LDA1 1-bit D latch with scan andasync preset dominantover async clear(page 382)
X X X X
LDA4 4-bit D latch with scan andasync preset dominantover async clear(page 382)
X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 37
Quick Reference Macro Table
LDA8 8-bit D latch with scan andasync preset dominantover async clear(page 382)
X X X X
LSR1 Simple SR latch(page 383)
X X X X X
LSR2 SR latch with OR on S andR inputs (page 383)
X X X X X
LXOR2 XOR gate (page 334) X X X X
MAG2 2-bit magnitudecomparator (page 79)
X X X X X
MAG4 4-bit magnitudecomparator (page 79)
X X X X X
MAG8 8-bit magnitudecomparator (page 79)
X X X X X
MULT24 2-bit by 4-bit multiplier(page 81)
X X X X X
MULT44 4-bit by 4-bit multiplier(page 81)
X X X X X
MUX2 1 of 2 input mux(page 336)
X X X X X
MUX2E 1 of 2 input mux withenable (page 336)
X X X X X
MUX4 1 of 4 input mux(page 337)
X X X X X
MUX4E 1 of 4 input mux withenable (page 337)
X X X X X
MUX8 1 of 8 input mux(page 338)
X X X X X
MUX8E 1 of 8 input mux withenable (page 338)
X X X X X
MUX16 1 of 16 input mux for 3000device only (page 339)
X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 38
Quick Reference Macro Table
MUX16E 1 of 16 input mux withenable for 3000 deviceonly (page 339)
X X X
MUX22 Dual 1 of 2 input mux withcommon select line(page 343)
X X X X X
MUX22E Dual 1 of 2 input mux withcommon select line andenable (page 343)
X X X X X
MUX24 Dual 1 of 4 input mux withcommon select line(page 344)
X X X X X
MUX24E Dual 1 of 4 input mux withcommon select line andenable (page 344)
X X X X X
MUX42 Quad 1 of 2 input mux withcommon select line(page 345)
X X X X X
MUX42E Quad 1 of 2 input mux withcommon select line andenable (page 345)
X X X X X
MUX44 Quad 1 of 4 input mux withcommon select line(page 346)
X X X X X
MUX44A Quad 1 of 4 input mux withcommon select line(page 349)
X X X X X
MUX44AE Quad 1 of 4 input mux withcommon select line andenable for 3000 deviceonly (page 349)
X X X
MUX44E Quad 1 of 4 input mux withcommon select line andenable (page 346)
X X X X X
MUX82 Octal 1 of 2 input mux withcommon select line(page 350)
X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 39
Quick Reference Macro Table
MUX82E Octal 1 of 2 input mux withcommon select line andenable (page 350)
X X X X X
NAND2 throughNAND12 &NAND16
2 through 12 and 16-inputNAND gate (page 330)
X X X X X
NOR2 throughNOR12 &NOR16
2 though 12 and 16-inputNOR gate (page 331)
X X X X X
OB11 1-bit output pin (page 321) X X X X X
OB21 1-bit inverting output pin(page 322)
X X X X X
OB24 Four OB21s (page 322) X X X X
OB28 Eight OB21s (page 322) X X X X
OR2 throughOR12 & OR16
1 through 12 and 16-inputOR gate (page 332)
X X X X X
OT11 1-bit 3-state output pin(page 323)
X X X X X
OT14 Four OT11s with commonOutput Enable (page 323)
X X X X
OT18 Eight OT11s with commonOutput Enable (page 323)
X X X X
OT21 1-bit inverting 3-stateoutput pin (page 324)
X X X X X
OT24 Four OT21s with commonOutput Enable (page 324)
X X X X
OT28 Eight OT21s with commonOutput Enable (page 324)
X X X X
OT31 1-bit 3-state output pinwith active low enable(page 325)
X X X X X
OT34 Four OT31s with commonOutput Enable (page 325)
X X X X
OT38 Eight OT31s with commonOutput Enable (page 325)
X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 40
Quick Reference Macro Table
OT41 1-bit inverting 3-stateoutput pin with active lowenable (page 326)
X X X X X
OT44 Four OT41s with commonOutput Enable (page 326)
X X X X
OT48 Eight OT41s with commonOutput Enable (page 326)
X X X X
PG1 1-bit propagate-generate(page 85)
X X X X X
PG2 2-bit propagate-generate(page 85)
X X X X X
PG3 3-bit propagate-generate(page 85)
X X X X X
PG4 4-bit propagate-generate(page 85)
X X X X X
PREN8 7 line-3 line priorityencoder (page 121)
X X X X X
PREN8E 7 line-3 line priorityencoder with enable(page 121)
X X X X X
PREN10 9 line-4 line priorityencoder (page 122)
X X X X X
PREN10E 9 line-4 line priorityencoder with enable(page 122)
X X X X X
PREN16 15 line-4 line priorityencoder (page 123)
X X X X X
PREN16E 15 line-4 line priorityencoder with enable(page 123)
X X X X X
SRR11 1-bit right shift register withasynchronous reset(page 384)
X X X X X
SRR14 4-bit right shift register withasynchronous reset(page 384)
X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 41
Quick Reference Macro Table
SRR18 8-bit right shift register withasynchronous reset(page 384)
X X X X X
SRR21 1-bit right shift register withasynchronous reset andenable (page 388)
X X X X X
SRR24 4-bit right shift register withasynchronous reset andenable (page 388)
X X X X X
SRR28 8-bit right shift register withasynchronous reset andenable (page 388)
X X X X X
SRR31 1-bit right shift register withasynchronous reset,enable, parallel data load,and synchronous preset(page 392)
X X X X X
SRR34 4-bit right shift register withasynchronous reset,enable, parallel data load,and synchronous preset(page 392)
X X X X X
SRR38 8-bit right shift register withasynchronous reset,enable, parallel data load,and synchronous preset(page 392)
X X X X X
SRR41 1-bit right shift register withsynchronous reset,enable, parallel data load,and synchronous preset,(page 396)
X X X X X
SRR44 4-bit right shift register withsynchronous reset,enable, parallel data load,and synchronous preset(page 396)
X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 42
Quick Reference Macro Table
SRR48 8-bit right shift register withsynchronous reset,enable, parallel data load,and synchronous preset(page 396)
X X X X X
SRRL1 1-bit right/left shift registerwith asynchronous reset,enable, parallel data load,and synchronous preset(page 400)
X X X X X
SRRL4 4-bit right/left shift registerwith asynchronous reset,enable, parallel data load,and synchronous preset(page 400)
X X X X X
SRRL8 8-bit right/left shift registerwith asynchronous reset,enable, parallel data load,and synchronous preset(page 400)
X X X X X
SUBF1 1-bit full subtractor(page 91)
X X X X X
SUBF2 2-bit full subtractor(page 91)
X X X X X
SUBF4 4-bit full subtractor(page 91)
X X X X X
SUBF8 8-bit full subtractor(page 91)
X X X X X
SUBF8A 8-bit full subtractor withpropagate-generate(page 91)
X X X X X
SUBF16A 16-bit full subtractor withpropagate-generate(page 91)
X X X X X
SUBH1 1-bit half subtractor(page 102)
X X X X X
SUBH2 2-bit half subtractor(page 102)
X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 43
Quick Reference Macro Table
* CAO is a 2-level output (1 logic level and 1 CO delay).
SUBH3 3-bit half subtractor(page 102)
X X X X X
SUBH4 4-bit half subtractor(page 102)
X X X X X
SUBH8 8-bit half subtractor(page 102)
X X X X X
SUBH8A 8-bit half subtractor builtwith propagate-generatesubmacro (page 102)
X X X X X
SUBH16A 16-bit half subtractor builtwith propagate-generatesubmacro (page 102)
X X X X X
XNOR2 Input XNOR gate(page 333)
X X X X X
XNOR3 Input XNOR gate(page 333)
X X X X X
XNOR4 Input XNOR gate(page 333)
X X X X X
XNOR7 Input XNOR gate(page 333)
X X X X X
XNOR8 Input XNOR gate(page 333)
X X X X X
XNOR9 Input XNOR gate(page 333)
X X X X X
XOR2 Input XOR gate(page 334)
X X X X X
XOR3 Input XOR gate(page 334)
X X X X X
XOR4 Input XOR gate(page 334)
X X X X X
XOR8 Input XOR gate(page 334)
X X X X X
XOR9 Input XOR gate(page 334)
X X X X X
Macro Description 1K 2K 3K pDSispDS/ispDS+
Macro Library Reference Manual 44
Quick Reference Macro Table
** ADDF8: CO is a 3-level output.*** SUBF8: BO is a 3-level output.
Macro Library Reference Manual 45
Programmable Macro Reference
Programmable Macro ReferenceThe following table provides a quick reference to the programmable macros thatsupport the 6000 device family.
ApplicableDevice
Module MacroName Description
COUNTERS
6192FF6192SM6192DM
C4R4AL Four Counters Up/Dn, 8/16 Bits, Adjacent Load & 4 AdjacentLoad Register File: Odd numbered banks [1, 3, 5, 7] areconfigured as 16-bit counters. Counter sizes can beindependently changed to 8 or 16 bits for each bank. Defaultis 16 bits. Once up or down or counter size options are setand programmed, they cannot be reprogrammed in thedevice. Default is up.
6192FF6192SM6192DM
C4R4PL Four Counters Up/Dn, 8/16 Bits, Parallel Load & 4 BankRegister File: Odd numbered banks [1, 3, 5, 7] are configuredas 16-bit counters. Counter sizes can be independentlychanged to 8 or 16 bits for each bank. Default is 16 bits.Once up or down or counter size options are set andprogrammed, they cannot be reprogrammed in the device.Default is up.
TIMERS
6192FF6192SM6192DM
T4R4AL Four Timers Up/Dn, 8/16 Bits, Adjacent Load & 4 AdjacentLoad Register File: Odd numbered banks [1, 3, 5, 7] areconfigured as 16-bit timers. Timer sizes can beindependently changed to 8 or 16 bits for each bank. Defaultis 16 bits. Once up or down or timer size options are set andprogrammed, they cannot be reprogrammed in the device.Default is up.
6192FF6192SM6192DM
T4R4PL Four Timers Up/Dn, 8/16 Bits, Parallel Load & 4 BankRegister File: Odd numbered banks [1, 3, 5, 7] are configuredas 16-bit timers. Timer sizes can be independently changedto 8 or 16 bits for each bank. Default is 16 bits. Once up ordown or timer size options are set and programmed, theycannot be reprogrammed in the device. Default is up.
6192FF6192SM6192DM
T4R4CPV Four Timers Up/Dn, 8/16 Bits, Custom Preset Value & 4 BankRegister File: Odd numbered banks [1, 3, 5, 7] are configuredas 16-bit timers. Default is zero. Timer sizes can beindependently changed to 8 or 16 bits for each bank. Defaultis 16 bits. Once up or down or timer size options are set andprogrammed, they cannot be reprogrammed in the device.Default is up.
Macro Library Reference Manual 46
Programmable Macro Reference
SHIFT REGISTERS
6192FF6192SM6192DM
PSSR8X16 8x16 Parallel to Serial Shift Register: 8-bank, 16-bit,parallel data-in, serial data-out shift register.
6192FF6192SM6192DM
SSSR128 8x16 Serial to Serial Shift Register: 8-bank, 16-bit, paralleldata-in, serial data-out shift register.
6192FF6192SM6192DM
SPSR8X16 8x16 Serial to Parallel Shift Register: 8-bank,16-bit,parallel data-in, serial data-out shift register.
6192FF6192SM6192DM
RF8X16 8x16 Register File: 8-bank, 16-bit, parallel data-in, serialdata-out shift register.
FIFOS
6192FF FIFO1 256x18: Size = 1•256•18; Port = A -> B
6192FF FIFO2 256x18: Size = 1•256•18; Port = B -> A
6192FF FIFO3 512x9: Size = 1•512•9; Port = A -> B
6192FF FIFO4 512x9: Size = 1•512•9; Port = B -> A
RAMS
6192SMRAM1
256x18 single port using port A: Size = 1•256•18; Port = A;Word Size = 18
6192SMRAM2
256x18 single port using port B: Size = 1•256•18; Port = B;Word Size = 18
6192SMRAM3
256x18 single port using port A with 9-bit write:Size = 1•256•18; Port = A; Word Size = 9
6192SMRAM4
256x18 single port using port B with 9-bit Write:Size = 1•256•18; Port = B; Word Size = 9
6192SMRAM5
512x9 single port using port A: Size = 1•512•9; Port = A;Word Size = 9
6192SMRAM6
512x9 single port using port B: Size = 1•512•9; Port = B;Word Size =9
ApplicableDevice
Module MacroName Description
Macro Library Reference Manual 47
Programmable Macro Reference
6192SMRAM7
Two 128x18 single port: Size = 2•128•18; Port = A and B;Word Size = 18
6192SMRAM8
Two 128x18 single port with 9-bit write: Size = 2•128•18;Port = A and B; Word Size = 9
6192SMRAM9
Two 256x9 single port: Size = 2•256•9; Port = A and B;Word Size = 9
6192DMRAM10
256x18 dual port: Size = 1•256•18; Port = A and B; WordSize = 18
6192DMRAM11
256x18 dual port with 9-bit write: Size = 1•256•18; Port = Aand B; Word Size = 9
6192DMRAM12
512x9 dual port: Size = 1•512•9; Port = A and B;Word Size = 9
ApplicableDevice
Module MacroName Description
Macro Library Reference Manual 48
Arithmetic Functions
This chapter contains information on the following macros:
■ Adders
■ Comparators
■ Multipliers
■ Propagate-Generate
■ Subtractors
Macro Library Reference Manual 49
Adders
ADDF1, ADDF2, F3ADD, ADDF4,ADDF8, ADDF8A & ADDF16A
Function:
ADDF1: 1-bit full adder.ADDF2: 2-bit full adder.F3ADD: 3-bit full adder, with propagate-generate.ADDF4: 4-bit full adder.ADDF8: 8-bit full adder.ADDF8A: 8-bit full adder built with propagate-generate
submacros.ADDF16A: 16-bit full adder built with propagate-generate
submacros.
Availability: ADDF1, ADDF2, F3ADD, ADDF4, ADDF8, ADDF8A,and ADDF16A are for pDS, ispDS, and ispDS+.
Additional symbols appear on the following page.
Type:
Soft: ADDF1, ADDF2, F3ADD, ADDF8A, ADDF16AHard: ADDF4, ADDF8
ADDF1
ADDF2
ADDF4
Z0
CO
A0
B0
CI
CO
Z1
Z0A1
CI
B1
B0
A0
Z1
Z0
Z2
Z3
CO
CI
A2
A3
B0
B1
B2
B3
A1
A0
F3ADD
CI
A0
A1
A2
B0
B1
B2
Z0
Z1
Z2
G012
P012
Z5
Z4
Z6
Z7
CO
Z1
Z0
Z2
Z3
ADDF8
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
CI
Macro Library Reference Manual 50
Logic Resources – pDS:
* Z0: 4 PT CO: 3 PT** Z0: 4 PT Z1: 7 PT CO: 7 PT*** Z0: 3 PT Z1: 7 PT Z2: 15 PT
G012: 7 PT P012: 3 PT**** Z0: 4 PT Z1: 7 PT Z2: 4 PT
Z3: 7 PT CO: 7 PT TCO: 7 PT***** Z0: 2 PT Z1: 3 PT Z2: 4 PT
Z3: 5 PT Z4: 6 PT Z5: 7 PTZ6: 7 PT Z7: 7 PT CO: 6 PTCA: 3 PT CB: 3 PT CC: 7 PTG0-G6: 1 PT P0-P7: 2 PT
****** Z0: 3 PT Z1: 7 PT Z2: 15 PTZ3: 3 PT Z4: 7 PT Z5: 15 PTZ6: 4 PT Z7: 7 PT CO: 7 PT
******* Z0: 3 PT Z1: 7 PT Z2: 15 PTZ3: 3 PT Z4: 7 PT Z5: 15 PTZ6: 3 PT Z7: 7 PT Z8: 15 PTZ9: 3 PT Z10: 7 PT Z11: 15 PTZ12: 3 PT Z13: 7 PT Z14: 15 PTZ15: 4 PT CO: 3 PT
+ (CO is a 3-level output).
Macro PT GLB Output Level
ADDF1 * .5 2 1ADDF2 ** 1 3 1F3ADD *** 2 5 1ADDF4 **** 2 6 2ADDF8 ***** 7 27 2+
ADDF8A ****** 5.5 15 1ADDF16A ******* 11.75 32 1
ADDF16A
CI
A0
A1
A2
A3
A4
A5
A12
A6
A7
A8
A9
A10
A11
Z0
Z1
Z2
Z3
Z4
Z5
Z6
A15
A13
A14
Z7
CO
B0
B1
B2
B3
B4
B5
B6
B11
B7
B8
B9
B10
B14
B12
B13
B15
Z8
Z9
Z10
Z11
Z12
Z13
Z14
Z15
ADDF8A
C1A0A1A2A3A4A5
B4
A6A7B0B1B2B3
Z0Z1Z2Z3Z4Z5Z6
B7
B5B6
Z7
C1
CI
A0
A1
A2
A3
A4A5
B4
A6
A7
B0
B1
B2
B3
Z0
Z1
Z2
Z3
Z4
Z5
Z6
B7
B5
B6
Z7
CO
Macro Library Reference Manual 51
Macro Port Definition:
ADDF1 (Z0,CAO,A0,B0,CI);ADDF2 (Z0,Z1,CO,A0,A1,B0,B1,CI);F3ADD ([Z0..Z2],G012,P012,A0,A1,A2,B0,B1,B2,CI);
F3ADD_1 (Z0,Z1,G012,A0,A1,A2,B0,B1,B2,CI);F3ADD_2 (Z2,P012,A0,A1,A2,B0,B1,B2,CI);
ADDF4 ([Z0..Z3],CO,[A0..A3],[B0..B3],CI);ADDF4_1 (Z0,Z1,TCO,A0,A1,B0,B1,CI);ADDF4_2 (Z2,Z3,CO,A2,A3,B2,B3,TCO);
ADDF8 ([Z0..Z7],CO,[A0..A7],[B0..B7],CI);ADDF8_1 (CO,[P0..P7],[G0..G3],CC,CI);ADDF8_2 (Z7,[P0..P7],[G0..G3],A3,B3,CI,CA);ADDF8_3 (Z6,[P0..P6],G0,G1,A0,A2,B0,B2,CI,CB);ADDF8_4 (Z5,[P0..P6],G0,G1,G3,A2,A4,A6,B2,B4,B6,CI);ADDF8_5 (Z2,Z4,[P0..P4],[G0..G2],G4,A1,A3,A4,B1,B3,B4,CI);ADDF8_6 (Z3,[P0..P3],G1,G2,G5,G6,A0,A1,A5,A6,B0,B1,B5,B6,CI);ADDF8_7 (Z0,P7,G2,CC,P0,P5,P6,G4,G5,G6,A2,A7,B2,B7,CI);ADDF8_8 (Z1,CA,CB,P5,P0,P1,P4,P6,[G3..G6],A0,A5,B0,B5,CI);
ADDF8A ([Z0..Z7],CO,[A0..A7],[B0..B7],CI);ADDF8A_1 (Z0,Z1,G012,A0,A1,A2,B0,B1,B2,CI);ADDF8A_2 (Z2,P012,A0,A1,A2,B0,B1,B2,CI);ADDF8A_3 (C2,CCI,CI,P012,P345,G012,G345);ADDF8A_4 (Z3,Z4,G345,A3,A4,A5,B3,B4,B5,C2);ADDF8A_5 (Z5,P345,A3,A4,A5,B3,B4,B5,C2);ADDF8A_6 (CO,Z6,Z7,A6,A7,B6,B7,CCI);
ADDF16A ([Z0..Z15],CO,[A0..A15],[B0..B15],CI);ADDF16A_1 (Z0,Z1,G012,A0,A1,A2,B0,B1,B2,CI);ADDF16A_2 (Z2,P012,A0,A1,A2,B0,B1,B2,CI);ADDF16A_3 (Z3,Z4,G345,A3,A4,A5,B3,B4,B5,C2);ADDF16A_4 (Z5,P345,A3,A4,A5,B3,B4,B5,C2);ADDF16A_5 (Z6,Z7,G678,A6,A7,A8,B6,B7,B8,C5);ADDF16A_6 (Z8,P678,A6,A7,A8,B6,B7,B8,C5);ADDF16A_7 (Z9,Z10,G911,A9,A10,A11,B9,B10,B11,C8);ADDF16A_8 (Z11,P911,A9,A10,A11,B9,B10,B11,C8);ADDF16A_9 (Z12,Z13,G1214,A12,A13,A14,B12,B13,B14,C11);ADDF16A_10 (Z14,P1214,A12,A13,A14,B12,B13,B14,C11);ADDF16A_11 (Z15,CO,C2,CI,P012,G012,A15,B15,C14);ADDF16A_12 (C5,C8,C11,C14,C2,P345,G345,P678,G678,
P911,G911,P1214,G1214);
Macro Library Reference Manual 52
Truth Table:
The truth table below applies to ADDF1, ADDF2, ADDF4, ADDF8,ADDF8A, and ADDF16A. The value of CO depends on the sum ofA+B and n.
* If A+B<2n, CO = 0. If A+B>2n, CO = 1.** If A+B+1<2n, CO = 0. If A+B+1>2n, CO = 1.
The truth table for F3ADD is shown below.
* If A+B<2n, G012 = 0. If A+B>2n, G012 = 1.** If A+B+1<2n, G012 = 0. If A+B+1>2n, G012 = 1.*** P012 = (A0+B0) (A1+B1) (A2+B2).
Input Output
An-1~A0 Bn-1~B0 CI Zn-1~Z0 CO
data data 0 A+B *data data 1 A+B+1 **
Input Output
A2~A0 B2~B0 CI Z2~Z0 G012 P012
data data 0 A+B * ***data data 1 A+B+1 ** ***
Macro Library Reference Manual 53
CI
B0
A0
Z0
CO
ADDF1
Macro Library Reference Manual 54
CI
CI
Z0
Z1
CO
B0
B1
A1
A0
LX2
B0
B1
B1
B0
B0
B1B0
B1
B0
B1
B0
B1
B[0:1]
B0
B1
B1
B0
B1
B0
A0
A0
A0
B0
B1
B[0:1]
B1
B0
B0
B1
B1
B0
A0
A1
A0
A1A1
A1
A0
A0
A1
A0
A1
A0
A[0:1]
A0
A0
A0
CI
ADDF2
Macro Library Reference Manual 55
CI
P012
CI
B1
B0
B2
B0
B2
B[0:2]
B1B1
B2
B2
B2
B1
B0
B1
B0
B0
B1
B0
B1
B1
B0
B0
B0
B2
B1
B1
A1
A0
B0
A2
B2
Z0LX2
LX2 Z1
G012
B0
B1
B2
B[0:2]
B1
B0
B1
B0
B0
B1
B0
B1
B2
A1
A2
A0
A[0:2]
A1
A0
A2
A0
A1
A2
A2
A2
A0
A1
A0
A1
A2
A0
A1
A0
A0
A0
A1
A0
A1
A2
A1
A0
A0
A0
A2
A[0:2]
F3ADD.1
Macro Library Reference Manual 56
A[0:1]
A0
A0
A1
A0
A1
A0
A1
A1
CI
CI
B[0:2]
B0
B0
B0
B1
B1
B2
B2
B2
B2
B2
B2
B2
B0
B1
B1
A[0:2]
A1
A0
A1
A0
A1
A0
A1
A0
A2
B[0:2]
B2
B2
B2
B2
B2
B0
B1
B1
B0
B0
B1
B1
B0
B2
B2
LX2 Z2
F3ADD.2
Macro Library Reference Manual 57
CI
B3
B2
A3
A2
CO
Z3
Z2
Z0
Z1
A0
A1
B0
B1
PRESERVE
A0
B0
B1
CI
A1
ADDF2
Z0
Z1
CO
A0
B0
B1
CI
A1
ADDF2
Z0
Z1
CO
ADDF4
Macro Library Reference Manual 58
G7
PRESERVE
G6
PRESERVE
G5
PRESERVE
G4
PRESERVE
G3
PRESERVE
G2
PRESERVE
G1
PRESERVE
G0
PRESERVE
P7
PRESERVE
P6
PRESERVE
P4
PRESERVE
PRESERVE
P3
PRESERVE
P2
P1
PRESERVE
P0
PRESERVEB0
A0
A3
B3
A2
B2
A1
B1
B4
A4
B5
A5
B6
A6
B7
A7
P5
PRESERVE
ADDF8.1
Macro Library Reference Manual 59
Z5
P1
P2
G1
G0
P0
CI
Z2
G4
CO
P7
G7
G6
P6
G5
P5
G4
G3
P4
G2
P3
P2
G1
P1
G0
P0
CI
CI
P0
G0
P1
G1
P2
G2
P3
G3
P4
P5
LX2
LX2
ADDF8.2
Macro Library Reference Manual 60
P0
Z0
P1
Z1
P7
G6
P6
G5
P5
G4
P4
G3
P3
G2
P2
G1
G0
Z7
CI
LX2
LX2
ADDF8.3
Macro Library Reference Manual 61
Z4
P3
G2
Z3
G3
P4
Z6
P6
G5
P1
G0
P0
P5
G4
G3
P4
G2
P3
P2
G1
CI
P0
G0
P1
G1
P2
G2
P3
P2
G1
P1
G0
P0
CI
CI
LX2
LX2
LX2
ADDF8.4
Macro Library Reference Manual 62
CI
A1
A2
B0
B1
B2
Z1
Z2
Z0A0
Z3
Z4
Z5
B5
B4
B3
A5
A4
A3
G345
P345
P012
G012
A6
A7
B6
B7
Z6
Z7
CO
F3ADD
Z2
Z1
Z0
G012
P012
A0
A1
B2
B1
B0
A2
CI
PGO1
PG1
PGI1
PI1
GI1
F3ADD
Z2
Z1
Z0
G012
P012
A0
A1
B2
B1
B0
A2
CI
PGO2
GI1
PI1
PGI1
PG2
GI2
PI2
A0
B0
B1
CI
A1
ADDF2
Z0
Z1
CO
ADDF8A
Macro Library Reference Manual 63
P012
CI
G678
P678
P911
B15
A15
CO
Z15
P345
G345
G911
Z11
Z10
Z9A9
A10
A11
B9
B10
B11
A12
B13
B14
Z12
Z7
Z6A6
A7
B8
B7
B6
A8 Z8
Z5
A4
A3
A5
B3
B4
B5
Z3
Z4
A1
A2
B0
B1
B2
Z1
Z2
Z0A0
Z13
B12
A14
A13
Z14
G1214
P1214
G012
F3ADD
Z2
Z1
Z0
G012
P012
A0
A1
B2
B1
B0
A2
CI
F3ADD
Z2
Z1
Z0
G012
P012
A0
A1
B2
B1
B0
A2
CI
F3ADD
Z2
Z1
Z0
G012
P012
A0
A1
B2
B1
B0
A2
CI
F3ADD
Z2
Z1
Z0
G012
P012
A0
A1
B2
B1
B0
A2
CI
F3ADD
Z2
Z1
Z0
G012
P012
A0
A1
B2
B1
B0
A2
CI
ADDF1
Z0
CO
A0
B0
CI
PGO1
PG1
PGI1
PI1
GI1
PGO1
PG1
PGI1
PI1
GI1
PGO2
GI1
PI1
PGI1
PG2
GI2
PI2
PGO3
PI3
GI3
PI2
GI2
PI1
PGI1
GI1
PG3
PGO4
PI4
GI4
GI3
PG4
GI1
PGI1
PI1
PI2
PI3
GI2
ADDF16 A
Macro Library Reference Manual 64
ADDH1, ADDH2, ADDH3, ADDH4,ADDH8, ADDH8A, & ADDH16A
Function:
ADDH1: 1-bit half adder.ADDH2: 2-bit half adder.ADDH3: 3-bit half adder.ADDH4: 4-bit half adder.ADDH8: 8-bit half adder.ADDH8A: 8-bit half adder built with propagate-generate
submacros.ADDH16A: 16-bit half adder built with propagate-generate
submacros.
Availability: ADDH1, ADDH2, ADDH3, ADDH4, ADDH8,ADDH8A, and ADDH16A are for pDS, ispDS, and ispDS+.
Additional symbols appear on the following page.
Type:
Soft: ADDH1, ADDH2, ADDH3, ADDH8A, ADDH16AHard: ADDH4, ADDH8
ADDH1
ADDH2
B0
A0 Z0
CO
CO
Z1
Z0A1
B1
B0
A0
ADDH4
Z1
Z0
Z2
Z3
CO
A2
A3
B0
B1
B2
B3
A1
A0
ADDH3
A0
A1
A2
B0
B1
B2
CO
Z1
Z2
Z0
Z5
Z4
Z6
Z7
CO
Z1
Z0
Z2
Z3
ADDH8
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
Macro Library Reference Manual 65
Logic Resources – pDS:
* Z0: 2 PT CO: 1 PT** Z1: 6 PT Z0: 2 PT CO: 3 PT*** Z0: 2 PT Z1: 4 PT
Z2: 9 PT CO: 7 PT**** Z0: 2 PT Z1: 6 PT
Z2: 4 PT Z3: 7 PTCO: 7 PT TCO: 3 PT
***** Z0: 2 PT Z1: 2 PTZ2: 3 PT Z3: 4 PTZ4: 5 PT Z5: 9 PTZ6: 11 PT Z7: 8 PTCO: 7 PT CC: 3 PTG1-G5: 1 PT P1-P7: 2 PT
****** Z0: 2 PT Z1: 4 PT Z2: 9 PTZ3: 3 PT Z4: 7 PT Z5: 15 PTZ6: 4 PT Z7: 7 PT CO: 7
******* Z0: 2 PT Z1: 4 PT Z2: 9 PTZ3: 3 PT Z4: 7 PT Z5: 15 PTZ6: 3 PT Z7: 7 PT Z8: 15 PTZ9: 3 PT Z10: 7 PT Z11: 15 PTZ12: 3 PT Z13: 7 PT Z14: 15 PTZ15: 4 PT CO: 3 PT
Macro PT GLB Output Level
ADDH1 * .5 2 1ADDH2 ** .75 3 1ADDH3 *** 1.25 4 1ADDH4 **** 1.75 6 2ADDH8 ***** 5.5 22 2
ADDH8A ****** 4.5 13 1ADDH16A ******* 10.75 30 1
A0
A1
A2
A3
A4
A5
A12
A6
A7
A8
A9
A10
A11
Z0
Z1
Z2
Z3
Z4
Z5
Z6
A15
A13
A14
Z7
CO
B0
B1
B2
B3
B4
B5
B6
B11
B7
B8
B9
B10
B14
B12
B13
B15
Z8
Z9
Z10
Z11
Z12
Z13
Z14
Z15
ADDH16AADDH8A
Z5
Z4
Z6
Z7
CO
Z1
Z0
Z2
Z3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
Macro Library Reference Manual 66
Macro Port Definition:
ADDH1 (Z0,CO,A0,B0);ADDH2 (Z0,Z1,CO,A0,A1,B0,B1);ADDH3 ([Z0..Z2],CO,A0,A1,A2,B0,B1,B2);
ADDH3_1 (Z0,A0,B0);ADDH3_2 (Z1,Z2,CO,A0,A1,A2,B0,B1,B2);
ADDH4 ([Z0..Z3],CO,[A0..A3],[B0..B3]);ADDH4_1 (Z0,Z1,TCO,A0,A1,B0,B1);ADDH4_2 (Z2,Z3,CO,A2,A3,B2,B3,TCO);
ADDH8 ([Z0..Z7],CO,[A0..A7],[B0..B7]);ADDH8_1 (CO,Z1,Z3,[P1..P7],[G1..G5],A0,B0,CC);ADDH8_2 (Z0,Z2,Z4,Z7,[P1..P7],[G1..G5],A0,A6,B0,B6);ADDH8_3 (Z6,G5,G4,P4,[P1..P3],P5,P6,[G1..G3],A0,A4,A5,B0,B4,B5);ADDH8_4 (Z5,G3,P3,G1,P1,P2,P4,P5,G2,G4,A0,A1,A3,B0,B1,B3);ADDH8_5 (G2,P2,P1,A1,A2,B1,B2);ADDH8_6 (P7,P6,P5,CC,[A5..A7],[B5..B7]);
ADDH8A ([Z0..Z7],CO,[A0..A7],[B0..B7]);ADDH8A_1 (Z0,A0,B0,C2,CCI,P345,G345);ADDH8A_2 (Z1,Z2,C2,A0,A1,A2,B0,B1,B2);ADDH8A_3 (Z3,Z4,G345,A3,A4,A5,B3,B4,B5,C2);ADDH8A_4 (Z5,P345,A3,A4,A5,B3,B4,B5,C2);ADDH8A_5 (Z6,Z7,CO,A6,A7,B6,B7,CCI);
ADDH16A ([Z0..Z15],CO,[A0..A15],[B0..B15]);ADDH16A_1 (Z0,Z15,CO,A0,A15,B0,B15,C14);ADDH16A_2 (Z1,Z2,C2,A0,A1,A2,B0,B1,B2);ADDH16A_3 (Z3,Z4,G345,A3,A4,A5,B3,B4,B5,C2);ADDH16A_4 (Z5,P345,A3,A4,A5,B3,B4,B5,C2);ADDH16A_5 (Z6,Z7,G678,A6,A7,A8,B6,B7,B8,C5);ADDH16A_6 (Z8,P678,A6,A7,A8,B6,B7,B8,C5);ADDH16A_7 (Z9,Z10,G911,A9,A10,A11,B9,B10,B11,C8);ADDH16A_8 (Z11,P911,A9,A10,A11,B9,B10,B11,C8);ADDH16A_9 (Z12,Z13,G1214,A12,A13,A14,B12,B13,B14,C11);ADDH16A_10 (Z14,P1214,A12,A13,A14,B12,B13,B14,C11);ADDH16A_11 (C5,C8,C11,C14,C2,P345,G345,P678,G678,P911,G911,
P1214,G1214);
Truth Table:
The value of CO depends on the sum of A+B and n.
* If A+B<2n, CO = 0. If A+B>2n, CO = 1.
Input Output
An-1~A0 Bn-1~B0 Zn-1~Z0 CO
data data A+B *
Macro Library Reference Manual 67
Z0
CO
B0
A0
ADDH1
Macro Library Reference Manual 68
A0
A1
A0
A0
A0
A[0:1]
A1
A1
A1
A0
A1
A1
A0
A1
A0
A0
A1
A[0:1]
A1
A0
A1
A0
A0
A1
B0
B1
B[0:1]
B1
B0
B1
B0
B1
B0
B1
B0
B1
B0
B1
B0B0
B1
Z1
Z0
COA0
A1
B[0:1]
B0
B1
B0
B0
B1
B1
B1
B0
ADDH2
Macro Library Reference Manual 69
A2
A1
A0
B2
B1
B0
B0
B[0:2]
B1
B0
B1
B2
A[0:1]
A1
A0
A0
Z1LX2
Z0LX2
CO
B1
B1
B2
B1
B0
B2
B2
B0
B2
B1
B0
B1
B0
B0
B1
B0
B0
B1
B2
B[0:2]
B0
B2
B1
A1
A0
A0
A1
A0
A1
A0
A1
A0
A2
A2
A2
A2
A1
A0
A[0:2]
A0
A1
A0
A2
A1
ADDH3.1
Macro Library Reference Manual 70
LX2 Z2
B2
B1
B2
B0
B[0:2]
B1
B0
B2
B1
B1
B2
B0
B0
B2
B2
B[0:2]
B2
B2
B1
A1
A1
A0
A[0:1]
A1
A0
A2
A0
A1
A0
A1
A[0:2]
ADDH3.2
Macro Library Reference Manual 71
PRESERVE
A0
B0
B1
CI
A1
ADDF2
Z0
Z1
COB3
B2
A3
A2
CO
Z3
Z2
Z0
Z1
A0
A1
B0
B1
A0
B0
B1
A1 Z0
Z1
CO
ADDH2
ADDH4
Macro Library Reference Manual 72
P1
PRESERVE
P2
PRESERVE
P3
PRESERVE
P4
PRESERVE
P5
PRESERVE
P6
PRESERVE
P7
PRESERVE
G1
PRESERVE
G2
PRESERVE
G3
PRESERVE
G7
PRESERVE
G6
PRESERVE
G5
PRESERVE
G4
PRESERVE
LX2
Z0B0
A0
A3
B3
A2
B2
A1
B1
B4
A4
B5
A5
B6
A6
B7
A7
Z1
ADDH8.1
Macro Library Reference Manual 73
CO
P1
P7
P2
G1
P1
A0
B0
Z2
P1
B0
A0
P5
G4
P4
G3
P3
G2
P2
G1
G7
G6
P6
G5
P5
G4
P4
G3
P3
G2
P2
G1
B0
A0
Z5
Z3
B0
P1
P3
G2
P2
G1
A0
LX2
LX2
LX2
ADDH8.2
Macro Library Reference Manual 74
P1
G1
P2
G2
P3
G3
P4
G4
P5
G5
P6
B0
A0
Z6
A0
Z7
P7
P1
G1
P2
G2
P3
G3
P4
G4
P5
G5
P6
G6
B0
Z4
B0
P1
G1
P2
G2
P3
G3
P4
A0
LX2
LX2
LX2
ADDH8.3
Macro Library Reference Manual 75
CO
Z7
Z6
B7
B6
A7
A6
P345
G345
A0
Z0
Z2
Z1
B2
B1
B0
A2
A1
Z5
A4
A3
A5
B3
B4
B5
Z3
Z4
G012
ADDH3
A0
A1
B2
B1
B0
A2
CO
Z2
Z0
Z1
F3ADD
Z2
Z1
Z0
G012
P012
A0
A1
B2
B1
B0
A2
CI
PGO1
PG1
PGI1
PI1
GI1
A0
B0
B1
CI
A1
ADDF2
Z0
Z1
CO
ADDH8A
Macro Library Reference Manual 76
G678
P678
P911
B15
A15
CO
Z15
P345
G345
G911
Z11
Z10
Z9A9
A10
A11
B9
B10
B11
A12
B13
B14
Z12
Z7
Z6A6
A7
B8
B7
B6
A8 Z8
Z5
A4
A3
A5
B3
B4
B5
Z3
Z4
A1
A2
B0
B1
B2
Z1
Z2
Z0
A0
Z13
B12
A14
A13
Z14
G1214
P1214
G012
ADDH3
A0
A1
B2
B1
B0
A2
CO
Z2
Z0
Z1
F3ADD
Z2
Z1
Z0
G012
P012
A0
A1
B2
B1
B0
A2
CI
F3ADD
Z2
Z1
Z0
G012
P012
A0
A1
B2
B1
B0
A2
CI
F3ADD
Z2
Z1
Z0
G012
P012
A0
A1
B2
B1
B0
A2
CI
F3ADD
Z2
Z1
Z0
G012
P012
A0
A1
B2
B1
B0
A2
CI
ADDF1
Z0
CO
A0
B0
CI
PGO1
PG1
PGI1
PI1
GI1
PGO2
GI1
PI1
PGI1
PG2
GI2
PI2
PGO3
PI3
GI3
PI2
GI2
PI1
PGI1
GI1
PG3
PGO4
PI4
GI4
GI3
PG4
GI1
PGI1
PI1
PI2
PI3
GI2
ADDH16A
Macro Library Reference Manual 77
Comparators
CMP2, CMP4, and CMP8
Function:
CMP2: 2-bit equality comparator.CMP4: 4-bit equality comparator.CMP8: 8-bit equality comparator.
Availability: CMP2, CMP4, and CMP8 are forpDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
Equation Entry for pDS:
CMP2 (EQ,A0,A1,B0,B1);CMP4 (EQ,[A0..A3],[B0..B3]);CMP8 (EQ,[A0..A7],[B0..B7]);
Truth Table:
Macro PT GLB Output Level
CMP2 4 .25 1 1CMP4 8 .5 1 1CMP8 16 .75 1 1
Input Output
A0~An-1, B0~Bn-1 EQ
A0=B0,... An-1=Bn-1 1All other values 0
CMP2 CMP8
EQ
A1
B0
B1
A0
CMP4
EQ
A0
A1
A2
A3
B0
B1
B2
B3
EQA7
B4
B7
B6
B5
B3
B2
B1
B0
A6
A5
A4
A3
A2
A1
A0
Macro Library Reference Manual 78
MAG2, MAG4, and MAG8
Function:
MAG2: 2-bit magnitude comparator.MAG4: 4-bit magnitude comparator.MAG8: 8-bit magnitude comparator.
Availability: MAG2, MAG4, and MAG8 are for pDS, ispDS,and ispDS+.
Additional symbol appears on the following page.
Type:
Soft: MAG2Hard: MAG4 and MAG8
Logic Resources – pDS:
Macro Port Definition:
MAG2 (GT,EQ,LT,A0,A1,B0,B1,GTI,EQI,LTI);MAG4 (GT,EQ,LT,[A0..A3],[B0..B3],GTI,EQI,LTI);
MAG4_1 (EQ,[A0..A3],[B0..B3],GTI,EQI,LTI);MAG4_2 (GT,[A0..A3],[B0..B3],GTI,EQI,LTI);MAG4_3 (LT,[A0..A3],[B0..B3],GTI,EQI,LTI);
MAG8 (GT,EQ,LT,[A0..A7],[B0..B7],GTI,EQI,LTI);MAG8_1 (TEQ,[A4..A7],[B4..B7],GTI,EQI,LTI);MAG8_2 (TGT,[A4..A7],[B4..B7],GTI,EQI,LTI);MAG8_3 (TLT,[A4..A7],[B4..B7],GTI,EQI,LTI);MAG8_4 (EQ,[A0..A3],[B0..B3],TGT,TEQ,TLT);MAG8_5 (GT,[A0..A3],[B0..B3],TGT,TEQ,TLT);MAG8_6 (LT,[A0..A3],[B0..B3],TGT,TEQ,TLT);
Macro PT GLB Output Level
MAG2 4/out .75 3 1MAG4 16/out 3 3 1MAG8 16/out 6 6 2
MAG2
MAG4
A1
A0
GT
EQ
LT
LTI
EQI
GTI
B1
B0
A0
A1
A2
A3
B0
B1
B2
B3
GTI
EQI
LTI
LT
EQ
GT
MAG8
GT
EQ
LT
LTI
EQI
GTI
B7
B6
B5
B4
B3
B2
B1
B0
A7
A6
A5
A4
A3
A2
A1
A0
Macro Library Reference Manual 79
Truth Table:
The truth table is the same for all MAGs.
x = don’t care.
Input Output
LTI ETI GTI A B LT EQ GT
0 0 0 x x 0 0 00 0 1 x x 0 0 10 1 0 A<B 1 0 00 1 0 A=B 0 1 00 1 0 A>B 0 0 10 1 1 x x 0 0 01 0 0 x x 1 0 01 0 1 x x 0 0 01 1 0 x x 0 0 01 1 1 x x 0 0 0
Macro Library Reference Manual 80
Multipliers
MULT24 and MULT44
Function:
MULT24: 2-bit by 4-bit multiplier.MULT44: 4-bit by 4-bit multiplier.
Availability: MULT24 and MULT44 are for pDS,ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
* Z0: 1 PT Z1: 4 PT Z2: 5 PTZ3: 7 PT Z4: 4 PT Z5: 2 PT
** Z0: 1 PT Z1: 1PT Z2: 2 PTZ3: 3 PT Z4: 7 PT Z5: 15 PTZ6: 3 PT Z7: 5 PT
+ (Z2, Z6, and Z7 are 2-level outputs)
Macro Port Definition:
MULT24 (Z0,Z1,Z2,Z3,Z4,Z5,A0,A1,B0,B1,B2,B3);MULT24_1 (Z0,Z1,Z2,Z3,A0,A1,B0,B1,B2,B3);MULT24_2 (Z4,Z5,A0,A1,B0,B1,B2,B3);
MULT44 ([Z0..Z7],[A0..A3],[B0..B3]);MULT44_1 (L0,L1,L2,L3,A0,A1,B0,B1,B2,B3);MULT44_2 (H0,H1,H2,H3,A2,A3,B0,B1,B2,B3);MULT44_3 (L4,L5,H4,H5,A0,A1,A2,A3,B0,B1,B2,B3);MULT44_4 (Z0,Z1,Z2,G012,L0,L1,L2,H0);MULT44_5 (Z3,Z4,G345,L3,L4,L5,H1,H2,H3,G012);MULT44_6 (Z5,P345,L3,L4,L5,H1,H2,H3,G012);MULT44_7 (Z6,Z7,G345,P345,G012,H4,H5,C5);
Truth Table:
* = multiply.
Macro PT GLB Output Level
MULT24 * 1.5 6 1MULT44 ** 6.5 23 1+
Input Output
An-1~A0 Bn-1~B0 Zn-1~Z0
data data A*B
B3
A1
A0
MULT24 MULT44
B1
B0
B2
Z5
Z1
Z0
Z3
Z2
Z4
B1
A1
A0
A3
A2
B0
Z5
Z1
Z0
Z3
Z2
Z4
Z7
Z6B3
B2
Macro Library Reference Manual 81
Z0
B3
B1
B1
B2
B0
B2
B2
B0
B1
B1
B0
B0
B0
B1
B2
B0
B[0:3]
B2
B3
B1
B[0:3]
B0
B1
B0
B1
B0
B3
B2
B1
B2
A[0:1]
A1
A0
A1
A0
A1
A0
A1
A1
A0
A0
A0
A1
A0
A0
A1
A1
A0
A0
A[0:1]
A1
A0
A0
A1
Z2
Z1
B0
B1
B2
B3
MULT24.1
Macro Library Reference Manual 82
Z0
B3
B1
B1
B2
B0
B2
B2
B0
B1
B1
B0
B0
B0
B1
B2
B0
B[0:3]
B2
B3
B1
B[0:3]
B0
B1
B0
B1
B0
B3
B2
B1
B2
A[0:1]
A1
A0
A1
A0
A1
A0
A1
A1
A0
A0
A0
A1
A0
A0
A1
A1
A0
A0
A[0:1]
A1
A0
A0
A1
Z2
Z1
B0
B1
B2
B3
MULT24.2
Macro Library Reference Manual 83
G012
H0
G012
L2
L0
L1
C5
Z7
C5
G012
P345
G345
PGO1
PG1
PGI1
PI1
GI1
Z1
P345
F3ADD
Z2
Z1
Z0
G012
P012
A0
A1
B2
B1
B0
A2
CI
G345
Z2
H2
H1
L5
L4
L3
Z6
Z5
Z4
Z3
Z0
A[0:3]
A0
A1
A2
A3
B[0:3]
B0
B1
B2
B3
B0
B1
B2
B3
A1
A0 Z0
Z1
Z2
Z3
Z4
Z5
MULT24
B0
B1
B2
B3
A1
A0 Z0
Z1
Z2
Z3
Z4
Z5
MULT24
B0
B1
B2
B3
LX2
LX2
H3
MULT44
Macro Library Reference Manual 84
Propagate-Generate
PG1, PG2, PG3, & PG4
Function:
PG1: Propagate-Generate Bit 1.PG2: Propagate-Generate Bit 2.PG3: Propagate-Generate Bit 3.PG4: Propagate-Generate Bit 4.
Availability: PG1, PG2, PG3, and PG4 are for pDS,ispDS, and ispDS+.
Type:
Soft: PG1, PG2, PG3, PG4
Logic Resources – pDS:
Macro Port Definition:
PG1 (PGO1,PGI1,PI1,GI1);PG2 (PGO2,PGI1,PI1,GI1,PI2,GI2);PG3 (PGO3,PGI1,PI1,GI1,PI2,GI2,PI3,GI3);PG4 (PGO4,PGI1,PI1,GI1,PI2,GI2,PI3,GI3,PI4,GI4);
Macro PT GLB Output Level
PG1 2 .25 1 1PG2 3 .25 1 1PG3 4 .25 1 1PG4 5 .25 1 1
PG1
PGO1
PI1
PGI1
GI1
PG2
PGO2
PI2
GI1
G12
PI1
PGI1
PG3
PGO3
PI3
GI2
GI3
PI2
GI1
PI1
PGI1
PG4
PGO4
PI4
GI3
GI4
PI3
GI2
PI2
GI1
PI1
PGI1
Macro Library Reference Manual 85
Truth Table for PG1:
x = don’t care.
Truth Table for PG2:
x = don’t care.
Truth Table for PG3:
x = don’t care.
Truth Table for PG4:
x = don’t care.
Input Output
PGI1 PI1 GI1 PGO1
x x 1 11 1 x 1
Input Output
PGI1 PI1 PI2 GI1 G12 PGO2
x x x x 1 1x x 1 1 x 11 1 1 x x 1
Input Output
PGI1 PI1 PI2 PI3 GI1 GI2 GI3 PGO3
x x x x x x 1 1x x x 1 x 1 x 1x x 1 1 1 x x 11 1 1 1 x x x 1
Input Output
PGI1 PI1 PI2 PI3 PI4 GI1 GI2 GI3 GI4 PGO4
x x x x x x x x 1 1x x x x 1 x x 1 x 1x x x 1 1 x 1 x x 1x x 1 1 1 1 x x x 11 1 1 1 1 x x x x 1
Macro Library Reference Manual 86
PGO1PI1
PGI1
GI1
PG1
Macro Library Reference Manual 87
PGO2
GI2
PI2
GI1
PI1
PGI1
PG2
Macro Library Reference Manual 88
PGO3
PGI1
PI1
GI1
PI2
GI2
PI3
GI3
PG3
Macro Library Reference Manual 89
PGO4
GI4
PI4
GI3
PI3
GI2
PI2
GI1
PI1
PGI1
PG4
Macro Library Reference Manual 90
Subtractors
SUBF1, SUBF2, F3SUB, SUBF4, SUBF8,SUBF8A, & SUBF16A
Function:
SUBF1: 1-bit full subtractor.SUBF2: 2-bit full subtractor.F3SUB: 3-bit full subtractor with propagate-generate.SUBF4: 4-bit full subtractor.SUBF8: 8-bit full subtractor.SUBF8A: 8-bit full subtractor built with propagate-generate
submacros.SUBF16A: 16-bit full subtractor built with propagate-generate
submacros.
Availability: SUBF1, SUBF2, F3SUB, SUBF4, SUBF8,SUBF8A, and SUBF16A are for pDS, ispDS, and ispDS+.
Additional symbol appears on the following page.
Type:
Soft: SUBF1, SUBF2, F3SUB, SUBF8A, SUBF16AHard: SUBF4, SUBF8
SUBF1
SUBF2
SUBF4
Z0
BO
A0
B0
BI
BO
Z1
Z0A1
BI
B1
B0
A0
Z1
Z0
Z2
Z3
BO
BI
A2
A3
B0
B1
B2
B3
A1
A0
A-B
A-B
A-B
F3SUB
BI
A0
A1
A2
B0
B1
B2
Z0
Z1
Z2
G012
P012
A-B
Z5
Z4
Z6
Z7
BO
Z1
Z0
Z2
Z3
SUBF8
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
BIA-B
A-B
SUBF8A
C1A0A1A2A3A4A5
B4
A6A7B0B1B2B3
Z0Z1Z2Z3Z4Z5Z6
B7
B5B6
Z7
C1
BI
A0
A1
A2
A3
A4
A5
B4
A6
A7
B0
B1
B2
B3
Z0
Z1
Z2
Z3
Z4
Z5
Z6
B7
B5
B6
Z7
BO
A-B
Macro Library Reference Manual 91
Logic Resources – pDS:
* Z0: 4 PT BO: 3 PT** Z0: 4 PT Z1: 7 PT BO: 7 PT*** Z0: 3 PT Z1: 7 PT Z2: 15 PT
G012: 7 PT P012: 3 PT**** Z0: 4 PT Z1: 7 PT Z2: 4 PT
Z3: 7 PT BO: 7 PT TBO: 7 PT***** Z0: 2 PT Z1: 3 PT Z2: 4 PT
Z3: 5 PT Z4: 6 PT Z5: 7 PTZ6: 6 PT Z7: 7 PT BO: 6 PTBA: 3 PT BB: 7 PT BC: 3 PTG0-G6: 1 PT P0-P7: 2 PT
****** Z0: 3 PT Z1: 7 PT Z2: 15 PTZ3: 3 PT Z4: 7 PT Z5: 15 PTZ6: 4 PT Z7: 7 PT BO: 7 PT
******* Z0: 3 PT Z1: 7 PT Z2: 15 PTZ3: 3 PT Z4: 7 PT Z5: 15 PTZ6: 3 PT Z7: 7 PT Z8: 15 PTZ9: 3 PT Z10: 7 PT Z11: 15 PTZ12: 3 PT Z13: 7 PT Z14: 15 PTZ15: 4 PT BO: 3 PT
+ (BO is a 3-level output).
Macro PT GLB Output Level
SUBF1 * .5 2 1SUBF2 ** 1 3 1F3SUB *** 2 5 1SUBF4 **** 2 6 2SUBF8 ***** 7.25 28 2+
SUBF8A ****** 5.5 15 1SUBF16A ******* 11.75 32 1
BI
A0
A1
A2
A3
A4
A5
A12
A6
A7
A8
A9
A10
A11
Z0
Z1
Z2
Z3
Z4
Z5
Z6
A15
A13
A14
Z7
BO
B0
B1
B2
B3
B4
B5
B6
B11
B7
B8
B9
B10
B14
B12
B13
B15
Z8
Z9
Z10
Z11
Z12
Z13
Z14
Z15
SUBF16A
A-B
Macro Library Reference Manual 92
Macro Port Definition:
SUBF1 (Z0,BO,A0,B0,BI);SUBF2 (Z0,Z1,BO,A0,A1,B0,B1,BI);F3SUB ([Z0..Z2],G012,P012,[A0..A2],[B0..B2],BI);
F3SUB_1 (Z0,Z1,G012,[A02..A2],[B0..B2],BI);F3SUB_2 (Z2,P012,[A0..A2][B0..B2],BI);
SUBF4 ([Z0..Z3],BO,[A0..A3],[B0..B3],BI);SUBF4_1 (Z0,Z1,TBO,A0,A1,B0,B1,BI);SUBF4_2 (Z2,Z3,BO,A2,A3,B2,B3,TBO);
SUBF8 ([Z0..Z7],BO,[A0..A7],[B0..B7],BI);SUBF8_1 (BO,[P0..P7],[G0..G3],BB,BI);SUBF8_2 (Z7,[P0..P7][G0..G3],A3,B3,BI,BA);SUBF8_3 (Z6,[P0..P6],G0,G1,A0,A2,B0,B2,BI,BC);SUBF8_4 (Z5,[P0..P6],G0,G1,G3,A2,A4,A6,B2,B4,B6,BI);SUBF8_5 (Z2,Z4,[P0..P4],[G0..G2],G4,A1,A3,A4,B1,B3,B4,BI);SUBF8_6 (Z3,[P0..P3],G1,G2,G5,G6,A0,A1,A5,A6,B0,B1,B5,B6,BI);SUBF8_7 (Z0,P7,G2,BB,P0,P5,P6,G4,G5,G6,A2,A7,B2,B7,BI);SUBF8_8 (Z1,BA,BC,P5,P0,P1,P4,P6,[G3..G6],A0,A5,B0,B5,BI);
SUBF8A ([Z0..Z7],BO,[A0..A7],[B0..B7],BI);SUBF8A_1 (Z0,Z1,G012,[A0..A2],[B0..B2],BI);SUBF8A_2 (Z2,P012,[A0..A2],[B0..B2],BI);SUBF8A_3 (BB2,BBI,BI,P012,P345,G012,G345);SUBF8A_4 (Z3,Z4,G345,A3,A4,A5,B3,B4,B5,BB2);SUBF8A_5 (Z5,P345,[A3..A5],[B3..B5],BB2);SUBF8A_6 (BO,Z6,Z7,A6,A7,B6,B7,BBI);
SUBF16A ([Z0..Z15],BO,[A0..A15],[B0..B15],BI);SUBF16A_1 (Z0,Z1,G012,A0,A1,A2,B0,B1,B2,BI);SUBF16A_2 (Z2,P012,A0,A1,A2,B0,B1,B2,BI);SUBF16A_3 (Z3,Z4,G345,A3,A4,A5,B3,B4,B5,BB2);SUBF16A_4 (Z5,P345,A3,A4,A5,B3,B4,B5,BB2);SUBF16A_5 (Z6,Z7,G678,A6,A7,A8,B6,B7,B8,BB5);SUBF16A_6 (Z8,P678,A6,A7,A8,B6,B7,B8,BB5);SUBF16A_7 (Z9,Z10,G911,A9,A10,A11,B9,B10,B11,BB8);SUBF16A_8 (Z11,P911,A9,A10,A11,B9,B10,B11,BB8);SUBF16A_9 (Z12,Z13,G1214,A12,A13,A14,B12,B13,B14,BB11);SUBF16A_10 (Z14,P1214,A12,A13,A14,B12,B13,B14,BB11);SUBF16A_11 (Z15,BO,BB2,BI,P012,G012,A15,B15,BB14);SUBF16A_12 (BB5,BB8,BB11,BB14,BB2,P345,G345,P678,G678,
P911,G911,P1214,G1214);
Macro Library Reference Manual 93
Truth Table:
The truth table below applies to SUBF1, SUBF2, SUBF4, SUBF8,SUBF8A, and SUBF16A.The value of BO depends on the differenceof A–B.
* If B<A, BO = 0. If B>A, BO = 1.** If B<A, BO = 0. If B>A, BO = 1.
The truth table for F3SUB is shown below.
* If B<A, G012 = 0. If B>A, G012 = 1.** If B<A, G012 = 0. If B>A, G012 = 1.*** P012 = (A0 + B0) (A1 + B1) (A2 + B2) where A0 = inverted A0.
Input Output
An-1~A0 Bn-1~B0 BI Zn-1~Z0 BO
data data 0 A–B *data data 1 A–B–1 **
Input Output
A2~A0 B2~B0 BI Z2~Z0 G012 P012
data data 0 A-B * ***data data 1 A-B-1 ** ***
Macro Library Reference Manual 94
BI
B0
A0
Z0
BO
SUBF1
Macro Library Reference Manual 95
BI
LX2
BO
Z0
Z1
B0
B1
A0
A1 A1
A0A0
A1
A[0:1]
A1
A0
A0
A0
B0
B1
B[0:1]
B0B0
B1
B0
B1
B1
BI
BI
A0
A1
A1
A0
A0
A1
A0
A0
A0
A1
A0
A1
A[0:1]
B0
B0
B1
B0
B1
B1
B1
B0
B[0:1]
B1
B0
B1
B1
B0
B0
B1
B1
B0
B0
SUBF2
Macro Library Reference Manual 96
B1
B2
B1
B1
B[0:2]
B1
B2
B0
B2
B0B2
B0
B1
B0
B1
B0
B0
B1
B2
B1
B2
B1
B0
B0
B0
G012
Z1LX2
LX2 Z0
B2
A2
B0
A0
A1
B1
BI
P012
BI
B0
B1
B2
B[0:2]
B1
B0
B0
B1
B0
B1
B0
B1
B2
A0
A1
A2
A0
A2
A1
A1
A0
A0
A[0:2]
A2
A1
A0
A0
A2
A1
A1
A1
A0
A1
A2
A0
A0
A[0:2]
A0
A0
A1
A2
A0
A2
A2
A0
F3SUB.1
Macro Library Reference Manual 97
BI
BI
BI
BI
BI
B2
B1
B2
B1
B2
B2
B0
B0
B2
B2
B[0:2]
B1
B0
B2
B1
B0
B2
B2
B0
B0
B1
B2
B1
B[0:2]
B2
B0
B2
B0
B1
B2
B2
B1
BI
BI
BI
BI
A0
A0
A0
A1
A1
A1
A0
A1
A[0:1]
A[0:2]
A0
A2
A0
A1
A0
A1
A1
A0
A1
Z2LX2
F3SUB. 2
Macro Library Reference Manual 98
BI
B3
B2
A3
A2
BO
Z3
Z2
Z0
Z1
A0
A1
B0
B1
PRESERVE
A-B
A0
B0
B1
BI
A1 Z0
Z1
BO
SUBF2
A-B
A0
B0
B1
BI
A1 Z0
Z1
BO
SUBF2
SUBF4
Macro Library Reference Manual 99
G7
PRESERVE
G6
PRESERVE
G5
PRESERVE
G4
PRESERVE
G3
PRESERVE
G2
PRESERVE
G1
PRESERVE
G0
PRESERVE
P7
PRESERVE
P6
PRESERVE
P5
PRESERVE
P4
PRESERVE
P3
PRESERVE
P2
PRESERVE
P1
PRESERVE
P0
PRESERVE
B0
A0
A3
B3
A2
B2
A1
B1
B4
A4
B5
A5
B6
A6
B7
A7
SUBF8.1
Macro Library Reference Manual 100
BO
P2
G1
P1
G0
P0
BI
G4
P5
Z5LX2
P4
G3
G2
G1
G0
BI
P3
P2
P0
P1
P7
P6
P5
G6
G5
G4
P4
G2
G3
P3
G1
P2
P1
P0
G0
BI
Z2LX2
G7
SUBF8.2
Macro Library Reference Manual 101
SUBH1, SUBH2, SUBH3, SUBH4,SUBH8, SUBH8A, & SUBH16A
Function:
SUBH1: 1-bit half subtractor.SUBH2: 2-bit half subtractor.SUBH3: 3-bit half subtractor.SUBH4: 4-bit half subtractor.SUBH8: 8-bit half subtractor.SUBH8A: 8-bit half subtractor built with propagate-generate
submacros.SUBH16A: 16-bit half subtractor built with propagate-generate
submacros.
Availability: SUBH1, SUBH2, SUBH3, SUBH4, SUBH8,SUBH8A, and SUBH16A are for pDS, ispDS, and ispDS+.
Additional symbol appears on the following page.
Type:
Soft: SUBH1, SUBH2, SUBH3, SUBH8A, SUBH16AHard: SUBH4, SUBH8
SUBH1
SUBH2
B0
A0 Z0
BO
BO
Z1
Z0A1
B1
B0
A0
SUBH4
Z1
Z0
Z2
Z3
BO
A2
A3
B0
B1
B2
B3
A1
A0
A-B
A-B
A-B
SUBH3
A0
A1
A2
B0
B1
B2
Z0
Z1
Z2
BO
A-B
SUBH8
Z5
Z4
Z6
Z7
BO
Z1
Z0
Z2
Z3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A-B
SUBH8A
C1A0A1A2A3A4A5
B4
A6A7B0B1B2B3
Z0Z1Z2Z3Z4Z5Z6
B7
B5B6
Z7
C1
A0
A1
A2
A3
A4
A5
B4
A6
A7
B0
B1
B2
B3
Z0
Z1
Z2
Z3
Z4
Z5
Z6
B7
B5
B6
Z7
BO
A-B
Macro Library Reference Manual 102
Logic Resources – pDS:
Logic Resources:
* Z0: 2 PT BO: 1 PT** Z0: 2 PT Z1: 6 PT BO: 3 PT*** Z0: 2 PT Z1: 4 PT Z2: 9 PT
BO: 7 PT**** Z0: 2 PT Z1: 6 PT Z2: 4 PT
Z3: 7 PT BO: 7 PT TBO: 3 PT***** Z0: 2 PT Z1: 2 PT Z2: 3 PT
Z3: 4 PT Z4: 5 PT Z5: 9 PTZ6: 11 PT Z7: 8 PT BO: 7 PTBB: 3 PT G1-G5: 1 PT P1-P7: 2 PT
****** Z0: 2 PT Z1:4 PT Z2: 9 PTZ3: 3 PT Z4: 7 PT Z5: 15 PTZ6: 4 PT Z7: 7 PT BO: 7 PT
******* Z0: 2 PT Z1: 4 PT Z2: 9 PTZ3: 3 PT Z4: 7 PT Z5: 15 PTZ6: 3 PT Z7: 7 PT Z8: 15 PTZ9: 3 PT Z10: 7 PT Z11: 15 PTZ12: 3 PT Z13: 7 PT Z14: 15 PTZ15: 4PT BO: 3 PT
Macro PT GLB Output Level
SUBH1 * .5 2 1SUBH2 ** .75 3 1SUBH3 *** 1.25 4 1SUBH4 **** 1.75 6 2SUBH8 ***** 5.75 23 2
SUBH8A ****** 4.5 13 1SUBH16A ******* 10.75 30 1
SUBH16A
A0
A1
A2
A3
A4
A5
A12
A6
A7
A8
A9
A10
A11
Z0
Z1
Z2
Z3
Z4
Z5
Z6
A15
A13
A14
Z7
BO
B0
B1
B2B3
B4
B5
B6
B11
B7
B8
B9
B10
B14
B12
B13
B15
Z8
Z9
Z10
Z11
Z12
Z13
Z14
Z15
A-B
Macro Library Reference Manual 103
Macro Port Definition:
SUBH1 (Z0,BO,A0,B0);SUBH2 (Z0,Z1,BO,A0,A1,B0,B1);SUBH3 ([Z0..Z2],BO,[A0..A2],[B0..B2]);
SUBH3_1 (Z0,A0,B0);SUBH3_2 (Z1,Z2,BO,A0,A1,A2,B0,B1,B2);
SUBH4 ([Z0..Z3],BO,[A0..A3],[B0..B3]);SUBH4_1 (Z0,Z1,TBO,A0,A1,B0,B1);SUBH4_2 (Z2,Z3,BO,A2,A3,B2,B3,TBO);
SUBH8 ([Z0..Z7],BO,[A0..A7],[B0..B7]);SUBH8_1 (BO,Z1,Z3,[P1..P7],[G1..G5],A0,B0,BB);SUBH8_2 (Z0,Z2,Z4,Z7,[P1..P7],[G1..G5],A0,A6,B0,B6);SUBH8_3 (Z6,[P1..P6],[G1..G5],A0,A4,A5,B0,B4,B5);SUBH8_4 (Z5,[P1..P5],[G1..G4],A0,A1,A3,B0,B1,B3);SUBH8_5 (G2,P2,P1,A1,A2,B1,B2);SUBH8_6 (BB,[P5..P7],[A5..A7],[B5..B7]);
SUBH8A ([Z0..Z7],BO,[A0..A7],[B0..B7]);SUBH8A_1 (Z0,A0,B0,BB2,BI,P345,G345);SUBH8A_2 (Z1,Z2,BB2,A0,A1,A2,B0,B1,B2);SUBH8A_3 (Z3,Z4,G345,A3,A4,A5,B3,B4,B5,BB2);SUBH8A_4 (Z5,P345,A3,A4,A5,B3,B4,B5,BB2);SUBH8A_5 (Z6,Z7,BO,A6,A7,B6,B7,BI);
SUBH16A ([Z0..Z15],BO,[A0..A15],[B0..B15]);SUBH16A_1 (Z0,Z15,BO,A0,A15,B0,B15,BB14);SUBH16A_2 (Z1,Z2,BB2,A0,A1,A2,B0,B1,B2);SUBH16A_3 (Z3,Z4,G345,A3,A4,A5,B3,B4,B5,BB2);SUBH16A_4 (Z5,P345,A3,A4,A5,B3,B4,B5,BB2);SUBH16A_5 (Z6,Z7,G678,A6,A7,A8,B6,B7,B8,BB5);SUBH16A_6 (Z8,P678,A6,A7,A8,B6,B7,B8,BB5);SUBH16A_7 (Z9,Z10,G911,A9,A10,A11,B9,B10,B11,BB8);SUBH16A_8 (Z11,P911,A9,A10,A11,B9,B10,B11,BB8);SUBH16A_9 (Z12,Z13,G1214,A12,A13,A14,B12,B13,B14,BB11);SUBH16A_10 (Z14,P1214,A12,A13,A14,B12,B13,B14,BB11);SUBH16A_11 (BB5,BB8,BB11,BB14,BB2,P345,G345,P678,G678,P911,
G911,P1214,G1214);
Truth Table:
The value of BO depends on the difference of A–B.
* If B<A, BO = 0. If B>A, BO = 1.
Input Output
An-1~A0 Bn-1~B0 Zn-1~Z0 BO
data data A–B *
Macro Library Reference Manual 104
Z0
BO
B0
A0
SUBH1
Macro Library Reference Manual 105
A[0:1]
A0
A0
A1
A0
A0
A1
A1
A1
A0
A1
A1
A1
A1
A0
A1
A0
A0
A1
A0
A0
A0
A1
A[0:1]
B0
B[0:1]
B1
B0
B1
B0
B1
B0
B1
B0
B1
B1
B0B0
B1
B0
B1
Z1
Z0
BO
B[0:1]
B0
B1
B0
B0
B1
B1
B1
B0
A0
A1
SUBH2
Macro Library Reference Manual 106
A2
A[0:2]
A2
A0
A0
A1
A2
A1
A2
A1
A0
A2
A0
A1
A1
A2
A1
A0
A[0:2]
A0
A1
A0
A1
A2
A0
B1
B[0:2]
B0
B1
B2
B0
B1
B0
B1
B2
B0
B0
B1B1
B0
B2
B2
B2
B2
B1
B0
B[0:2]
B2
B0
B0
B1
B1
B0
B1
A2
A1
A0
B2
B1
B0
Z1LX2
Z0
BO
A0 A0
SUBH3.1
Macro Library Reference Manual 107
Z2LX2
A0
A1
A0
A2
A1
A1
A[0:2]
B2
B2
B2
B1
B0
B1
B0
B2
B[0:2]
B2
B1
B0
B2
B1
B2
B1
B2
B[0:2]
B0
A0
A[0:1]
A1
A1
A0
SUBH3.2
Macro Library Reference Manual 108
PRESERVE
A-B
A0
B0
B1
BI
A1 Z0
Z1
BO
SUBF2
A-B
A0
B0
B1
A1 Z0
Z1
BO
SUBH2
B1
B0
A1
A0
Z1
Z0
Z2
Z3
BO
A2
A3
B2
B3
SUBH4
Macro Library Reference Manual 109
P1
PRESERVE
P2
PRESERVE
P3
PRESERVE
P4
PRESERVE
P5
PRESERVE
P6
PRESERVE
P7
PRESERVE
G1
PRESERVE
G2
PRESERVE
G3
PRESERVE
G4
PRESERVE
G5
PRESERVE
G6
PRESERVE
G7
PRESERVE
LX2
Z0
A7
B7
A6
B6
A5
B5
A4
B4
B1
A1
B2
A2
B3
A3
A0
B0
Z1
SUBH8.1
Macro Library Reference Manual 110
P5
G4
G3
G2
BO
P3
G2
G1
B0
P2
P1
A0
Z5
B0
G1
P4
P3
P2
P1
A0
G7
P2
G1
B0
P1
A0
P5
P7
P6
P4
G6
G5
G4
G3
G2
P3
B0
G1
P2
P1
A0
Z2
Z3LX2
LX2
LX2
SUBH8.2
Macro Library Reference Manual 111
P4
G3
G2
P7
Z7LX2
B0
G1
A0
P1
P2
P3
B0
G1
G2
G3
G4
P6
G5
P5
P4
P3
P2
P1
A0
B0
G1
G2
G3
G4
G5
G6
P6
P5
P4
P3
P2
P1
A0
Z6
Z4LX2
LX2
SUBH8.3
Macro Library Reference Manual 112
Z4
Z3
B5
B4
B3
A5
A3
A4
Z5
A1
A2
B0
B1
B2
Z1
Z2
Z0
A0
A6
A7
B6
B7
Z6
Z7
BO
P345
G345
G012
A-B
SUBH3
A0
A1
A2
BO
Z2
Z0
Z1
B0
B1
B2
A-B
F3SUB
BI
B2
B1
B0
A2
A1
A0
P012
G012
Z2
Z1
Z0
PGO1
PG1
PGI1
PI1
GI1
A-B
A0
B0
B1
BI
A1 Z0
Z1
BO
SUBF2
SUBH8A
Macro Library Reference Manual 113
G012
P678
P911
P1214
G1214
Z14
A13
A14
B12
Z13
A0
Z0
Z2
Z1
B2
B1
B0
A2
A1
Z4
Z3
B5
B4
B3
A5
A3
A4
Z5
Z8A8
B6
B7
B8
A7
A6 Z6
Z7
Z12
B14
B13
A12
B11
B10
B9
A11
A10
A9 Z9
Z10
Z11
G911
G345
P345
Z15
BO
A15
B15
A-B
SUBH3
A0
A1
A2
BO
Z2
Z0
Z1
B0
B1
B2
A-B
F3SUB
BI
B2
B1
B0
A2
A1
A0
P012
G012
Z2
Z1
Z0
A-B
F3SUB
BI
B2
B1
B0
A2
A1
A0
P012
G012
Z2
Z1
Z0
A-B
F3SUB
BI
B2
B1
B0
A2
A1
A0
P012
G012
Z2
Z1
Z0
A-B
F3SUB
BI
B2
B1
B0
A2
A1
A0
P012
G012
Z2
Z1
Z0
A-B
SUBF1
Z0
BO
A0
B0
BI
PGO1
PG1
PGI1
PI1
GI1
PGO2
GI1
PI1
PGI1
PG2
GI2
PI2
PGO3
PI3
GI3
PI2
GI2
PI1
PGI1
GI1
PG3
PGO4
PI4
GI4
GI3
PG4
GI1
PGI1
PI1
PI2
PI3
GI2
SUBH16A
Macro Library Reference Manual 114
Coders
This chapter contains information on the following macros:
■ Decoders
■ Encoders
Macro Library Reference Manual 115
Decoders
BIN27
Function: Binary to seven segment decoder with enable. A highlevel on an output turns on the segment.
Availability: BIN27 is for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
* Z0: 6 PTZ1, Z2, Z3, Z5: 5 PTZ4, Z6: 4 PT
Macro Port Definition:
BIN27 ([Z0..Z6],[A0..A3],EN);BIN27_1 ([Z0..Z2],[A0..A3],EN);BIN27_2 ([Z3..Z6],[A0..A3],EN);
Segment Map:
Each BIN27 output corresponds to one of 7 segments.Combinations of these segments form hexadecimal digits.
Macro PT GLB Output LevelBIN27 * 2 7 1
BIN27
EN
A0
A1
A2
A3 Z6
Z5
Z4
Z3
Z2
Z1
Z0
Z0Z1
Z2Z6
Z3
Z5
Z4
Macro Library Reference Manual 116
Truth Table:
x = don’t care.
Input OutputCharacter
EN A3 A2 A1 A0 Z0 Z1 Z2 Z3 Z4 Z5 Z6
1 0 0 0 0 1 1 1 1 1 1 0 01 0 0 0 1 0 1 1 0 0 0 0 11 0 0 1 0 1 1 0 1 1 0 1 21 0 0 1 1 1 1 1 1 0 0 1 31 0 1 0 0 0 1 1 0 0 1 1 41 0 1 0 1 1 0 1 1 0 1 1 51 0 1 1 0 1 0 1 1 1 1 1 61 0 1 1 1 1 1 1 0 0 0 0 71 1 0 0 0 1 1 1 1 1 1 1 81 1 0 0 1 1 1 1 1 0 1 1 91 1 0 1 0 1 1 1 0 1 1 1 A1 1 0 1 1 0 0 1 1 1 1 1 B1 1 1 0 0 0 0 0 1 1 0 1 C1 1 1 0 1 0 1 1 1 1 0 1 D1 1 1 1 0 1 0 0 1 1 1 1 E1 1 1 1 1 1 0 0 0 1 1 1 F0 x x x x 0 0 0 0 0 0 0 Off
Macro Library Reference Manual 117
DEC2 and DEC2E
Function:
DEC2: 1 to 2 decoder.DEC2E: 1 to 2 decoder with enable.
Availability: DEC2 and DEC2E are for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
DEC2 (Z0,Z1,S0);DEC2E (Z0,Z1,EN,S0);
Truth Table:
Gray areas (EN) apply only to DEC2E.
x = don’t care.
Macro PT GLB Output Level
DEC2 1/out .5 2 1DEC2E 1/out .5 2 1
Input Output
EN S0 Z0 Z1
1 0 1 01 1 0 10 x 0 0
Z0
Z1
EN
S0
DEC2
DEC2E
Z1
Z0
S0
Macro Library Reference Manual 118
DEC3 and DEC3E
Function:
DEC3: 1 to 3 decoder.DEC3E: 1 to 3 decoder with enable.
Availability: DEC3 and DEC3E are for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
DEC3 (Z0,Z1,Z2,S0,S1);DEC3E (Z0,Z1,Z2,EN,S0,S1);
Truth Table:
Gray areas (EN) apply only to DEC3E.
x = don’t care.
Macro PT GLB Output Level
DEC3 1/out .75 3 1DEC3E 1/out .75 3 1
Input Output
EN S1 S0 Z0 Z1 Z2
1 0 0 1 0 01 0 1 0 1 01 1 0 0 0 11 1 1 0 0 01 x x 0 0 0
DEC3
DEC3E
Z2
Z1
Z0
EN
S0
S1
Z2
Z1
Z0
S0
S1
Macro Library Reference Manual 119
DEC4 and DEC4E
Function:
DEC4: 1 to 4 decoder.DEC4E: 1 to 4 decoder with enable.
Availability: DEC4 and DEC4E are for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
DEC4 ([Z0..Z3],S0,S1);DEC4E ([Z0..Z3],EN,S0,S1);
Truth Table:
Gray areas (EN) apply only to DEC4E.
x = don’t care.
Macro PT GLB Output Level
DEC4 1/out 1 4 1DEC4E 1/out 1 4 1
Input Output
EN S1 S0 Z0 Z1 Z2 Z3
1 0 0 1 0 0 01 0 1 0 1 0 01 1 0 0 0 1 01 1 1 0 0 0 10 x x 0 0 0 0
Z1
Z0
Z2
Z3S0
S1
Z1
Z0
Z2
Z3
EN
S0
S1
DEC4
DEC4E
Macro Library Reference Manual 120
Encoders
PREN8 and PREN8E
Function:
PREN8: 7 line to 3 line priority encoder.PREN8E: 7 line to 3 line priority encoder with enable.
Availability: PREN8 and PREN8E are for pDS, ispDS, andispDS+.
Type: Soft
Logic Resources – pDS:
* Z0: 4 PT Z1: 3 PT Z2: 1 PT** Z0: 4 PT Z1: 4 PT Z2: 2 PT
Macro Port Definition:
PREN8 ([Z0..Z2],[S0..S6]);PREN8E ([Z0..Z2],[S0..S6],EN);
Truth Table:
Gray areas (EN) apply only to PREN8E.
x = don’t care
Macro PT GLB Output Level
PREN8 * .75 3 1PREN8E ** .75 3 1
Input Output
EN S0 S1 S2 S3 S4 S5 S6 Z2 Z1 Z0
1 0 0 0 0 0 0 0 0 0 01 1 0 0 0 0 0 0 0 0 11 x 1 0 0 0 0 0 0 1 01 x x 1 0 0 0 0 0 1 11 x x x 1 0 0 0 1 0 01 x x x x 1 0 0 1 0 11 x x x x x 1 0 1 1 01 x x x x x x 1 1 1 10 x x x x x x x 0 0 0
PREN8
PREN8E
S0
S1
S2
S3
S4
S5
S6
EN
Z2
Z1
Z0
S0
S1
S2
S3
S4
S5
S6
Z2
Z1
Z0
Macro Library Reference Manual 121
PREN10 and PREN10E
Function:
PREN10: 9 line to 4 line priority encoder.PREN10E: 9 line to 4 line priority encoder with enable.
Availability: PREN10 and PREN10E are for pDS, ispDS, andispDS+.
Type: Soft
Logic Resources – pDS:
* Z3: 1 PT Z2, Z1: 4 PT Z0: 5 PT** Z3: 2 PT Z2, Z1: 4 PT Z0: 5 PT
Macro Port Definition:
PREN10 ([Z0..Z3],[S0..S8]);PREN10E ([Z0..Z3],[S0..S8],EN);
Truth Table:
Gray areas (EN) apply only to PREN10E.
x = don’t care.
Macro PT GLB Output Level
PREN10 14* 1 4 1PREN10E 15** 1 4 1
Input Output
EN S0 S1 S2 S3 S4 S5 S6 S7 S8 Z3 Z2 Z1 Z0
1 0 0 0 0 0 0 0 0 0 0 0 0 01 1 0 0 0 0 0 0 0 0 0 0 0 11 x 1 0 0 0 0 0 0 0 0 0 1 01 x x 1 0 0 0 0 0 0 0 0 1 11 x x x 1 0 0 0 0 0 0 1 0 01 x x x x 1 0 0 0 0 0 1 0 11 x x x x x 1 0 0 0 0 1 1 01 x x x x x x 1 0 0 0 1 1 11 x x x x x x x 1 0 1 0 0 01 x x x x x x x x 1 1 0 0 10 x x x x x x x x x 0 0 0 0
PREN10 PREN10E
S0
S1
S2
S3
S4
S5
S6
S7
S8
EN
Z3
Z2
Z1
Z0S0
S1
S2
S3
S4
S5
S6
S7
S8
Z3
Z2
Z1
Z0
Macro Library Reference Manual 122
PREN16 & PREN16E
Function:
PREN16: 15 line to 4 line priority encoder.PREN16E: 15 line to 4 line priority encoder with enable.
Availability: PREN16 and PREN16E are for pDS, ispDS, andispDS+.
Type: Soft
Logic Resources – pDS:
* Z0, Z1, Z2: 8 PTZ3: 1 PT
Macro Port Definition:
PREN16 ([Z0..Z3],[S0..S14]);PREN16_1 (Z0,Z1,[S0..S14]);PREN16_2 (Z2,Z3,[S3..S14]);
PREN16E ([Z0..Z3],[S0..S14],EN);PREN16E_1 (Z0,Z1,[S0..S14],EN);PREN16E_2 (Z2,Z3,[S3..S14],EN);
Truth Table:
Gray areas (EN) apply only to PREN16E. Some areas of this table are notshown. Refer to the PREN10/10E truth table for the logic pattern.
x = don’t care.
Macro PT GLB Output Level
PREN16 * 1.5 4 1PREN16E 8/out 2 4 1
Input Output
EN S0 S1 S2 S3 S11 S12 S13 S14 Z3 Z2 Z1 Z0
1 0 0 0 0 0 0 0 0 0 0 0 01 1 0 0 0 0 0 0 0 0 0 0 11 x 1 0 0 0 0 0 0 0 0 1 01 x x 1 0 ------ 0 0 0 0 0 0 1 1x x x x x 1 0 0 0 1 1 0 01 x x x x x 1 0 0 0 1 0 11 x x x x x x 1 0 1 1 1 01 x x x x ------ x x x 1 1 1 1 10 x x x x x x x x 0 0 0 0
PREN16 PREN16E
S0
S1
S2
S3
S4
S5
S6
S7
S13
S12
S11
S10
S9
S14
S8
EN
Z3
Z2
Z1
Z0S0
S1
S2
S3
S4
S5
S6
S7
S13
S12
S11
S10
S9
S14
S8
Z3
Z2
Z1
Z0
Macro Library Reference Manual 123
Counters
This chapter contains information on the following macros:
■ Binary Counters
■ Decade Counters
■ Gray Code Counters
Macro Library Reference Manual 124
Binary Counters
CBD11, CBD12, CBD14, and CBD18
Function: 1-, 2-, 4-, and 8-bit down counters with asynchronousclear, CAI, and CAO.
Availability: CBD11, CBD12, CBD14, and CBD18 are for pDS,ispDS, and ispDS+.
Type:
Soft: CBD11 and CBD12.Hard: CBD14 and CBD18.
Logic Resources – pDS:
* Q0-Qn-1: 2 PT per output.CAO: 1 PT.CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.
** (CAO is a 2-level output).
Macro Port Definition:
CBD11 (Q0,CAO,CAI,CLK,CD);CBD12 (Q0,Q1,CAO,CAI,CLK,CD);CBD14 ([Q0..Q3],CAO,CAI,CLK,CD);
CBD14_1 ([Q0..Q3],CAI,CLK,CD);CBD14_2 (CAO,[Q0..Q3],CAI);
CBD18 ([Q0..Q7],CAO,CAI,CLK,CD);CBD18_1 ([Q0..Q3],CAI,CLK,CD);CBD18_2 ([Q4..Q7],[Q0..Q3],CAI,CLK,CD);CBD18_3 (CAO,[Q0..Q7],CAI);
Macro PT GLB Output Level
CBD11 * .5 2 1**CBD12 * .75 3 1**CBD14 * 1.25 5 1**CBD18 * 2.25 9 1**
CBD11
CBD12
CBD14
CBD18
CD
CAO
Q0CAI
CD
CAO
Q1
Q0CAI
CD
CAO
Q3
Q2
Q1
Q0CAI
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CD
CAI
CAO
Macro Library Reference Manual 125
Counting Ranges:
CBD11: 1-0. CBD12: 3-0. CBD14: 15-0. CBD18: 255-0.
Truth Table:
The truth table is the same for all CBD1s.
* CAO = 1 after terminal count, when CAI = 1.CAI = shift registers: serial input; counters: CAscade In,Q = output of flip-flop or latch, x = don’t care, ↑ = rising clock edge.
Input Output
CD CAI CLK Q CAO
1 x x 0 CAI0 0 x Q 00 1 ↑ count down *
Macro Library Reference Manual 126
Q0LX2
CLK
CDCAO
CAI
CD
QD
FD21
CBD11
Macro Library Reference Manual 127
Q1
Q0QI0
QI[0:1]
QI1
QI0
QI1
QI0
QI1
LX2
LX2
QI0
QI0
QI1
QI0
QI1
QI[0:1]
CLK
CD
CAI
CAO
CD
QD
FD21
CD
QD
FD21
CBD12
Macro Library Reference Manual 128
Q3
Q2
Q1
Q0
QI3
QI2
QI1
QI0
QI2
QI[0:3]
QI1QI1
QI2
QI3
QI0QI0
QI3
QI2
QI[0:3]
QI0
QI0
QI1
QI1
QI2
QI3
QI3
QI1
QI0
QI0
QI1
QI2
QI0LX2
LX2
LX2
LX2
CLK
CD
CD
QD
FD21
CAO
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CAI
CBD14
Macro Library Reference Manual 129
Q3QI3
QI0QI5
QI4
QI[0:7]
QI0
QI2
QI3
QI4
QI5
QI6
QI7
QI1
QI0
QI1
QI2
QI3
QI6
QI7QI7
QI6
QI5
QI4
QI2
QI1
Q4
Q2
Q5
Q1
Q6
Q0
Q7
QI4
QI7
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI5
QI4
QI3
QI2
QI1
QI0
QI4
QI3
QI2
QI1
QI0
QI3
QI2
QI1
QI0
QI1
QI0
QI1
QI2
QI3
QI5
QI6
QI7
QI[0:7]
QI2
QI1
QI0
QI0
QI0
LX2
LX2
LX2
LX2
LX2
LX2
LX2
LX2
CD
CLK
CAI
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CAO
CBD18
Macro Library Reference Manual 130
CBD21, CBD22, CBD24, and CBD28
Function: 1-, 2-, 4-, and 8-bit down counters with asynchronousclear, enable, CAI, and CAO.
Availability: CBD21, CBD22, CBD24, and CBD24 are for pDS,ispDS, and ispDS+.
Type:
Soft: CBD21 and CBD22.Hard: CBD24 and CBD28.
Logic Resources – pDS:
* Q0-Qn-1: 2 PT per output.CAO: 1 PT.CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.
** (CAO is a 2-level output).
Macro Port Definition:
CBD21 (Q0,CAO,CAI,CLK,EN,CD);CBD22 (Q0,Q1,CAO,CAI,CLK,EN,CD);CBD24 ([Q0..Q3],CAO,CAI,CLK,EN,CD);
CBD24_1 ([Q0..Q3],CAI,CLK,EN,CD);CBD24_2 (CAO,[Q0..Q3],CAI,EN);
CBD28 ([Q0..Q7],CAO,CAI,CLK,EN,CD);CBD28_1 ([Q0..Q3],CAI,CLK,EN,CD);CBD28_2 ([Q4..Q7],[Q0..Q3],CAI,CLK,EN,CD);CBD28_3 (CAO,[Q0..Q7],CAI,EN);
Counting Ranges:
CBD21: 1-0. CBD22: 3-0. CBD24: 15-0. CBD28: 255-0.
Macro PT GLB Output Level
CBD21 * .5 2 1**CBD22 * .75 3 1**CBD24 * 1.25 5 1**CBD28 * 2.25 9 1**
CBD21
CBD22
CBD24
CBD28
CDCAO
Q0CAI
CDCAO
Q1
Q0CAI
CDCAO
Q3
Q2
Q1
Q0CAI
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CD
CAI
CAO
EN
EN
EN
EN
Macro Library Reference Manual 131
Truth Table:
The truth table is the same for all CBD2s.
* CAO = 1 after terminal count, when CAI = 1 and EN = 1CAI⋅EN = shift registers: serial input; counters:CAscade In, enable for multiplexors and counters, Q = output.
Input Output
CD EN CAI CLK Q CAO
1 x x x 0 CAI⋅EN0 0 x x Q 00 x 0 x Q 00 1 1 ↑ count down *
Macro Library Reference Manual 132
Q0
CAO
LX2
CD
CLK
EN
CAI
CD
QD
FD21
Q0
CBD21
Macro Library Reference Manual 133
Q1
Q0
QI[0:1]
QI1
QI0QI0
QI0
QI1
QI1
QI0
QI1
QI0
QI[0:1]
QI1
QI0
LX2
LX2
CLK
CD
EN
CAI
CD
QD
FD21
CD
QD
FD21
CAO
CBD22
Macro Library Reference Manual 134
QI3
QI2
QI[0:3]
QI0
QI1
QI2
QI3
QI0
QI2
QI1
QI0
QI1
QI0
QI0
QI1
Q0QI0
QI[0:3]
QI1
QI3
QI2
QI0QI0
QI1
QI3QI3
QI2
QI1
QI2
Q1
Q2
Q3LX2
LX2
LX2
LX2
CLK
CD
EN
CAI
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CAO
CBD24
Macro Library Reference Manual 135
Q5
Q4
Q3
Q2
Q1
Q0
Q6
Q7
QI5
QI2
QI2
QI0
QI0
QI1
QI3
QI4
QI6
QI7
QI3
QI2
QI1
QI5
QI4
QI3
QI2
QI1
QI0
QI4
QI3
QI2
QI1
QI0
QI3
QI2
QI0
QI2
QI1
QI0
QI1
QI0
QI0
QI5
QI6
QI7
QI0
QI1
QI3
QI4
QI5
QI6
QI[0:7]
QI1
QI4
CAO
CLK
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
EN
CAI
CD
LX2
LX2
LX2
LX2
LX2
LX2
LX2
LX2QI4
QI7
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI[0:7]
QI0
QI1
QI2
QI3
QI5
QI6
QI7QI7
QI6
QI5
QI4
QI3
QI2
QI1
QI0
CBD28
Macro Library Reference Manual 136
CBD31, CBD32, CBD34, and CBD38
Function: 1-, 2-, 4-, and 8-bit down counters with asynchronousclear, enable, parallel data load, synchronous preset, CAI, and CAO.
Availability: CBD31, CBD32, CBD34, and CBD38 are for pDS,ispDS, and ispDS+.
Type:
Soft: CBD31 and CBD32.Hard: CBD34 and CBD38.
Logic Resources – pDS:
* Q0-Qn-1: 4 PT per output.CAO: 1 PT.CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.
** (CAO is a 2-level output).
Macro Port Definition:
CBD31 (Q0,CAO,D0,CAI,CLK,PS,LD,EN,CD);CBD32 (Q0,Q1,CAO,D0,D1,CAI,CLK,PS,LD,EN,CD);CBD34 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,PS,LD,EN,CD);
CBD34_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CD);CBD34_2 (CAO,[Q0..Q3],CAI,EN);
CBD38 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,PS,LD,EN,CD);CBD38_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CD);CBD38_2 (Q4,Q5,[Q0..Q3],D4,D5,CAI,CLK,PS,LD,EN,CD);CBD38_3 (Q6,Q7,[Q0..Q5],D6,D7,CAI,CLK,PS,LD,EN,CD);CBD38_4 (CAO,[Q0..Q7],CAI,EN);
Counting Ranges:
CBD31: 1-0. CBD32: 3-0. CBD34: 15-0. CBD38: 255-0.
Macro PT GLB Output Level
CBD31 * .5 2 1**CBD32 * .75 3 1**CBD34 * 1.25 5 1**CBD38 * 2.25 9 1**
CBD31 CBD32
CBD34 CBD38
PS
Q0
CAO
EN
CAI
LD
D0
CD
D0
1
LD
CAI
EN
Q1
CAO
Q0
PS
CD
PS
Q0
CAO
Q1
Q2
Q3
EN
CAI
LD
D3
D2
D1
D0
CD
PS
D0
D1
D2
D3
D4
D5
D6
LD
D7
CAI
EN
Q7
Q6
Q5
Q4
Q3
Q2
Q1
CAO
Q0
CD
Macro Library Reference Manual 137
Truth Table:
The truth table is the same for all CBD3s.
* CBD31: CAO = CAI⋅EN⋅D0CBD32: CAO = CAI⋅EN⋅D0⋅D1CBD34: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3CBD38: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3⋅D4⋅D5⋅D6⋅D7
** CAO = 1 after terminal count, when CAI = 1 and EN = 1.CAI⋅EN = shift registers: serial input; counters: CAscade In, enable for multiplexors and counters,d = any pattern of 1s and 0s on an input or set of inputs,Q = output of flip-flop or latch, ↑ = rising clock edge.
Input Output
CD PS LD D EN CAI CLK Q CAO
1 x x x x x x 0 CAI⋅EN0 1 x x x x ↑ 1 00 0 1 d x x ↑ d *0 0 0 x 0 x x Q 00 0 0 x x 0 x Q 00 0 0 x 1 1 ↑ count down **
Macro Library Reference Manual 138
Q0LX2
CAO
CD
CLK
PS
EN
CAI
LD
D0
CD
QD
FD21
CBD31
Macro Library Reference Manual 139
Q0
Q1
QI0
QI1
QI1
QI0
QI1
QI[0:1]
QI0
QI1
QI[0:1]QI0
QI0
QI1
QI0
LX2
LX2
CAI
LD
D0
EN
D1
PS
CD
QD
FD21
CD
QD
FD21
CD
CLK
CAO
CBD32
Macro Library Reference Manual 140
QI[0:3]
QI3
QI0
QI0
QI0
QI1
QI0
QI1
QI2
QI0
QI1
QI2
QI3
QI1
QI2
Q3
Q2
Q1
Q0QI0
QI1
QI2
QI3
QI3
QI2
QI1
QI0
QI[0:3]
QI0
QI1
QI2
QI3
LX2
LX2
LX2
LX2
CD
PS
EN
CAI
LD
D2
D3
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
D1
D0
CLK
CAO
CBD34
Macro Library Reference Manual 141
QI3
QI2QI2
QI3
QI4
QI5
QI6
QI7
QI0
QI1
QI[0:7]
QI2
QI3
QI1
QI0
QI0
QI1
QI0
QI3
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI2
QI1
QI0
QI1
QI0
QI1
QI2
QI0
QI[0:7]
CAO
CD
PS
EN
CAI
LD
D0
D1
D2
D3
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CLK
LX2
LX2
LX2
LX2Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CBD38.1
Macro Library Reference Manual 142
QI7
QI6
QI5
QI4
QI[0:7]
QI4
QI5
QI7
QI6
QI4
QI7
QI6
QI5
QI[0:7]
QI0
QI1
QI2
QI0
QI1
QI2
QI3
QI0
QI1
QI2
QI3
QI4
QI0
QI1
QI2
QI6
QI5
QI4
QI3
QI5
QI4
QI3
LX2
LX2
LX2
LX2
D4
D5
D6
D7
CD
CLK
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CAI
EN
PS
LD
CBD38.2
Macro Library Reference Manual 143
CBD41, CBD42, CBD44, and CBD48
Function: 1-, 2-, 4-, and 8-bit down counters withsynchronous clear, enable, parallel data load, synchronouspreset, CAI, and CAO.
Availability: CBD41, CBD42, CBD44, and CBD48 are for pDS,ispDS, and ispDS+.
Type:
Soft: CBD41 and CBD42.Hard: CBD44 and CBD48.
Logic Resources – pDS:
* Q0-Qn-1: 4 PT per output.CAO: 1 PT.CLK: 1 PT per GLB if Product Term Clock is used.
** (CAO is a 2-level output).
Macro Port Definition:
CBD41 (Q0,CAO,D0,CAI,CLK,PS,LD,EN,CS);CBD42 (Q0,Q1,CAO,D0,D1,CAI,CLK,PS,LD,EN,CS);CBD44 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,PS,LD,EN,CS);
CBD44_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CS);CBD44_2 (CAO,[Q0..Q3],CAI,EN);
CBD48 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,PS,LD,EN,CS);CBD48_2 (Q4,Q5,[Q0..Q3],D4,D5,CAI,CLK,PS,LD,EN,CS);CBD48_3 (Q6,Q7,[Q0..Q5],D6,D7,CAI,CLK,PS,LD,EN,CS);CBD48_4 (CAO,[Q0..Q7],CAI,EN);
Counting Ranges:
CBD41: 1-0. CBD42: 3-0. CBD44: 15-0. CBD48: 255-0.
Macro PT GLB Output Level
CBD41 * .5 2 1**CBD42 * .75 3 1**CBD44 * 1.25 5 1**CBD48 * 2.25 9 1**
CBD41CBD42
CBD44 CBD48
PS
Q0
CAO
EN
CAI
LD
D0
CS
D0
D1
LD
CAI
EN
Q1
CAO
Q0
PS
CS
PS
CAO
Q1
Q2
Q3
EN
CAI
LD
D3
D2
D1
D0
CS
PS
D0
D1
D2
D3
D4
D5
D6
LD
D7
CAI
EN
Q7
Q6
Q5
Q4
Q3
Q2
Q1
CAO
Q0
CS
Macro Library Reference Manual 144
Truth Table:
The truth table is the same for all CBD4s.
* CBD41: CAO = CAI⋅EN⋅D0CBD42: CAO = CAI⋅EN⋅D0⋅D1CBD44: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3CBD48: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3⋅D4⋅D5⋅D6⋅D7
** CAO = 1 after terminal count, when CAI = 1 and EN = 1.CAI⋅EN = shift registers: serial input; counters: CAscade In, enable for multiplexors and counters,d = any pattern of 1s and 0s on an input or set of inputs, Q = output of flip-flop or latch, ↑ = rising clock edge.
Input Output
PS CS LD D EN CAI CLK Q CAO
1 x x x x x ↑ 1 00 1 x x x x ↑ 0 CAI⋅EN0 0 1 d x x ↑ d *0 0 0 x 0 x x Q 00 0 0 x x 0 x Q 00 0 0 x 1 1 ↑ count down **
Macro Library Reference Manual 145
Q0LX2 QD
FD11CLK
CAO
PS
CS
EN
CAI
LD
D0
CBD41
Macro Library Reference Manual 146
Q1
Q0QI0
QI1
QI[0:1]
QI0
QI1
QI0
QI1
QI1
QI0
QI1
QI0
QI0
QI[0:1]
LX2
LX2
CS
D1
PS
EN
CAI
D0
LD
QD
FD11
QD
FD11
CLK
CAO
CBD42
Macro Library Reference Manual 147
Q0
Q1
Q2
Q3
QI0
QI2
QI3
QI1
QI0
QI3
QI2
QI1
QI[0:3]
QI2
QI3
QI0
QI1
QI2
QI1
QI[0:3]
QI2
QI3
QI3
QI1
QI0
QI0
QI1
QI2
QI1
QI0
QI0
QI0
LX2
LX2
LX2
LX2
CAI
EN
PS
CS
D3
D2
D1
D0
LD
CLK
QD
FD11
QD
FD11
QD
FD11
QD
FD11
CAO
CBD44
Macro Library Reference Manual 148
Q0
Q1
Q2
Q3QI3
QI2
QI1
QI0
QI[0:7]
QI2
QI3
QI1
QI0
QI0
QI1
QI4
QI5
QI6
QI3QI7
QI2
Q4
Q5
Q6
Q7
QI1
QI4
QI7
QI6
QI5
QI[0:7]
QI2
QI3
QI0
QI1
QI2
QI1
QI0
QI0
QI0
QI2
QI1
QI0
QI3
LX2
LX2
LX2
LX2
QD
FD11
QD
FD11
QD
FD11
QD
FD11
CLK
LD
D0
D1
D2
D3
CS
PS
EN
CAI
CAO
CBD48.1
Macro Library Reference Manual 149
QI0
QI7
QI6
QI5
QI[0:7]
QI2
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI5
QI4
QI3
QI1
QI4
QI0
QI1
QI2
QI3
QI0
QI1
QI2
QI3
QI4
PS
LX2
LX2
LX2
LX2
LD
D4
D5
D6
D7
CS
CLK
QD
FD11
QD
FD11
QD
FD11
QD
FD11
EN
CAI
QI5
QI4
QI6
QI7
QI[0:7]
QI4
QI5
QI6
QI7
CBD48.2
Macro Library Reference Manual 150
CBD516 and CBD616
Function: 16-bit down counters with asynchronous clear andenable. CBD616 also has CAO.
Availability: CBD516 andCBD616 are for pDS, ispDS, andispDS+.
Type: Hard
Logic Resources – pDS:
* Q0-Qn-1: 2 PT per output.CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.
** Q0-Qn-1: 2 PT per output.CAO: 1 PT.CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.
*** (CAO is a 2-level output).
Macro Port Definition:
CBD516 ([Q0..Q15],CLK,EN,CD);CBD516_1 ([Q0..Q3],CLK,EN,CD);CBD516_2 ([Q4..Q7],[Q0..Q3],CLK,EN,CD);CBD516_3 ([Q8..Q11],[Q0..Q7],CLK,EN,CD);CBD516_4 ([Q12..Q15],[Q0..Q11],CLK,EN,CD);
CBD616 ([Q0..Q15],CAO,CLK,EN,CD);CBD616_1 ([Q0..Q3],CLK,EN,CD);CBD616_2 ([Q4..Q7],[Q0..Q3],CLK,EN,CD);CBD616_3 ([Q8..Q11],[Q0..Q7],CLK,EN,CD);CBD616_4 (Q12,Q13,[Q0..Q11],CLK,EN,CD);CBD616_5 (Q14,Q15,CAO,[Q0..Q13],CLK,EN,CD);
Counting Ranges:
CBD516: 65,535-0. CBD616: 65,535-0.
Macro PT GLB Output Level
CBD516 * 4 16 1CBD616 ** 4.25 17 1***
CBD516
CBD616
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q10
Q11
Q12
Q13
Q14
CD
Q15
Q9
EN
EN
Q9
Q15
CAO
CD
Q14
Q13
Q12
Q11
Q10
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Macro Library Reference Manual 151
Truth Table:
Gray areas (CAO) apply only to the CBD616.
* CAO = 1 after terminal count, when EN = 1 and terminal count = 0.EN = enable for multiplexors and counters, Q = output of flip-flop or latch,x = don’t care, ↑ = rising clock edge.
Input Output
CD EN CLK Q CAO
1 x x 0 EN0 0 x Q 00 1 ↑ count down *
Macro Library Reference Manual 152
Q9
LX2
LX2
LX2
LX2
CD
CLK
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
QI1
QI0
QI1
QI0
QI1
QI2
QI0
QI2
QI[0:14]
QI0
QI3
EN
Q3
Q2
Q1
Q0
Q8
Q7
Q6
Q5
Q4
QI12
QI13
QI14
QI15
QI11
QI10
QI9
QI2QI8
QI7
QI3
QI1
QI0
QI0
QI1
QI2
QI3
QI[0:15]
QI0
QI2
QI4
QI1QI5
QI6
QI3
Q15
Q14
Q13
Q12
Q11
Q10
CBD516.1
Macro Library Reference Manual 153
QI6
QI6
QI4
QI4
QI0
QI1
QI2
QI3
QI5
QI7
QI0
QI1
QI2
QI3
QI4
QI5
QI0
QI1
QI2
QI3
QI4
QI5
QI0
QI1
QI2
QI3
QI[0:14]
QI6
QI4
QI7
QI[0:15]
QI6
QI5
QI4
QI5
QI7
EN
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
CLK
LX2
LX2
LX2
LX2
CBD516.2
Macro Library Reference Manual 154
QI11
QI9QI9
QI8
QI[0:15]
QI8
QI10QI10
QI11
QI0
QI0
QI1
QI3
QI2
QI4
QI5
QI6
QI8
QI[0:14]
QI11
QI10
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI9
QI8
QI7
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI9
QI9
QI3
QI2
QI1
QI0
QI4
QI5
QI6
QI7
QI8
QI7
QI10
QI8
EN
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CLK
CD
LX2
LX2
LX2
LX2
CBD516.3
Macro Library Reference Manual 155
QI13
QI12
QI14
QI12
QI13
QI14
QI15
QI[0:15]
QI15
QI9
QI3
QI5
QI12
QI2
QI[0:14]
QI0
QI1
QI2
QI4
QI5
QI6
QI7
QI8
QI10
QI11
QI12
QI13
QI14
QI13
QI12
QI11
QI10
QI9
QI8
QI7
QI6
QI4
QI3
QI2
QI1
QI0
QI14
QI13
QI12
QI0
QI1
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
EN
CLK
CD
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
LX2
LX2
LX2
LX2
CBD516.4
Macro Library Reference Manual 156
Q15
Q14
Q13
Q12
Q11
Q10
Q9
QI13
QI15
QI14
QI3
QI11
QI10
QI8
QI7
QI6
QI1
QI0
QI[0:15]
QI0
QI1
QI2
QI3
QI0
QI2
QI3
QI4
QI1QI5
QI2
QI9
QI12
Q4
Q5
Q6
Q7
Q8
Q0
Q1
Q2
Q3
QI2
QI0
QI0
QI1
QI[0:15]QI0
QI1
QI3
QI2
QI0
QI1
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI13
QI14
QI15
EN
LX2
LX2
LX2
LX2
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CAO
CLK
CD
CBD616.1
Macro Library Reference Manual 157
QI6
QI4
QI3
QI4
QI2
QI3
QI0
QI1
QI2
QI4
QI5
QI6
QI7
QI0
QI1
QI2
QI3
QI5
QI0
QI1
QI3
QI4
QI5
QI0
QI1
QI2
QI[0:15]
QI6
QI5
QI4
QI[0:15]
QI7
QI6
QI5
QI4
QI7LX2
LX2
LX2
LX2
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
CLK
EN
CBD616.2
Macro Library Reference Manual 158
QI8
QI9
QI[0:15]
QI10
QI9
QI8
QI11
QI10
QI11
QI9
QI[0:15]
QI0
QI1
QI3
QI2
QI4
QI5
QI6
QI7
QI8
QI11
QI10
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI10
QI9
QI8
QI7
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI3
QI2
QI1
QI0
QI4
QI5
QI6
QI7
QI8
QI9
LX2
LX2
LX2
LX2
EN
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CLK
CD
CBD616.3
Macro Library Reference Manual 159
QI13
QI12
QI14
QI12
QI13
QI14
QI15
QI[0:15]
QI15
EN
CLK
CD
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
LX2
LX2
LX2
LX2
QI15
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI5
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI13
QI14
QI13
QI12
QI11
QI10
QI9
QI8
QI7
QI6
QI4
QI3
QI2
QI1
QI0
QI[0:15]QI12
QI13
QI14
CBD616.4
Macro Library Reference Manual 160
CBU11, CBU12, CBU14, and CBU18
Function: 1-, 2-, 4-, and 8-bit up counters with asynchronous clear,CAI, and CAO.
Availability: CBU11, CBU12, CBU14, and CBU18 are for pDS,ispDS, and ispDS+.
Type:
Soft: CBU11 and CBU12.Hard: CBU14 and CBU18.
Logic Resources – pDS:
* Q0-Qn-1: 2 PT per output.CAO: 1 PT.CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.
** (CAO is a 2-level output).
Macro Port Definition:
CBU11 (Q0,CAO,CAI,CLK,CD);CBU12 (Q0,Q1,CAO,CAI,CLK,CD);CBU14 ([Q0..Q3],CAO,CAI,CLK,CD);
CBU14_1 ([Q0..Q3],CAI,CLK,CD);CBU14_2 (CAO,[Q0..Q3],CAI);
CBU18 ([Q0..Q7],CAO,CAI,CLK,CD);CBU18_1 ([Q0..Q3],CAI,CLK,CD);CBU18_2 ([Q4..Q7],[Q0..Q3],CAI,CLK,CD);CBU18_3 (CAO,[Q0..Q7],CAI);
Counting Ranges:
CBU11: 0-1. CBU12: 0-3. CBU14: 0-15. CBU18: 0-255.
Macro PT GLB Output Level
CBU11 * .5 2 1**CBU12 * .75 3 1**CBU14 * 1.25 5 1**CBU18 * 2.25 9 1**
CBU11
CBU12
CBU14
CBU18
CD
CAO
Q0CAI
CD
CAO
Q1
Q0CAI
CD
CAO
Q3
Q2
Q1
Q0CAI
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CD
CAI
CAO
Macro Library Reference Manual 161
Truth Table:
The truth table is the same for all CBU1s.
* CAO = 1 after terminal count, when CAI = 1Q = output of flip-flop or latch,x = don’t care, ↑ = rising clock edge.
Input Output
CD CAI CLK Q CAO
1 x x 0 00 0 x Q 00 1 ↑ count up *
Macro Library Reference Manual 162
LX2
CD
CAO
CD
QD
FD21
Q0CAI
CLK
CBU11
Macro Library Reference Manual 163
QI1
QI0
QI1
QI0
QI1
QI0
QI[0:1]
QI0
QI0 QI1
Q0
LX2
LX2
CLK CD
CAI
Q1
CAO
CD
QD
FD21
CD
QD
FD21
CBU12
Macro Library Reference Manual 164
CLK
CD
QD
FD21
CD
QD
FD21
CAI
CAO
CD
LX2
LX2
LX2
LX2
CD
QD
FD21
CD
QD
FD21
QI3
QI2
QI0
QI1
QI2
QI0
QI1
QI3
QI0
QI1
QI2
QI0
QI0
QI[0:3]
QI3
QI2
QI1
QI0
QI1
QI0
QI1
QI3
QI2
Q0
Q1
Q2
Q3
CBU14
Macro Library Reference Manual 165
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
QI[0:7]
QI0
QI1
QI0
QI2
QI5
QI0
QI1
QI2
QI3
QI4
QI6
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI5
QI4
QI3
QI2
QI1
QI0
QI3
QI2
QI1
QI0
QI4
QI2
QI1
QI0
QI3
QI1
QI0
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI7
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CAI
CD
QD
FD21
CD
QD
FD21
CAO
CD
QD
FD21
CLK
CD
LX2
LX2
LX2
LX2
LX2
LX2
LX2
LX2
CBU18
Macro Library Reference Manual 166
CBU21, CBU22, CBU24, and CBU28
Function: 1-, 2-, 4-, and 8-bit up counters with asynchronous clear,enable, CAI, and CAO.
Availability: CBU21, CBU22, CBU24, and CBU28 are for pDS,ispDS, and ispDS+.
Type:
Soft: CBU21 and CBU22.Hard: CBU24 and CBU28.
Logic Resources – pDS:
* Q0-Qn-1: 2 PT per output.CAO: 1 PT.CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.
** (CAO is a 2-level output).
Macro Port Definition:
CBU21 (Q0,CAO,CAI,CLK,EN,CD);CBU22 (Q0,Q1,CAO,CAI,CLK,EN,CD);CBU24 ([Q0..Q3],CAO,CAI,CLK,EN,CD);
CBU24_1 ([Q0..Q3],CAI,CLK,EN,CD);CBU24_2 (CAO,[Q0..Q3],CAI,EN);
CBU28 ([Q0..Q7],CAO,CAI,CLK,EN,CD);CBU28_1 ([Q0..Q3],CAI,CLK,EN,CD);CBU28_2 ([Q4..Q7],[Q0..Q3],CAI,CLK,EN,CD);CBU28_3 (CAO,[Q0..Q7],CAI,EN);
Counting Ranges:
CBU21: 0-1. CBU22: 0-3. CBU24: 0-15. CBU28: 0-255.
Macro PT GLB Output Level
CBU21 * .5 2 1**CBU22 * .75 3 1**CBU24 * 1.25 5 1**CBU28 * 2.25 9 1**
CBU21
CBU22
CBU24
CBU28
CDCAO
Q0CAI
CDCAO
Q1
Q0CAI
CDCAO
Q3
Q2
Q1
Q0CAI
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CD
CAI
CAO
EN
EN
EN
EN
Macro Library Reference Manual 167
Truth Table:
The truth table is the same for all CBU2s.
* CAO = 1 after terminal count, when CAI = 1 and EN = 1Q = output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Input Output
CD EN CAI CLK Q CAO
1 x x x 0 00 0 x x Q 00 x 0 x Q 00 1 1 ↑ count up *
Macro Library Reference Manual 168
Q0LX2
CLK
CD
CAO
EN
CAI
CD
QD
FD21
CBU21
Macro Library Reference Manual 169
QI1
QI1
QI0
QI1
QI0
QI1
QI0
QI[0:1]
QI0
QI0
CD
QD
FD21Q0
Q1
LX2
LX2
CD
CAI
EN
CD
QD
FD21
CLK
CAO
CBU22
Macro Library Reference Manual 170
QI2
QI0
QI0
QI1
QI1
QI0
QI[0:3]
QI0
QI1
QI0
QI0
QI1
QI0
QI1
QI2
QI3
QI2
QI2
QI3QI3
QI3
QI2
QI1
Q0
Q1
Q3
Q2
LX2
LX2
LX2
LX2
EN
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CAI
CD
CLK
CAO
CBU24
Macro Library Reference Manual 171
Q0
Q1QI1
QI0
QI5
QI7
QI6
QI4
QI6
QI7
QI7
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI5
QI4
QI2
QI[0:7]
QI0
QI1
QI0
QI2
QI4
QI5
QI0
QI1
QI2
QI3
QI4
QI5
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI6
QI4
QI3
QI2
QI1
QI0
QI3
QI2
QI1
QI0
QI2
QI1
QI0
QI3
QI1
QI0
QI0
QI1
QI3
QI2
QI3
Q4
Q5
Q6
Q7
Q3
Q2
CD
QD
FD21
CD
QD
FD21
CLK
CAI
EN
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CAO
CD
QD
FD21
CD
QD
FD21
CD
CD
QD
FD21
LX2
LX2
LX2
LX2
LX2
LX2
LX2
LX2
CBU28
Macro Library Reference Manual 172
CBU31, CBU32, CBU34, and CBU38
Function: 1-, 2-, 4-, and 8-bit up counters with asynchronous clear,enable, parallel data load, synchronous preset, CAI, and CAO.
Availability: CBU31, CBU32, CBU34, and CBU38 are for pDS,ispDS, and ispDS+.
Type:
Soft: CBU31 and CBU32.Hard: CBU34 and CBU38.
Logic Resources – pDS:
* Q0-Qn-1: 4 PT per output.CAO: 1 PT.CLK: 1 PT per GLB if Product Term Clock is used. CD: 1PT per GLB.
** (CAO is a 2-level output).
Macro Port Definition:
CBU31 (Q0,CAO,D0,CAI,CLK,PS,LD,EN,CD);CBU32 (Q0,Q1,CAO,D0,D1,CAI,CLK,PS,LD,EN,CD);CBU34 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,PS,LD,EN,CD);
CBU34_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CD);CBU34_2 (CAO,[Q0..Q3],CAI,EN);
CBU38 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,PS,LD,EN,CD);CBU38_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CD);CBU38_2 (Q4,Q5,[Q0..Q3],D4,D5,CAI,CLK,PS,LD,EN,CD);CBU38_3 (Q6,Q7,[Q0..Q5],D6,D7,CAI,CLK,PS,LD,EN,CD);CBU38_4 (CAO,[Q0..Q7],CAI,EN);
Counting Ranges:
CBU31: 0-1. CBU32: 0-3. CBU34: 0-15. CBU38: 0-255.
Macro PT GLB Output Level
CBU31 * .5 2 1**CBU32 * .75 3 1**CBU34 * 1.25 5 1**CBU38 * 2.25 9 1**
CBU31 CBU32
CBU34 CBU38
PS
Q0
CAO
EN
CAI
LD
D0
CD
D0
D1
LD
CAI
EN
Q1
CAO
Q0
PS
CD
PS
Q0
CAO
Q1
Q2
Q3
EN
CAI
LD
D3
D2
D1
D0
CD
PS
D0
D1
D2
D3
D4
D5
D6
LD
D7
CAI
EN
Q7
Q6
Q5
Q4
Q3
Q2
Q1
CAO
Q0
CD
Macro Library Reference Manual 173
Truth Table:
he truth table is the same for all CBU3s.
* CBU31: CAO = CAI⋅EN⋅D0CBU32: CAO = CAI⋅EN⋅D0⋅D1CBU34: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3CBU38: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3⋅D4⋅D5⋅D6⋅D7
** CAO = 1 after terminal count, when CAI = 1 and EN = 1.CAI⋅EN = shift registers: serial input, counters:CAscade In, enable for multiplexors and counters,d = any pattern of 1s and 0s on an input or set of inputs,Q = output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Input Output
CD PS LD D EN CAI CLK Q CAO
1 x x x x x x 0 00 1 x x x x ↑ 1 CAI⋅EN0 0 1 d x x ↑ d *0 0 0 x 0 x x Q 00 0 0 x x 0 x Q 00 0 0 x 1 1 ↑ count up **
Macro Library Reference Manual 174
Q0LX2
PS
EN
CAI
LD
D0
CAO
CLK
CD
QD
FD21
CD
CBU31
Macro Library Reference Manual 175
CD
CLK
LX2
LX2
PS
D1
EN
CAI
D0
LD
CAO
CD
QD
FD21
CD
QD
FD21
Q1
Q0
QI1
QI[0:1]
QI0
QI1
QI0
QI0
QI1
QI0
QI1
QI0
CBU32
Macro Library Reference Manual 176
Q0
QI2
QI[0:3]
QI0
QI1
QI0
QI0
QI1
QI0
QI1
QI2
QI3
QI2
QI0
QI1
QI3
QI0
QI1
QI2
QI3
QI3
QI2
QI1
QI0
Q1
Q2
Q3
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
LX2
LX2
LX2
LX2
D2
D1
D0
PS
EN
CAI
LD
CD
CD
QD
FD21
CAO
CLK
D3
CBU34
Macro Library Reference Manual 177
Q1
Q0QI0
QI1
QI2
QI0
QI7
QI6
QI5
QI4
QI3
QI2
QI1
QI3QI7
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI[0:7]
QI2
QI3
QI2
QI1
QI0
QI1
QI0
QI0
QI1
QI0
Q2
Q3
Q4
Q5
Q6
Q7
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
LX2
LX2
LX2
LX2
D3
D2
D1
D0
LD
PS
EN
CAI
CLK
CD
CAO
CD
QD
FD21
CBU38.1
Macro Library Reference Manual 178
QI6
QI0
QI4
QI5
QI5
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI4
QI3
QI2
QI1
QI6
QI4
QI3
QI2
QI1
QI0
QI5
QI3
QI2
QI1
QI0
QI4
QI7
QI[0:7]
CD
QD
FD21
PS
LX2
LX2
LX2
LX2
D4
D5
D6
D7
CD
QD
FD21
CD
CLK
LD
CAI
EN
CD
QD
FD21
CD
QD
FD21
CBU38.2
Macro Library Reference Manual 179
CBU41, CBU42, CBU44, and CBU48
Function: 1-, 2-, 4-, and 8-bit up counters with synchronous clear,enable, parallel data load, synchronous preset, CAI, and CAO.
Availability: CBU41, CBU42, CBU44, and CBU48 are for pDS,ispDS, and ispDS+.
Type:
Soft: CBU41 and CBU42.Hard: CBU44 and CBU48.
Logic Resources – pDS:
* Q0-Qn-1: 4 PT per output.CAO: 1 PT.CLK: 1 PT per GLB if Product Term Clock is used.
** (CAO is a 2-level output).
Macro Port Definition:
CBU41 (Q0,CAO,D0,CAI,CLK,PS,LD,EN,CS);CBU42 (Q0,Q1,CAO,D0,D1,CAI,CLK,PS,LD,EN,CS);CBU44 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,PS,LD,EN,CS);
CBU44_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CS);CBU44_2 (CAO,[Q0..Q3],CAI,EN);
CBU48 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,PS,LD,EN,CS);CBU48_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CS);CBU48_2 (Q4,Q5,[Q0..Q3],D4,D5,CAI,CLK,PS,LD,EN,CS);CBU48_3 (Q6,Q7,[Q0..Q5],D6,D7,CAI,CLK,PS,LD,EN,CS);CBU48_4 (CAO,[Q0..Q7],CAI,EN);
Counting Ranges:
CBU41: 0-1. CBU42: 0-3. CBU44: 0-15. CBU48: 0-255.
Macro PT GLB Output Level
CBU41 * .5 2 1**CBU42 * .75 3 1**CBU44 * 1.25 5 1**CBU48 * 2.25 9 1**
CBU41 CBU42
CBU44 CBU48
PS
Q0
CAO
EN
CAI
LD
D0
CS
D0
D1
LD
CAI
EN
Q1
CAO
Q0
PS
CS
PS
Q0
CAO
Q1
Q2
Q3
EN
CAI
LD
D3
D2
D1
D0
CS
PS
D0
D1
D2
D3
D4
D5
D6
LD
D7
CAI
EN
Q7
Q6
Q5
Q4
Q3
Q2
Q1
CAO
Q0
CS
Macro Library Reference Manual 180
Truth Table:
The truth table is the same for all CBU4s.
* CBU41: CAO = CAI⋅EN⋅D0CBU42: CAO = CAI⋅EN⋅D0⋅DCBU44: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3CBU48: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3⋅D4⋅D5⋅D6⋅D7
** CAO = 1 after terminal count, when CAI = 1 and EN = 1.CAI⋅EN = shift registers: serial input, counters:CAscade In, enable for multiplexors and counters,d = any pattern of 1s and 0s on an input or set of inputs,Q = output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Input Output
PS CS LD D EN CAI CLK Q CAO
1 x x x x x ↑ 1 CAI⋅EN0 1 x x x x ↑ 0 00 0 1 d x x ↑ d *0 0 0 x 0 x x Q 00 0 0 x x 0 x Q 00 0 0 x 1 1 ↑ count up **
Macro Library Reference Manual 181
Q0
PS
CLK
QD
FD11
D0
LD
CAI
EN
CS
LX2
CAO
CBU41
Macro Library Reference Manual 182
Q0QI0
QI1
QI0
QI0
QI[0:1]
QI0
QI1
QI0
QI1
QI1 Q1
LX2
LX2
LD
D0
CAI
EN
PS
D1
CS
CLK
QD
FD11
QD
FD11
CAO
CBU42
Macro Library Reference Manual 183
Q0QI0
QI2
QI[0:3]
QI0
QI1
QI0
QI2
QI0
QI1
QI3
QI0
QI1
QI2
QI0
QI1
QI3
QI0
QI1
QI2
QI3
QI3
QI2
QI1 Q1
Q2
Q3
QD
FD11
LX2
LX2
LX2
LX2
D2
QD
FD11
LD
CAI
EN
QD
FD11
CLK
PS
D0
D1
D3
QD
FD11
CAOCS
CBU44
Macro Library Reference Manual 184
Q0QI0
QI[0:7]
QI0
QI1
QI0
QI2
QI1
QI0
QI3
QI1
QI0
QI2
QI0
QI1
QI2
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI3QI7
QI6
QI5
QI4
QI3
QI2
QI1 Q1
Q2
Q4
Q3
Q7
Q6
Q5
QD
FD11
QD
FD11
LX2
LX2
LX2
LX2
CLK
LD
EN
CAI
CS
CAO
QD
FD11
QD
FD11
D3
D2
D1
PS
D0
CBU48.1
Macro Library Reference Manual 185
QI7
QI4
QI6
QI5
QI4
QI[0:7]
QI5
QI0
QI1
QI2
QI3
QI4
QI0
QI1
QI2
QI3
QI4
QI5
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI6
QI3
QI0
QI1
QI2
QD
FD11
QD
FD11
LX2
LX2
LX2
LX2
CAI
PS
EN
LD
CLK
CS
QD
FD11
QD
FD11
D7
D6
D5
D4
CBU48.2
Macro Library Reference Manual 186
CBU516 and CBU616
Function: 16-bit up counters with asynchronous clear and enable.CBU616 also has CAO.
Availability: CBU516 and CBU616 are for pDS, ispDS, andispDS+.
Type: Hard
Logic Resources – pDS:
* Q0-Qn-1: 2 PT per output.CLK: 1 PT per GLB if Product Term Clock is used. CD: 1PT per GLB.
** (CAO is a 2-level output).
Macro Port Definition:
CBU516 ([Q0..Q15],CLK,EN,CD);CBU516_1 ([Q0..Q3],CLK,EN,CD);CBU516_2 ([Q4..Q7],[Q0..Q3],CLK,EN,CD);CBU516_3 ([Q8..Q11],[Q0..Q7],CLK,EN,CD);CBU516_4 ([Q12..Q15],[Q0..Q11],CLK,EN,CD);
CBU616 ([Q0..Q15],CAO,CLK,EN,CD);CBU616_1 ([Q0..Q3],CLK,EN,CD);CBU616_2 ([Q4..Q7],[Q0..Q3],CLK,EN,CD);CBU616_3 ([Q8..Q11],[Q0..Q7],CLK,EN,CD);CBU616_4 (Q12,Q13,[Q0..Q11],CLK,EN,CD);CBU616_5 (Q14,Q15,CAO,[Q0..Q13],CLK,EN,CD);
Counting Ranges:
CBU516: 0-65,535. CBU616: 0-65,535.
Macro PT GLB Output Level
CBU516 * 4 16 1CBU616 * 4.25 17 1**
CBU516
CBU616
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q10
Q11
Q12
Q13
Q14
CD
Q15
Q9
EN
EN
Q9
Q15
CAOCD
Q14
Q13
Q12
Q11
Q10
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Macro Library Reference Manual 187
Truth Table:
Gray areas (CAO) apply only to the CBU616.
* CAO = 1 after terminal count,when EN = 1 and each terminal count bit = 1.Q = output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Input Output
CD EN CLK Q CAO
1 x CLK 0 00 0 x Q 00 1 ↑ count up *
Macro Library Reference Manual 188
QI8QI2
QI7
QI6
QI5
QI1
QI3
QI2
QI0
QI[0:15]
QI0
QI1
QI0
QI2
QI0
QI1
QI2
QI1
QI0
QI3
QI0
QI1
QI4
QI3
QI15
QI14
QI13
QI12
QI11
QI10
QI9
Q12
Q13
Q14
Q15
Q8
Q9
Q10
Q11
Q6
Q7
Q1
Q0
Q2
Q3
Q4
Q5
LX2
LX2
LX2
LX2
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
CLK
CD
QD
FD21
EN
CBU516.1
Macro Library Reference Manual 189
CD
QD
FD21
LX2
LX2
LX2
LX2
QI0
QI2
QI1
QI3
QI4
QI5
QI6
QI0
QI1
QI2
QI3
QI4
QI5
QI0
QI1
QI2
QI3
QI4
QI0
QI1
QI2
QI3
QI[0:15]
QI4
QI5
QI7
QI4
QI5
QI6
QI7
QI6
EN
CD
QD
FD21
CD
QD
FD21
CLK CD
CD
QD
FD21
CBU516.2
Macro Library Reference Manual 190
LX2
LX2
LX2
LX2
CD
QD
FD21
CD
QD
FD21
CLK
CD
QD
FD21
CD
QD
FD21
CD
EN
QI11
QI10
QI9
QI8
QI11
QI10
QI9
QI[0:15]
QI8
QI7
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI8
QI7
QI6
QI5
QI4
QI2
QI3
QI1
QI0
QI9
QI8
QI7
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI10
QI9
QI8
QI7
QI6
QI5
QI4
QI2
QI3
QI1
QI0
CBU516.3
Macro Library Reference Manual 191
LX2
LX2
LX2
LX2
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
EN
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI13
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI11
QI14
QI9
QI6
QI5
QI3
QI1
QI0
QI2
QI4
QI7
QI8
QI10
QI11
QI12
QI13
QI10
QI8
QI7
QI9
QI6
QI5
QI4
QI3
QI1
QI0
QI2
QI13
QI12
QI14
QI15QI15
QI14
QI13
QI12
QI[0:15]
CLK CD
CBU516.4
Macro Library Reference Manual 192
Q15QI15
QI13
QI14
QI11
QI10
QI9
QI5
QI1
QI1QI0
QI[0:15]
QI0
QI1
QI0
QI2
QI0
QI1
QI0
QI1
QI2
QI3
QI0
QI2
QI3
QI4
QI6
QI7
QI2QI8
QI15
QI14
QI13
QI12
QI11
QI10
QI9
QI8
QI7
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI12
QI3
Q13
Q14
Q12
Q6
Q7
Q8
Q9
Q10
Q11
CAO
Q0
Q1
Q2
Q3
Q4
Q5
LX2
LX2
LX2
LX2
EN
CD
QD
FD21CLK
CD
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
CBU616.1
Macro Library Reference Manual 193
CD
QD
FD21
CDCLK
CD
QD
FD21
CD
QD
FD21
EN
QI6
QI7
QI6
QI5
QI4
QI7
QI5
QI4
QI[0:15]
QI3
QI2
QI1
QI0
QI4
QI3
QI2
QI1
QI0
QI5
QI4
QI3
QI2
QI1
QI0
QI6
QI5
QI4
QI3
QI1
QI2
QI0
LX2
LX2
LX2
LX2
CD
QD
FD21
CBU616.3
Macro Library Reference Manual 194
QI0
QI1
QI3
QI2
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI0
QI1
QI3
QI2
QI4
QI5
QI6
QI7
QI8
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI[0:15]
QI9
QI10
QI11
QI8
QI9
QI10
QI11
EN
CD
CD
QD
FD21
CD
QD
FD21
CLK
CD
QD
FD21
CD
QD
FD21
LX2
LX2
LX2
LX2
CBU616.4
Macro Library Reference Manual 195
CBU716
Function: 16-bit up counter with asynchronous clear, enable,parallel data load and carry out for 3K device only.
Availability: CBU716 is for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
* Q0- Q15: 3 PT. CAO: 1 PT.
Macro Port Definition:
CBU716 ([Q0..Q15],CAO,CLK,EN,LD,CD,CAI,[D0..D15]);CBU716_1 ([Q0..Q3],[D0..D3],CAI,CLK,LD,EN,CD);CBU716_2 ([Q4..Q7],[Q0..Q3],[D4..D7],CAI,CLK,
LD,EN,CD);CBU716_3 ([Q8..Q11],[Q0..Q7],[D8..D11],CAI,CLK,
LD,EN,CD);CBU716_4 ([Q12..Q15],[Q0..Q11],[D12..D15],
CAI,CLK,LD,EN,CD);CBU716_5 (CAO,[Q0..Q15],CAI,EN);
Counting Ranges:
0 - 65,535
Truth Table:
* CBU716: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3⋅D4⋅D5⋅D6⋅D7⋅D8⋅D9⋅D10⋅D11⋅D12⋅D13⋅D14⋅D15.** CAO = 1 after terminal count, when CAI = 1 and EN = 1.
Macro PT GLB Output Level
CBU716 * 4.25 17 1
Input Output
CD LD D EN CAI CLK Q CAO
1 X X X X X 0 CAI • EN0 1 d X X ↑ d *0 0 X 0 X X Q 00 0 X X 0 X Q 00 0 X 1 1 ↑ count up **
CBU716
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q10
Q11
Q12
Q13
Q14
CD
Q15
Q9
CAI
D0
D1
D2
D3
D4
D5
D6
D7
D8
D10
D11
D12
D13
D14
D15
D9
LD
EN
CAO
Macro Library Reference Manual 196
EN
QI4
QI0
QI4
QI1
QI2
QI3
QI2
QI10
QI15
QI14
QI3
QI11
QI10
QI2
QI6
QI1
QI3
QI0
QI[0:15]
QI0
QI1
QI0
QI2
QI0
QI1
QI3
QI0
QI1
QI2
QI4
QI5
QI7
QI8
QI9
QI12
QI13
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI11
QI12
QI13
QI14
QI15
QI0
QI1
LX2
D4
Q4
CD
CLK
LD LX2
CD
QD
FD21
D0
CAI
EN
LX2
CD
QD
FD21
D1
LX2
CD
QD
FD21
D2
LX2
CD
QD
FD21
D3
Q3
Q2
Q1
Q0
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
CAO
CD
QD
FD21
CBU716.1
Macro Library Reference Manual 197
LX2
D8
CD
QD
FD21
CD
QD
FD21
D5
LX2
CD
QD
FD21
D6
LX2
CD
QD
FD21
D7
LX2LD
CAI
EN
CD
CLK
QI8
QI4
QI5
QI7
QI6
QI3
QI2
QI1
QI0
QI8
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI5
QI4
QI3
QI2
QI1
QI0
QI6
QI4
QI3
QI2
QI1
QI0
QI5
QI[0:15]
QI5
QI6
QI7
CBU716.2
Macro Library Reference Manual 198
CLK
CD
QD
FD21
LX2
D9
LX2
D10
D11
LX2
CD
QD
FD21
CD
QD
FD21
CD
LD
CAI
EN
QI6
QI7
QI10
QI9
QI8
QI4
QI2
QI11
QI8
QI7
QI5
QI4
QI3
QI2
QI8
QI7
QI11
QI10
QI9
QI9
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI10
QI0
QI1
QI6
QI9
QI0
QI1
QI3
QI5
QI[0:15]
CBU716.3
Macro Library Reference Manual 199
QI6
QI11
QI8
QI12
QI[0:15]
QI13
QI12
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI9
QI10
QI13
QI0
QI1
QI2
QI3
QI4
QI5
QI9
QI11
QI12
QI10
QI8
QI7
LD
CAI
EN
CD
CLK
LX2
D12
D13
CD
QD
FD21
LX2
CD
QD
FD21
CBU716.4
Macro Library Reference Manual 200
QI4
QI5
QI6
QI7
QI11
QI14
QI0
QI1
QI15
QI12
QI13
QI14
QI11
QI10
QI9
QI8
QI5
QI4
QI3
QI2
QI15
QI[0:15]
QI14
QI6
QI7
QI8
QI9
QI13
QI10
QI12
QI2
QI1
QI0
QI3
EN
CAI
LX2
CD
QD
FD21
CD
LD
D14
D15
LX2
CD
QD
FD21CLK
CBU716.5
Macro Library Reference Manual 201
CBUD1, CBUD2, CBUD4, and CBUD8
Function: 1-, 2-, 4-, and 8-bit up/down counters with asynchronousclear, synchronous clear, enable, parallel data load, synchronouspreset, CAI, and CAO.
Availability: CBUD1, CBUD2, CBUD4, and CBUD8 are for pDS,ispDS, and ispDS+.
Type:
Soft: CBUD1 and CBUD2.Hard: CBUD4 and CBUD8.
Logic Resources – pDS:
* Q0: 4 PT. Q1-Qn-1: 5 PT.CAO: 2 PT.CLK: 1 PT per GLB if Product Term Clock is used. CD: 1PT per GLB.
** (CAO is a 2-level output).
Macro Port Definition:
CBUD1 (Q0,CAO,D0,CAI,CLK,PS,LD,EN,DNUP,CD,CS);CBUD2 (Q0,Q1,CAO,D0,D1,CAI,CLK,PS,LD,EN,DNUP,CD,CS);CBUD4 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,PS,LD,EN,DNUP,CD,CS);
CBUD4_1 ([Q0..Q2],[D0..D2],CAI,CLK,PS,LD,EN,DNUP,CD,CS);CBUD4_2 (Q3,CAO,[Q0..Q2],D3,CAI,CLK,PS,LD,EN,DNUP,CD,CS);
CBUD8 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,PS,LD,EN,DNUP,CD,CS);CBUD8_1 ([Q0..Q2],[D0..D2],CAI,CLK,PS,LD,EN,DNUP,CD,CS);CBUD8_2 [Q3..Q5],[Q0..Q2],[D3..D5],CAI,CLK,PS,LD,EN,DNUP,CD,CS);CBUD8_3 (Q6,Q7,CAO,[Q0..Q5],D6,D7,CAI,CLK,PS,LD,EN,DNUP,CD,CS);
Counting Ranges:
CBUD1: 0↔1. CBUD2: 0↔3. CBUD4: 0↔15. CBUD8: 0↔255.
Macro PT GLB Output Level
CBUD1 * .5 2 1**CBUD2 * .75 3 1**CBUD4 */out 1.25 5 1**CBUD8 */out 2.5 9 1**
CBUD1 CBUD2
CBUD4 CBUD8
DN/UP
CSCD
D0
LD
CAI
EN
CAO
Q0
PS
DN/UP
PS
Q0
CAO
Q1
EN
CAI
LD
D1
D0
CD CS
DN/UP
PS
Q0
CAO
Q1
Q2
Q3
EN
CAI
LD
D3
D2
D1
D0
CD CS DN/UP
PS
CSCD
D0
D1
D2
D3
D4
D5
D6
LD
D7
CAI
EN
Q7
Q6
Q5
Q4
Q3
Q2
Q1
CAO
Q0
Macro Library Reference Manual 202
Truth Table:
The truth table is the same for all CBUDs.
* CBUD1: CAO = CAI⋅EN⋅(DNUP⋅D0+DNUP⋅D0)CBUD2: CAO = CAI⋅EN⋅(DNUP⋅D0⋅D1+DNUP⋅D0⋅D1)CBUD4: CAO = CAI⋅EN⋅(DNUP⋅D0⋅D1⋅D2⋅D3+DNUP⋅D0⋅D1⋅D2⋅D3)CBUD8: CAO = CAI⋅EN⋅(DNUP⋅D0⋅D1⋅D2⋅D3⋅D4⋅D5⋅D6⋅D7+DNUP⋅D0⋅D1⋅D2⋅D3⋅D4⋅D5⋅D6⋅D7)
** CAO = 1 after terminal count, when CAI = 1 and EN = 1.CAI⋅EN = shift registers: serial input; counters: CAcade In, enable for multiplexors and counters, d = anypattern of 1s and 0s on an input or set of inputs, Q = output of flip-flop or latch, ↑ = rising clock edge.
Input Output
CD PS CS LD D EN CAI DNUP CLK Q CAO
1 x x x x x x x x 0 CAI⋅EN⋅DNUP0 1 x x x x x x ↑ 1 CAI⋅EN⋅DNUP0 0 1 x x x x x ↑ 0 CAI⋅EN⋅DNUP0 0 0 1 d x x x ↑ d *0 0 0 0 x 0 x x x Q 00 0 0 0 x x 0 x ↑ Q 00 0 0 0 x 1 1 0 ↑ count up **0 0 0 0 x 1 1 1 ↑ count down **
Macro Library Reference Manual 203
Q0LX2
CD
QD
FD21CLK
CD
CAOUP
CS
EN
CAI
D0
LD
PS
DNUP
CBUD1
Macro Library Reference Manual 204
QI0
QI0
QI1
QI0
QI[0:1]
QI0
QI1
QI1
QI0
QI1
QI1
QI0
QI[0:1]
QI0
QI0
QI1
Q0
Q1
CAO
LD
D0
PS
CAI
D1
CS
CLK
CD
QD
FD21
CD
QD
FD21
CD
DNUP
EN
UP
LX2
LX2
CBUD2
Macro Library Reference Manual 205
Q3
Q2
Q1
Q0
QI1
QI2
QI3
QI0
QI1
QI0
QI1
QI0
QI[0:3]
QI0
QI3
QI2
QI1
QI0
UP
CAO
QI[0:3]
QI0
QI0
QI1
QI0
QI1
QI2
QI3
LX2
LX2
DNUP
CS
CD
CD
QD
FD21
CD
QD
FD21
LD
D0
D1
PS
CAI
EN
CLK
CBUD4.1
Macro Library Reference Manual 206
QI[0:3]
QI2
QI2
QI1
QI3
QI0
QI1
QI2
QI0
QI3
LD
CD
CLK
CS
QI[0:3]
QI2
QI3
QI2
QI0
QI1
QI0
QI1
D3
D2
CD
QD
FD21
CD
QD
FD21
LX2
LX2
EN
CAI
PS
DNUP
UP
CBUD4.2
Macro Library Reference Manual 207
QI1
QI0
QI[0:7]
QI0
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
QI0
QI1
QI0
QI2
QI3
QI5
QI6
QI7
QI4
QI5
QI6
QI7
QI3
QI2
QI1
QI0QI1
QI4
QI[0:7]
QI0
QI1
QI0
LX2
LX2
DNUP
CS
CAO
CD
CD
QD
FD21
CD
QD
FD21
LD
D0
D1
PS
CAI
EN
CLK
UP
CBUD8.1
Macro Library Reference Manual 208
QI[0:7]
QI2
QI2
QI1
QI3
QI0
QI1
QI2
QI0
QI3
DNUP
LX2
LX2
CD
CLK
CS
D3
D2
CD
QD
FD21
CD
QD
FD21
EN
CAI
PS
LD
QI[0:7]
QI2
QI3
QI2
QI0
QI1
QI0
QI1
UP
CBUD8.2
Macro Library Reference Manual 209
DNUP
CS
UP
D5
PS
EN
CAI
D4
LD
LX2
LX2
CLK
CD
QI[0:7]
QI5
QI4
QI4
QI4
QI3
QI2
QI1
QI0
QI5
QI3
QI2
QI1
QI0
CD
QD
FD21
CD
QD
FD21
QI[0:7]
QI5
QI4
QI4
QI3
QI1
QI0
QI3
QI2
QI1
QI0
QI2
CBUD8.3
Macro Library Reference Manual 210
QI7
QI6
QI0
QI1
QI2
QI3
QI4
QI5
QI7
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI6
QI[0:7]
LD
EN
CAI
PS
DNUP
UP
QI7
QI2
QI3
QI5
QI0
QI1
QI2
QI3
QI5
QI6
QI4
QI4
QI0
QI1
QI6
QI[0:7]
CD
QD
FD21
CD
QD
FD21
CD
CLK
LX2
LX2
CS
D7
D6
CBUD8.4
Macro Library Reference Manual 211
CDD14 and CDD18
Function: 4- and 8-bit decade down counters with asynchronousclear, enable, and parallel data load.
Availability: CDD14 and CDD18 are for pDS, ispDS, andispDS+.
Type: Hard
Logic Resources – pDS:
* CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.Q0: 5 PT Q1: 6 PT Q2: 5 PT Q3: 5 PT
** CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.Q0: 5 PT Q1: 6 PT Q2: 5 PT Q3: 5 PTQ4: 6 PT Q5: 6 PT Q6: 5 PT Q7: 5 PT
Macro Port Definition:
CDD14 ([Q0..Q3],[D0..D3],CLK,LD,EN,CD);CDD14_1 ([Q0..Q2],[D0..D2],Q3,CLK,LD,EN,CD);CDD14_2 (Q3,D3,[Q0..Q2],CLK,LD,EN,CD);
CDD18 ([Q0..Q7],[D0..D7],CLK,LD,EN,CD);CDD18_1 ([Q0..Q2],[D0..D2],Q3,CLK,LD,EN,CD);CDD18_2 ([Q3..Q5],[D3..D5],[Q0..Q2],Q6,Q7,CLK,LD,EN,CD);CDD18_3 (Q6,Q7,D6,D7,[Q0..Q5],CLK,LD,EN,CD);
Counting Ranges:
CDD14: 9-0. CDD18: 99-0.
Macro PT GLB Output Level
CDD14 * 1.5 4 1CDD18 ** 2.75 8 1
CDD14
CDD18
LD
EN
D3 Q3
D2 Q2
D1 Q1
D0 Q0
CD
Q7D7
LD
EN
D6 Q6
D5 Q5
D4 Q4
D3 Q3
D2 Q2
D1 Q1
D0 Q0
CD
Macro Library Reference Manual 212
Truth Table:
The truth table is the same for both CDD1s.
Valid states for each 4-bit digit are 0-9.Loading higher hexadecimal input values (A-F) clears that decimal output digit on the next clock pulse.d = any pattern of 1s and 0s on an input or set of inputs,Q = output of flip-flop or latch, x = don’t care, ↑ = rising clock edge.
Input Output
CD LD D EN CLK Q
1 x x x x 00 1 d x ↑ d0 0 x 0 x Q0 0 x 1 ↑ count down
Macro Library Reference Manual 213
QI3
QI2
QI1
QI0
QI3
QI1
QI0
QI3
QI0
QI1
QI3
QI2
QI3
QI2
QI1
QI3
QI2
QI3
QI3
QI2
QI1
QI3
QI3
QI2
QI1
QI0QI[0:3]
QI2
CD
QD
FD21
Q3
Q2
Q1
Q0
QI[0:3]
QI1
QI0
QI0
QI3
QI0
QI2
QI0
QI2
QI1
QI3
QI1
QI0
QI1
QI0
QI2
QI2
QI1
QI3
QI0
LX2
LX2
LX2
LX2
CLK
D0
LD
LOAD3
CD
QD
FD21
LOAD1
LOAD0
CD
QD
FD21
HOLD0
HOLD2
HOLD3
HOLD1
CD
QD
FD21
LOAD2
EN
D1
D2
D3
CD
CDD14
Macro Library Reference Manual 214
HOLD3
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
QI2
QI3
QI4
QI5
QI6
QI3
QI1
QI0
QI3
QI0
QI1
QI3
QI2
QI3
QI2
QI1
QI3
QI2
QI3
QI3
QI2
QI1
QI3
QI3
QI2
QI1
QI0QI[0:7]
QI2
QI1
QI0
QI7
QI0
QI3
QI1
QI2
QI2
QI0
QI1
QI0
QI1
QI3
QI1
QI2
QI0
QI2
QI0
QI3
QI0
QI0
QI1
QI[0:7]
LX2
LX2
LX2
LX2
CD
D3
D2
D1
EN
LOAD2
CD
QD
FD21
HOLD1
HOLD2
HOLD0
CD
QD
FD21
LOAD0
LOAD1
CD
QD
FD21
CD
QD
FD21
LOAD3
LD
D0
CLK
CDD18.1
Macro Library Reference Manual 215
QI[0:7]
QI5
QI6
QI2
QI2
QI3
QI2
QI6
QI5
QI3
QI1
QI0
QI4
QI1
QI0
QI7
QI4
QI3
QI1
QI0
QI0
QI1
QI2
QI3
QI4
QI7
QI3
QI2
QI1
QI0
QI4
LX2
LX2
CLK
CD
EN
LD
QI[0:7]
QI7
QI4
QI7
QI6
QI4
QI7
QI5
QI4
QI5
QI7
QI5
QI5
QI6
QI4
QI5
CD
QD
FD21
HOLD4
HOLD5
CD
QD
FD21
D4
D5
CDD18.2
Macro Library Reference Manual 216
QI[0:7]
QI6
QI6
QI7
QI6
QI7
QI7
QI6
QI7
QI7
QI6
QI7
QI5
LX2
LX2
CLK
CD
LD
QI[0:7]
QI5
QI4
QI3
QI1
QI0
QI2
QI1
QI3
QI2
QI0
QI6
QI7
QI4
QI5
QI5
QI4
QI3
QI2
QI1
QI0
QI6
CD
QD
FD21
CD
QD
FD21
HOLD6
HOLD7
D6
D7
EN
CDD18.3
Macro Library Reference Manual 217
CDD24 and CDD28
Function: 4- and 8-bit decade down counters with synchronousclear, enable, and parallel data load.
Availability: CDD24 and CDD28 are for pDS, ispDS, andispDS+.
Type: Hard
Logic Resources – pDS:
* CLK: 1 PT per GLB if Product Term Clock is used.Q0: 5 PT Q1: 6 PT Q2: 5 PT Q3: 5 PT
** CLK: 1 PT per GLB if Product Term Clock is used.Q0: 5 PT Q1: 6 PT Q2: 5 PT Q3: 5 PTQ4: 6 PT Q5: 6 PT Q6: 5 PT Q7: 5 PT
Macro Port Definition:
CDD24 ([Q0..Q3],[D0..D3],CLK,LD,EN,CS);CDD24_1 ([Q0..Q2],[D0..D2],Q3,CLK,LD,EN,CS);CDD24_2 (Q3,D3,[Q0..Q2],CLK,LD,EN,CS);
CDD28 ([Q0..Q7],[D0..D7],CLK,LD,EN,CS);CDD28_1 ([Q0..Q2],[D0..D2],Q3,CLK,LD,EN,CS);CDD28_2 ([Q3..Q5],[D3..D5],[Q0..Q2],Q6,Q7,CLK,LD,EN,CS);CDD28_3 (Q6,Q7,D6,D7,[Q0..Q5],CLK,LD,EN,CS);
Counting Ranges:
CDD24: 9-0. CDD28: 99-0.
Macro PT GLB Output Level
CDD24 * 1.25 4 1CDD28 ** 2.5 8 1
CDD24
CDD28
LD
EN
D3 Q3
D2 Q2
D1 Q1
D0 Q0
CS
Q7D7
LD
EN
D6 Q6
D5 Q5
D4 Q4
D3 Q3
D2 Q2
D1 Q1
D0 Q0
CS
Macro Library Reference Manual 218
Truth Table:
The truth table is the same for both CDD2s.
Valid states for each 4-bit digit are 0-9.Loading higher hexadecimal input values (A-F) clears that decimal output digit on the next clock pulse.d = any pattern of 1s and 0s on an input or set of inputs,Q = output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Input Output
CS LD D EN CLK Q
1 x x x ↑ 00 1 d x ↑ d0 0 x 0 x Q0 0 x 1 ↑ count down
Macro Library Reference Manual 219
Q3
Q2
Q1
Q0
QI1
QI2
QI3
QI0
QI2
QI1
QI0
QI1
QI3
QI2
QI3
QI3
QI2
QI3
QI2
QI3
QI2
QI1
QI3
QI3
QI2
QI1
QI1
QI0
QI3
QI[0:3]
QI3
QI0
QI0
QI3
QI1
QI2
QI0
QI2
QI1
QI0
QI1
QI0
QI3
QI2
QI1
QI0
QI2
QI0
QI3
QI0
QI1
QI[0:3]
LX2
LX2
LX2
LX2
CLK
D2
D0
CS
LD
LOAD3
QD
FD11
LOAD2
QD
FD11
LOAD1
QD
FD11
LOAD0
QD
FD11
HOLD1
HOLD0
HOLD2
HOLD3
EN
D1
D3
CDD24
Macro Library Reference Manual 220
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI0
QI2
QI1
QI0
QI0
QI1
QI3
QI2
QI3
QI3
QI2
QI3
QI2
QI3
QI2
QI1
QI3
QI3
QI2
QI1
QI1
QI0
QI3
QI[0:7]
QI3
QI0
QI3
QI1
QI2
QI0
QI2
QI1
QI0
QI1
QI0
QI3
QI2
QI1
QI0
QI2
QI0
QI3
QI0
QI1
QI[0:7]
LX2
LX2
LX2
LX2
D3
D1
EN
HOLD3
TMLATTICE Semiconductor Corporation
HOLD2
HOLD0
HOLD1
QD
FD11
LOAD0
QD
FD11
LOAD1
QD
FD11
LOAD2
QD
FD11
LOAD3
LD
CS
D0
D2
CLK
CDD28.1
Macro Library Reference Manual 221
QI[0:7]
QI7
QI4
QI3
QI2
QI1
QI0
QI4
QI3
QI2
QI1
QI0
QI4
QI3
QI2
QI1
QI0
QI6
QI5
QI6
QI5
QI3
QI2
QI1
QI0
QI7
QI3
QI2
QI1
QI0
QI4
LX2
LX2
CLK
EN
LD
CS
QI[0:7]
QI6
QI5
QI5
QI7
QI7
QI5
QI5
QI7
QI5
QI4
QI7
QI6
QI4
QI4
QI4
QD
FD11
QD
FD11
HOLD4
HOLD5
D4
D5
CDD28.2
Macro Library Reference Manual 222
QI[0:7]
QI6
QI7
QI7
QI5
QI7
QI7
QI6
QI7
QI6
QI7
QI6
QI6
LX2
LX2
CLK
LD
EN
QI[0:7]
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI3
QI2
QI1
QI0
QI7
QI5
QI4
QI5
QI4
QI3
QI2
QI1
QI0
QI6
QD
FD11
QD
FD11
HOLD7
HOLD6
CS
D6
D7
CDD28.3
Macro Library Reference Manual 223
CDD34 and CDD38
Function: 4- and 8-bit decade down counters with asynchronousclear, enable, parallel data load, CAI, and CAO.
Availability: CDD34 and CDD38 are for pDS, ispDS, andispDS+.
Type: Hard
Logic Resources – pDS:
* CLK: 1 PT per GLB if Product Term Clock is used.CAO: 1 PT CD: 1 PT per GLB.Q0: 5 PT Q1: 6 PTQ2: 5 PT Q3: 5 PT
** CLK: 1 PT per GLB if Product Term Clock is used.CAO: 1 PT CD: 1 PT per GLB.Q0: 5 PT Q1: 6 PT Q2: 5 PTQ3: 5 PT Q4: 6 PT Q5: 6 PTQ6: 5 PT Q7: 5 PT
* (CAO is a 2-level output).
Macro Port Definition:
CDD34 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,LD,EN,CD);CDD34_1 ([Q0..Q2],[D0..D2],Q3,CAI,CLK,LD,EN,CD);CDD34_2 (Q3,CAO,D3,[Q0..Q2],CAI,CLK,LD,EN,CD);
CDD38 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,LD,EN,CD);CDD38_1 ([Q0..Q2],[D0..D2],Q3,CAI,CLK,LD,EN,CD);CDD38_2 ([Q3..Q5],[D3..D5],[Q0..Q2],Q6,Q7,CAI,CLK,LD,EN,CD);CDD38_3 (Q6,Q7,CAO,D6,D7,[Q0..Q5],CAI,CLK,LD,EN,CD);
Counting Ranges:
CDD34: 9-0. 38: 99-0.
Macro PT GLB Output Level
CDD34 * 1.5 5 1***CDD38 ** 2.75 9 1***
CDD34
CDD38
CD
CAI
Q0D0
Q1D1
Q2D2
Q3D3
EN
LD CAO
CD
CAI
Q0D0
Q1D1
Q2D2
Q3D3
Q4D4
Q5D5
Q6D6
EN
LD CAO
D7 Q7
Macro Library Reference Manual 224
Truth Table:
The truth table is the same for both CDD3s.
* CAO = CAI⋅EN⋅terminal count.** CAO = 1 after terminal count when CAI = 1 and EN = 1.
Valid states for each 4-bit digit are 0~9. Loading higher hexadecimal inputvalues (A-F) will clear that decimal output digit.
Input Output
CD LD D EN CAI CLK Q CAO
1 x x x x x 0 CAI⋅EN0 1 d x x ↑ d *0 0 x 0 x x Q 00 0 x x 0 x Q 00 0 x 1 1 ↑ count down **
Macro Library Reference Manual 225
QI0
QI1
QI2
QI3
QI3
QI2
QI1
QI0
QI3
QI0
QI1
QI1
QI3
QI2
QI2
QI2
QI1
QI3
QI3
QI3
QI3
QI2
QI3
QI3
QI2
QI1
QI0QI[0:3]
QI0
QI3
QI1
QI2
QI2
QI0
QI3
QI0
QI2
QI0
QI1
QI1
QI0
QI0
QI1
QI2
QI3
QI0
QI1
QI[0:3]
QI3
QI2
QI1
QI0 CAO
Q3
Q2
Q1
Q0
LX2
LX2
LX2
LX2
CLK
D3
D2
D1
D0
LD
HOLD2
HOLD1
HOLD0
HOLD3
CD
QD
FD21
LOAD0
CD
QD
FD21
LOAD1
CD
QD
FD21
LOAD2
CD
QD
FD21
LOAD3
CAI
EN
CD
CDD34
Macro Library Reference Manual 226
QI3
QI2
QI1
QI[0:7]
QI3
QI2
QI1
QI3
QI0
QI2
QI0
QI1
QI0
QI1
QI0
QI1
QI2
QI0
QI0
QI0
QI6
QI3
QI2
QI1
QI0
QI4
QI5
QI7
QI3
QI2
QI1
QI0
QI5
QI6
QI7
QI[0:7]QI0
QI1
QI2
QI3
QI3
QI2
QI3
QI3
QI3
QI3
QI1
QI2
QI2
QI2
QI3
QI1
QI1
QI0
QI3
QI0
QI1
QI2
QI3
QI4
CAO
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LX2
LX2
LX2
LX2
CD
EN
CAI
LOAD3
CD
QD
FD21
LOAD2
CD
QD
FD21
LOAD1
CD
QD
FD21
LOAD0
CD
QD
FD21
HOLD3
HOLD0
HOLD1
HOLD2
LD
D0
D1
D2
D3
CLK
CDD38.1
Macro Library Reference Manual 227
QI4
QI0
QI1
QI3
QI2
QI7
QI0
QI1
QI2
QI3
QI4
QI6
QI4
QI3
QI2
QI1
QI0
QI7
QI4
QI3
QI2
QI1
QI0
QI6
QI5
QI3
QI2
QI1
QI0
QI5
QI[0:7]
LX2
LX2
CLK
CD
EN
CAI
LD
CD
QD
FD21
HOLD5
HOLD4
CD
QD
FD21
QI4
QI6
QI7
QI5
QI4
QI4
QI4
QI5
QI7
QI5
QI6
QI7
QI5
QI7
QI5
QI[0:7]
D4
D5
CDD38.2
Macro Library Reference Manual 228
QI[0:7]
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI5
QI4
QI2
QI3
QI1
QI0
QI5
QI4
QI3
QI1
QI2
QI0
QI6
LX2
LX2
CLK
CD
EN
CAI
LD
QI[0:7]
QI7
QI7
QI6
QI7
QI5
QI7
QI7
QI6
QI6
QI7
QI6
QI6
CD
QD
FD21
CD
QD
FD21
HOLD6
HOLD7
D6
D7
CDD38.3
Macro Library Reference Manual 229
CDD44 and CDD48
Function: 4- and 8-bit decade down counters with synchronousclear, enable, parallel data load, CAI, and CAO.
Availability: CDD44 and CDD48 are for pDS, ispDS, andispDS+.
Type: Hard
Logic Resources – pDS:
* CLK: 1 PT per GLB if Product Term Clock is used.CAO: 1 PT Q0: 5 PTQ1: 6 PT Q2: 5 PT Q3: 5 PT
** CLK: 1 PT per GLB if Product Term Clock is used.CAO: 1 PT Q0: 5 PTQ1: 6 PT Q2: 5 PT Q3: 5 PTQ4: 6 PT Q5: 6 PT Q6: 5 PT Q7: 5 PT
*** (CAO is a 2-level output).
Macro Port Definition:
CDD44 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,LD,EN,CS);CDD44_1 ([Q0..Q2],[D0..D2],Q3,CAI,CLK,LD,EN,CS);CDD44_2 (Q3,CAO,D3,[Q0..Q2],CAI,CLK,LD,EN,CS);
CDD48 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,LD,EN,CS);CDD48_1 ([Q0..Q2],[D0..D2],Q3,CAI,CLK,LD,EN,CS);CDD48_2 ([Q3..Q5],[D3..D5],[Q0..Q2],Q6,Q7,CAI,CLK,LD,
EN,CS);CDD48_3 (Q6,Q7,CAO,D6,D7,[Q0..Q5],CAI,CLK,LD,EN,CS);
Counting Ranges:
CDD44: 9-0. 48: 99-0.
Macro PT GLB Output Level
CDD44 * 1.5 5 1***CDD48 ** 2.75 9 1***
CDD44
CDD48
CS
CAI
Q0D0
Q1D1
Q2D2
Q3D3
EN
LD CAO
CS
CAI
Q0D0
Q1D1
Q2D2
Q3D3
Q4D4
Q5D5
Q6D6
EN
LD CAO
D7 Q7
Macro Library Reference Manual 230
Truth Table:
Valid states for each 4-bit digit are 0-9. Loading higher hexadecimalinput values (A-F) clears that decimal output digit on the next clockpulse.
* CAO = CAI⋅EN⋅terminal count.** CAO = 1 after terminal count when CAI = 1 and EN = 1.
d = any pattern of 1s and 0s on an input or set of inputs,Q = output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Input Output
CS LD D EN CAI CLK Q CAO
1 x x x x ↑ 0 00 1 d x x ↑ d *0 0 x 0 x x Q 00 0 x x 0 x Q 00 0 x 1 1 ↑ count down **
Macro Library Reference Manual 231
QI5
QI4
QI4
QI4
QI5
QI7
QI5
QI5
QI6
QI7
QI5
QI7
QI4
QI6
QI7
QI[0:7]
QI4
QI0
QI2
QI1
QI3
QI7
QI0
QI1
QI2
QI3
QI5
QI6
QI0
QI1
QI2
QI3
QI4
QI0
QI1
QI2
QI3
QI4
QI7
QI0
QI1
QI2
QI3
QI4
QI6
QI5
QI[0:7]
LX2
LX2
CLK
LD
CS
EN
CAI
QD
FD11
HOLD4
QD
FD11
HOLD5
D4
D5
CDD48.2
Macro Library Reference Manual 232
QI[0:7]
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI0
QI1
QI2
QI3
QI4
QI5
QI0
QI1
QI2
QI3
QI4
QI5
QI6
LX2
LX2
CLK
EN
CAI
LD
CS
QI[0:7]
QI7
QI5
QI7
QI6
QI7
QI7
QI7
QI6
QI6
QI7
QI6
QI6
QD
FD11
HOLD7
QD
FD11
HOLD6
D6
D7
CDD48.3
Macro Library Reference Manual 233
Decade Counters
CDU14 and CDU18
Function: 4- and 8-bit decade up counters with asynchronous clear,enable, and parallel data load.
Availability: CDU14 and CDU18 are for pDS, ispDS, andispDS+.
Type: Hard
Logic Resources – pDS:
* CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.Q0: 5 PT Q1: 4 PT Q2: 4 PT Q3: 6 PT
** CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.Q0: 5 PT Q1: 4 PT Q2: 4 PTQ3: 6 PT Q4: 6 PT Q5: 4 PTQ6: 4 PT Q7: 6 PT
Macro Port Definition:
CDU14 ([Q0..Q3],[D0..D3],CLK,LD,EN,CD);CDU18 ([Q0..Q7],[D0..D7],CLK,LD,EN,CD);
CDU18_1 ([Q0..Q3],[D0..D3],CLK,LD,EN,CD);CDU18_2 ([Q4..Q6],[D4..D6],[Q0..Q3],Q7,CLK,LD,EN,CD);CDU18_3 (Q7,D7,[Q0..Q6],CLK,LD,EN,CD);
Counting Ranges:
CDU14: 0-9. 18: 0-99.
Macro PT GLB Output Level
CDU14 * 1 4 1CDU18 ** 2.25 8 1
CDU14
CDU18
LD
EN
D3 Q3
D2 Q2
D1 Q1
D0 Q0
CD
Q7D7
LD
EN
D6 Q6
D5 Q5
D4 Q4
D3 Q3
D2 Q2
D1 Q1
D0 Q0
CD
Macro Library Reference Manual 234
Truth Table:
The truth table is the same for both CDU1s.
Valid states for each 4-bit digit are 0-9.Loading higher hexadecimal input values (A-F) clears that decimal output digit on the next clock pulse.d = any pattern of 1s and 0s on an input or set of inputs,Q = output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Input Output
CD LD D EN CLK Q
1 x x x x 00 1 d x ↑ d0 0 x 0 x Q0 0 x 1 ↑ count up
Macro Library Reference Manual 235
QI1
QI[1:3]
QI3
QI1
QI2
QI3
QI2
QI3
QI3
QI2
QI1
QI[0:3]QI0
QI0
QI1
QI0
QI0
QI3
QI2
QI3
QI1
QI3
QI2
QI0
QI3
QI0
QI1
QI3
QI1
QI2
QI1
QI3
QI3
QI0
QI3
QI0
QI1
QI2
QI3
QI2
Q0
Q1
Q2
Q3
D3
D2
D1
D0
EN
LD
CD
QD
FD21CLK
CD
HOLD0
HOLD3
HOLD2
HOLD1
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
LX2
LX2
LX2
LX2
CDU14
Macro Library Reference Manual 236
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI0
QI3
QI1
QI3
QI1
QI3
QI0
QI1
QI2
QI1
QI2
QI1
QI0
QI0
QI0
QI2
QI2
QI0
QI3
QI0
QI2
QI3
QI1
QI3
QI3
QI[0:7]
QI3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CD
QD
FD21
QI3
QI3
QI1
QI2
QI3
QI2
QI3
QI1
QI[1:3],QI[5:7]
CD
QD
FD21
CD
QD
FD21
HOLD1
HOLD2
HOLD3
HOLD0
CD
CLK
CD
QD
FD21
LD
EN
D0
D1
D2
D3
LX2
LX2
LX2
LX2
CDU18.1
Macro Library Reference Manual 237
QI2
QI1
QI6
QI5
QI2
QI1
QI7
QI2
QI1
QI7
QI[1:3],QI[5:7]
QI5
D5
D4
HOLD4
HOLD5
CD
QD
FD21
CD
QD
FD21
LD
EN
CLK
CD
LX2
LX2
QI0
QI3
QI0
QI7
QI6
QI4
QI7
QI5
QI4
QI5
QI4
QI3
QI0
QI7
QI5
QI3
QI4QI[0:7]
QI4
QI5
CDU18.2
Macro Library Reference Manual 238
QI1
QI6
QI7
QI2
QI2
QI1
QI7
QI1
QI2
QI[1:3],QI[5:7]
QI7
QI7
QI5
QI6
QI7
QI4
QI3
QI0
QI7
QI6
QI7
QI6
QI7
QI0
QI6
QI5
QI4
QI3
QI6
QI5
QI4
QI3
QI0
QI[0:7]
D6
HOLD6
HOLD7
CD
QD
FD21
CD
QD
FD21
LD
EN
D7
CD
CLK
LX2
LX2
CDU18.3
Macro Library Reference Manual 239
CDU24 and CDU28
Function: 4- and 8-bit decade up counters with synchronous clear,enable, and parallel data load.
Availability: CDU24 and CDU28 are for pDS, ispDS, andispDS+.
Type: Hard
Logic Resources – pDS:
* CLK: 1 PT per GLB if Product Term Clock is used.Q0: 5 PT Q1: 4 PTQ2: 4 PT Q3: 6 PT
** CLK: 1 PT per GLB if Product Term Clock is used.Q0: 5 PT Q1: 4 PTQ2: 4 PT Q3: 6 PT Q4: 6 PTQ5: 4 PT Q6: 4 PT Q7: 6 PT
Macro Port Definition:
CDU24 ([Q0..Q3],[D0..D3],CLK,LD,EN,CS);CDU28 ([Q0..Q7],[D0..D7],CLK,LD,EN,CS);
CDU28_1 ([Q0..Q3],[D0..D3],CLK,LD,EN,CS);CDU28_2 ([Q4..Q6],[D4..D6],[Q0..Q3],Q7,CLK,LD,EN,CS);CDU28_3 (Q7,D7,[Q0..Q6],CLK,LD,EN,CS);
Counting Ranges:
CDU24: 0-9. CDU28: 0-99.
Macro PT GLB Output Level
CDU24 * 1 4 1CDU28 ** 2.25 8 1
CDU24
CDU28
LD
EN
D3 Q3
D2 Q2
D1 Q1
D0 Q0
CS
Q7D7
LD
EN
D6 Q6
D5 Q5
D4 Q4
D3 Q3
D2 Q2
D1 Q1
D0 Q0
CS
Macro Library Reference Manual 240
Truth Table:
The truth table is the same for both CDU2s.
Valid states for each 4-bit digit are 0~9.Loading higher hexadecimal input values (A-F) will clear that decimal output digit.d = any pattern of 1s and 0s on an input or set of inputs, Q = output of flip-flop or latch,x = don’t care, ↑ = rising clock edge.
Input Output
CS LD D EN CLK Q
1 x x x ↑ 00 1 d x ↑ d0 0 x 0 x Q0 0 x 1 ↑ count up
Macro Library Reference Manual 241
Q0
Q1
Q2
Q3
QI2
QI1
QI0
QI0
QI2
QI2
QI1
QI0
QI0
QI0
QI1
QI3
QI1
QI3
QI0
QI3
QI0
QI1
QI2
QI3
QI2
QI3
QI0
QI1
QI2
QI3
QI1
QI3
QI[0:3]
QI3
QI3
QI2
QI1
QI2
QI1
QI3
QI3
QI3
QI[1:3]
QI3
EN
CLK
QD
FD11
HOLD3
HOLD0
HOLD1
HOLD2
QD
FD11
QD
FD11
QD
FD11
CS
LD
D1
D0
D2
D3
LX2
LX2
LX2
LX2
CDU24
Macro Library Reference Manual 242
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI3
QI[0:7]
QI3
QI1
QI3
QI2
QI1
QI0
QI3
QI2
QI3
QI2
QI3
QI0
QI3
QI1
QI3
QI2
QI1
QI0
QI0
QI0
QI0
QI2
QI1
QI0
QI1
QI2
QI1
QI2
QI1
QI3
QI3
QI3
QI[1:3],QI[5:7]
QI3
D3
D2
D0
D1
LD
CS
QD
FD11
QD
FD11
QD
FD11
HOLD2
HOLD1
HOLD0
HOLD3
QD
FD11
CLK
EN
LX2
LX2
LX2
LX2
CDU28.1
Macro Library Reference Manual 243
QI5
QI5
QI0
QI0
QI3
QI4
QI5
QI4
QI7
QI4
QI6
QI7
QI0
QI3
QI3
QI4
QI4
QI[0:7]
QI7
QI5
QI2
QI7
QI1
QI6
QI5
QI2
QI1
QI7
QI2
QI1
QI[1:3],QI[5:7]
QI5
CLK
LD
CS
EN
QD
FD11
QD
FD11
HOLD5
HOLD4
D4
D5
LX2
LX2
CDU28.2
Macro Library Reference Manual 244
QI7
QI7
QI[0:7]
QI6
QI7
QI4
QI3
QI0
QI6
QI5
QI4
QI3
QI0
QI7
QI6
QI0
QI3
QI4
QI5
QI6
QI7
QI6
QI7
QI5
QI[1:3],QI[5:7]
QI2
QI1
QI2
QI1
QI1
QI2
QI7
QI6
QI7
D6
D7
CS
LD
EN
QD
FD11
HOLD6
QD
FD11
HOLD7
CLK
LX2
LX2
CDU28.3
Macro Library Reference Manual 245
CDU34 and CDU38
Function: 4- and 8-bit decade up counters with asynchronous clear,enable, parallel data load, CAI, and CAO.
Availability: CDU34 and CDU38 are for pDS, ispDS, andispDS+.
Type: Hard
Logic Resources – pDS:
* CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.Q0: 5 PT Q1: 4 PTQ2: 4 PT Q3: 6 PT CAO: 1 PT
** CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.Q0: 5 PT Q1: 4 PT Q2: 4 PT Q3: 6 PTQ4: 6 PT Q5: 4 PT Q6: 4 PT Q7: 6 PTCAO: 1 PT
*** (CAO is a 2-level output).
Macro Port Definition:
CDU34 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,LD,EN,CD);CDU34_1 ([Q0..Q3],[D0..D3],CAI,CLK,LD,EN,CD);CDU34_2 (CAO,[Q0..Q3],CAI,EN);
CDU38 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,LD,EN,CD);CDU38_1 ([Q0..Q3],[D0..D3],CAI,CLK,LD,EN,CD);CDU38_2 ([Q4..Q6],CAO,[D4..D6],[Q0..Q3],Q7,CAI,CLK,
LD,EN,CD);CDU38_3 (Q7,D7,[Q0..Q6],CAI,CLK,LD,EN,CD);
Counting Ranges:
CDU34: 0-9. CDU38: 0-99.
Macro PT GLB Output Level
CDU34 * 1.25 5 1***CDU38 ** 2.5 9 1***
CDU34
CDU38
CD
CAI
Q0D0
Q1D1
Q2D2
Q3D3
EN
LD CAO
CD
CAI
Q0D0
Q1D1
Q2D2
Q3D3
Q4D4
Q5D5
Q6D6
EN
LD CAO
D7 Q7
Macro Library Reference Manual 246
Truth Table:
Valid states for each 4-bit digit are 0-9. Loading higher hexadecimalinput values (A-F) clears that decimal output digit on the next clockpulse.
* CAO = CAI⋅EN⋅terminal count.** CAO = 1 after terminal count (9 or 99) when CAI = 1 and EN = 1.
d = any pattern of 1s and 0s on an input or set of inputs,Q = output of flip-flop or latch, x = don’t care, ↑ = rising clock edge.
Input Output
CD LD D EN CAI CLK Q CAO
1 x x x x x 0 00 1 d x x ↑ d *0 0 x 0 x x Q 00 0 x x 0 x Q 00 0 x 1 1 ↑ count up **
Macro Library Reference Manual 247
QI3
QI2
QI1
QI0
QI2
QI0
QI2
QI0
QI1
QI0
QI3
QI1
QI3
QI2
QI3
QI1
QI0
QI3
QI1
QI2
QI3
QI0
QI3
QI0
QI1
QI2
QI0
QI3
QI[0:3]
QI0
QI1
QI3
QI3
QI1
QI2
QI2
QI3
QI3
QI1
QI3
QI[1:3]
QI1
QI3
QI2
Q0
Q1
Q2
Q3
CD
CAI
CAO
HOLD0
CD
QD
FD21
HOLD1
HOLD2
HOLD3
CD
QD
FD21
CD
QD
FD21
CD
QD
FD21
EN
LD
D1
D0
D3
D2
CLK
LX2
LX2
LX2
LX2
CDU34
Macro Library Reference Manual 248
QI7
QI6
QI5
QI3
QI2
QI1
QI0
QI4
QI2
QI[0:7]QI0
QI1
QI0
QI3
QI1
QI3
QI2
QI3
QI2
QI1
QI0
QI3
QI1
QI2
QI3
QI0
QI3
QI0
QI1
QI2
QI0
QI3
QI0
QI1
QI3
QI7
QI0
QI3
QI4
QI5
QI1
QI2
QI[1:3],QI[5:7]
QI3
QI3
QI1
QI2
QI3
QI1
QI2
QI3
QI6
CD
QD
FD21
Q4
Q3
Q2
Q1
Q0
Q5
Q6
Q7
CAO
CLK
D2
D3
D0
D1
LD
EN
CD
QD
FD21
CD
QD
FD21
HOLD3
HOLD2
HOLD1
CD
QD
FD21
HOLD0
CAI
CD
LX2
LX2
LX2
LX2
CDU38.1
Macro Library Reference Manual 249
QI7
QI1
QI2
QI7
QI1
QI2
QI5
QI6
QI1
QI2
QI[1:3],QI[5:7]
QI5
QI4
QI4
QI5
QI[0:7]
QI3
QI0
QI3
QI0
QI7
QI6
QI4
QI7
QI5
QI4
QI5
QI4
QI3
QI0
QI7
QI5
D5
D4
CLK
CD
QD
FD21
CD
QD
FD21
HOLD5
HOLD4
CD
LD
CAI
EN
LX2
LX2
CDU38.2
Macro Library Reference Manual 250
QI6
QI1
QI2
QI7
QI7
QI1
QI2
QI1
QI2
QI[1:3],QI[5:7]
QI6
QI3
QI4
QI6
QI0
QI3
QI4
QI5
QI7
QI7
QI4
QI0
QI6
QI5
QI3
QI0
QI6
QI7
QI7
QI6
QI7
QI5
QI7
QI[0:7]
CAI
HOLD6
HOLD7
CD
QD
FD21
CD
QD
FD21
EN
LD
D7
D6
CD
CLK
LX2
LX2
CDU38.3
Macro Library Reference Manual 251
CDU44 and CDU48
Function: 4- and 8-bit decade up counters with synchronous clear,enable, parallel data load, CAI, and CAO.
Availability: CDU44 and CDU48 are for pDS, ispDS, andispDS+.
Type: Hard
Logic Resources – pDS:
* CLK: 1 PT per GLB if Product Term Clock is used.CAO: 1 PTQ0: 5 PT Q1: 4 PTQ2: 4 PT Q3: 6 PT
** CLK: 1 PT per GLB if Product Term Clock is used.CAO: 1 PTQ0: 5 PT Q1: 4 PTQ2: 4 PT Q3: 6 PT Q4: 6 PTQ5: 4 PT Q6: 4 PT Q7: 6 PT
*** (CAO is a 2-level output).
Macro Port Definition:
CDU44 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,LD,EN,CS);CDU44_1 ([Q0..Q3],[D0..D3],CAI,CLK,LD,EN,CS);CDU44_2 (CAO,[Q0..Q3],CAI,EN);
CDU48 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,LD,EN,CS);CDU48_1 ([Q0..Q3],[D0..D3],CAI,CLK,LD,EN,CS);CDU48_2 ([Q4..Q6],CAO,[D4..D6],[Q0..Q3],Q7,CAI,CLK,
LD,EN,CS);CDU48_3 (Q7,D7,[Q0..Q6],CAI,CLK,LD,EN,CS);
Counting Ranges:
CDU44: 0-9. CDU48: 0-99.
Macro PT GLB Output Level
CDU44 * 1.25 5 1***CDU48 ** 2.5 9 1***
CDU44
CDU48
CS
CAI
Q0D0
Q1D1
Q2D2
Q3D3
EN
LD CAO
CS
CAI
Q0D0
Q1D1
Q2D2
Q3D3
Q4D4
Q5D5
Q6D6
EN
LD CAO
D7 Q7
Macro Library Reference Manual 252
Truth Table:
Valid states for each 4-bit digit are 0-9. Loading higher hexadecimalinput values (A-F) clears that decimal output digit on the next clockpulse.
* CAO = CAI⋅EN⋅terminal count.** CAO = 1 after terminal count (9 or 99) when CAI=1 and EN=1
d = any pattern of 1s and 0s on an input or set of inputs,Q = output of flip-flop or latch, x = don’t care, ↑ = rising clock edge.
Input Output
CS LD D EN CAI CLK Q CAO
1 x x x x ↑ 0 00 1 d x x ↑ d *0 0 x 0 x x Q 00 0 x x 0 x Q 00 0 x 1 1 ↑ count up **
Macro Library Reference Manual 253
QI3
QI1
QI0
QI[0:3]
QI3
QI0
QI1
QI0
QI3
QI1
QI2
QI1
QI0
QI3
QI2
QI1
QI3
QI0
QI3
QI3
QI2
QI3
QI0
QI1
QI2
QI0
QI1
QI2
QI3
QI0
QI0
QI2
QI3
QI1
QI1
QI3
QI2
QI1
QI3
QI3
QI[1:3]
QI2
QI2
QI3
Q3
Q2
Q1
Q0
CLK
CAO
D3
D2
D1
CLK
QD
FD11
QD
FD11
QD
FD11
HOLD0
HOLD3
QD
FD11
HOLD1
HOLD2
LD
CS
D0
EN
CAI
LX2
LX2
LX2
LX2
CDU44
Macro Library Reference Manual 254
QI3
QI2
QI[1:3],QI[5:7]
QI3
QI3
QI1
QI2
QI3
QI1
QI6
QI5
QI2
QI1
QI4
QI7
QI6
QI5
QI4
QI0
QI0
QI[0:7]
QI3
QI0
QI1
QI0
QI3
QI1
QI2
QI1
QI0
QI3
QI2
QI1
QI3
QI0
QI3
QI3
QI2
QI3
QI0
QI1
QI2
QI0
QI1
QI2
QI3
QI1
QI2
QI3
QI7
QI3
QI0
CAO
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CAI
EN
D0
CS
LD
HOLD2
HOLD1
QD
FD11
HOLD3
HOLD0
QD
FD11
QD
FD11
QD
FD11
CLK
D1
D2
D3
CLK
LX2
LX2
LX2
LX2
CDU48.1
Macro Library Reference Manual 255
QI4
QI3
QI0
QI5
QI7
QI0
QI3
QI4
QI5
QI4
QI5
QI7
QI4
QI6
QI7
QI0
QI3
QI4QI[0:7]
QI5
D5
D4
HOLD4
HOLD5
QD
FD11
QD
FD11
CLK
CS
LD
CAI
EN
LX2
LX2
QI7
QI2
QI1
QI1
QI2
QI7
QI1
QI2
QI5
QI6
QI[1:3],QI[5:7]
QI5
CDU48.2
Macro Library Reference Manual 256
QI6
QI[1:3],QI[5:7]
QI1
QI7
QI2
QI1
QI2
QI1
QI7
QI2
QI3
QI[0:7]
QI7
QI6
QI7
QI5
QI7
QI6
QI7
QI4
QI3
QI0
QI6
QI5
QI4
QI3
QI0
QI7
QI7
QI6
QI5
QI4
QI0
QI6
CLK
LD
EN
CAI
CS
QD
FD11
QD
FD11
HOLD7
HOLD6
D6
D7
LX2
LX2
CDU48.3
Macro Library Reference Manual 257
CDUD4 and CDUD8
Function: 4- and 8-bit decade up/down counters with asynchronousclear, synchronous clear, enable, and parallel data load.
Availability: CDUD4 and CDUD8 are for pDS, ispDS, andispDS+.
Type: Hard
Logic Resources – pDS:
* CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.Q0: 5 PT Q1: 7 PTQ2: 6 PT Q3: 7 PT
** CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.Q0: 5 PT Q1: 7 PT Q2: 6 PTQ3: 7 PT Q4: 8 PT Q5: 7 PTQ6: 6 PT Q7: 7 PT
Macro Port Definition:
CDUD4 ([Q0..Q3],[D0..D3],CLK,LD,EN,DNUP,CD,CS);CDUD4_1 ([Q0..Q2],[D0..D2],Q3,CLK,LD,EN,DNUP,CD,CS);CDUD4_2 (Q3,D3,[Q0..Q2],CLK,LD,EN,DNUP,CD,CS);
CDUD8 ([Q0..Q7],[D0..D7],CLK,LD,EN,DNUP,CD,CS);CDUD8_1 ([Q0..Q2],[D0..D2],Q3,CLK,LD,EN,DNUP,CD,CS);CDUD8_2 (Q3,Q4,D3,D4,[Q0..Q2],[Q5..Q7],CLK,LD,EN,DNUP,CD,CS);CDUD8_3 (Q5,Q6,D5,D6,[Q0..Q4],Q7,CLK,LD,EN,DNUP,CD,CS);CDUD8_4 (Q7,D7,[Q0..Q6],CLK,LD,EN,DNUP,CD,CS);
Counting Ranges:
CDUD4: 0↔9. 8: 0↔99.
Macro PT GLB Output Level
CDUD4 * 1.5 4 1CDUD8 ** 3.25 8 1
CDUD4 CDUD8
DN/UP
Q0D0
Q1D1
Q2D2
Q3D3
CS
EN
LD
CD DN/UP
CD
Q7D7
LD
EN
CS
D6 Q6
D5 Q5
D4 Q4
D3 Q3
D2 Q2
D1 Q1
D0 Q0
Macro Library Reference Manual 258
Truth Table:
Valid states for each 4-bit digit are 0-9. Loading higher hexadecimalinput values (A-F) clears that decimal output digit on the next clockpulse.
d = any pattern of 1s and 0s on an input or set of inputs,Q = output of flip-flop or latch, x = don’t care, ↑ = rising clock edge.
Input Output
CD CS LD D EN DNUP CLK Q
1 x x x x x x 00 1 x x x x ↑ 00 0 1 d x x ↑ d0 0 0 x 0 x x Q0 0 0 x 1 0 ↑ count up0 0 0 x 1 1 ↑ count down
Macro Library Reference Manual 259
QI0
QI1
QI2
QI3
QI[0:3]
QI3
QI1
QI0
QI1
QI3
QI3
QI1
QI2
QI0
QI0
QI0
QI1
Q0
Q1
Q2
Q3
QI1
QI[0:3]
QI0
QI3
QI0
QI3
QI2
QI0
QI2
QI1
QI3
QI0
LX2
LX2
CD
LOAD1CD
QD
FD21
LOAD0CD
QD
FD21
HOLD0
HOLD1
CS
LD
EN
DNUP
D0
D1
CLK
CDUD4.1
Macro Library Reference Manual 260
QI[0:3]
QI1
QI0
QI3
QI0
QI1
QI0
QI1
QI2
QI3
QI2
QI2
QI[0:3]
QI0
QI3
QI2
QI3
QI3
QI2
QI3
QI0
QI2
QI1
QI2
QI1
QI0
QI3
QI2
QI3
QI1
QI3LX2
LX2
D3
D2
HOLD3
HOLD2
CD
QD
FD21
CLK
LOAD2
CD
QD
FD21
CD
CS
LD
DNUP
EN
CDUD4.2
Macro Library Reference Manual 261
QI1
QI2
QI3
QI4
QI3
QI1
QI0
QI1
QI3
QI3
QI1
QI2
QI0
QI0QI[0:7]
QI0
QI1
QI0
QI7
QI6
QI5
QI1
QI0
QI3
QI1
QI2
QI0
QI2
QI3
QI0
QI3
QI0
QI[0:7]
LX2
LX2
CLK
D1
D0
DNUP
EN
LD
CS
HOLD1
HOLD0
CD
QD
FD21LOAD0
CD
QD
FD21LOAD1
CD
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CDUD8.1
Macro Library Reference Manual 262
QI2
QI3
QI1
QI3
QI2
QI3
QI0
QI1
QI2
QI1
QI2
QI0
QI3
QI2
QI3
QI3
QI2
QI3
QI0
QI[0:7]
LX2
LX2
CD
CLK
EN
DNUP
LD
CS
CD
QD
FD21LOAD2
CD
QD
FD21
HOLD2
HOLD3
QI2
QI3
QI2
QI1
QI0
QI1
QI0
QI3
QI0
QI1
QI[0:7]
D2
D3
CDUD8.2
Macro Library Reference Manual 263
QI[0:7]
QI2
QI3
QI5
QI6
QI0
QI1
QI2
QI3
QI7
QI1
QI2
QI5
QI6
QI0
QI1
QI7
QI2
QI1
QI4
LX2
CD
CLK
EN
DNUP
LD
CS
QI[0:7]
QI4
QI5
QI7
QI4
QI6
QI7
QI3
QI0
QI3
QI0
QI4
QI4
LOAD4CD
QD
FD21
HOLD4
D4
CDUD8.3
Macro Library Reference Manual 264
QI[0:7]
QI5
QI7
QI7
QI6
QI5
QI5
QI4
QI3
QI0
QI5
LX2
QI5
QI[0:7]
QI1
QI2
QI3
QI4
QI6
QI0
QI7
QI4
QI3
QI1
QI2
QI0
QI7
QI2
QI1
QI4
QI3
QI2
QI1
QI0
CD
CLK
EN
DNUP
LD
LOAD5CD
QD
FD21
HOLD5
CS
D5
CDUD8.4
Macro Library Reference Manual 265
QI[0:7]
QI6
QI7
QI6
QI7
QI0
QI3
QI4
QI5
QI6
QI6LX2
QI[0:7]
QI2
QI3
QI4
QI5
QI0
QI1
QI2
QI3
QI4
QI5
QI1
QI2
QI0
QI1
QI7
QI6
EN
DNUP
LD
LOAD6
CD
CLK
CD
QD
FD21
CS
HOLD6
D6
CDUD8.5
Macro Library Reference Manual 266
QI[0:7]
QI7
QI7
QI4
QI3
QI0
QI7
QI6
QI5
QI6
QI4
QI5
QI3
QI0
QI7
QI7
LX2
QI[0:7]
QI0
QI2
QI3
QI4
QI5
QI6
QI2
QI1
QI1
QI1
QI2
QI7
LD
EN
DNUP
CS
LOAD7
HOLD7
CLK
CD
CD
QD
FD21
D7
CDUD8.6
Macro Library Reference Manual 267
CDUD4c and CDUD8c
Function: 4- and 8-bit decade up/down counters with asynchronousclear, synchronous clear, enable, parallel data load, CAI, and CAO.
Availability: CDUD4c and CDUD8c are for pDS, ispDS, andispDS+.
Type: Hard
Logic Resources – pDS:
* CLK: 1 PT per GLB if Product Term Clock is used.CAO: 2 PT CD: 1 PT per GLB.Q0: 5 PT Q1: 7 PTQ2: 6 PT Q3: 7 PT
** CLK: 1 PT per GLB if Product Term Clock is used.CAO: 2 PT CD: 1 PT per GLB.Q0: 5 PT Q1: 7 PT Q2: 6 PTQ3: 7 PT Q4: 8 PT Q5: 7 PTQ6: 6 PT Q7: 7 PT
*** (CAO is a 2-level output).
Macro Port Definition:
CDUD4c ([Q0..Q3],CAO,[D0..D3],CAI,CLK,LD,EN,DNUP,CD,CS);CDUD4c_1 ([Q0..Q2],[D0..D2],Q3,CAI,CLK,LD,EN,DNUP,CD,CS);CDUD4c_2 (Q3,CAO,D3,[Q0..Q2],CAI,CLK,LD,EN,DNUP,CD,CS);
CDUD8c ([Q0..Q7],CAO,[D0..D7],CAI,CLK,LD,EN,DNUP,CD,CS);CDUD8c_1 ([Q0..Q2],[D0..D2],Q3,CAI,CLK,LD,EN,DNUP,CD,CS);CDUD8c_2 (Q3,Q4,CAO,D3,D4,[Q0..Q2],[Q5..Q7],CAI,CLK,LD,
EN,DNUP,CD,CS);CDUD8c_3 (Q5,Q6,D5,D6,[Q0..Q4],Q7,CAI,CLK,LD,EN,DNUP,CD,CS);CDUD8c_4 (Q7,D7,[Q0..Q6],CAI,CLK,LD,EN,DNUP,CD,CS);
Counting Ranges:
CDUD4c: 0↔9. CDUD8c: 0↔99.
Macro PT GLB Output Level
CDUD4c * 1.5 5 1***CDUD8c ** 3.25 9 1***
CDUD4c CDUD8c
DN/UP
CAI
Q0D0
Q1D1
Q2D2
Q3D3
CS
EN
LD CAO
CD DN/UP
CD
Q7D7
CAOLD
EN
CS
D6 Q6
D5 Q5
D4 Q4
D3 Q3
D2 Q2
D1 Q1
D0 Q0
CAI
Macro Library Reference Manual 268
Truth Table:
Valid states for each 4-bit digit are 0-9. Loading higher hexadecimalinput values (A-F) clears that decimal output digit on the next clockpulse.
* CAO = CAI⋅EN⋅DNUP** CDUD4c: CAO = CAI⋅EN⋅DNUP⋅D0⋅D1⋅D2⋅D3+DNUP⋅9
CDUD8c: CAO = CAI⋅EN⋅DNUP⋅D0⋅D1⋅D2⋅D3⋅D4⋅D5⋅D6⋅D7+DNUP⋅99*** CAO = 1 after terminal count (9 or 99) when CAI = 1 and EN = 1.
terminal count = 0 when DNUP = 1 (count down).terminal count = 9 or 99 when DNUP=0 (count up).d = any pattern of 1s and 0s on an input or set of inputs, Q = output offlip-flop or latch, x = don’t care, ↑ = rising clock edge.
Input Output
CD CS LD D EN CAI DNUP CLK Q CAO
1 0 x x x x x x 0 *0 1 x x x x x ↑ 0 *0 0 1 d x x x ↑ d **0 0 0 x 0 x x x Q 00 0 0 x x 0 x x Q 00 0 0 x 1 1 0 ↑ count up 00 0 0 x 1 1 1 ↑ count down ***
Macro Library Reference Manual 269
Q3
Q2
Q0
Q1
QI0
QI2
QI3
QI1
QI0
QI1
QI0
QI1
QI0
QI3
QI0
QI3
QI1
QI3
QI2
QI1
QI[0:3]
QI0
QI3
QI0
QI1
QI2
QI3
QI2
QI1
QI0
QI3
QI1
QI2
QI0
QI0
QI3
QI2
QI0
QI3
QI1
QI[0:3]
CAO
LX2
LX2
CLK
EN
CS
LD
LOAD0CD
QD
FD21
CD
QD
FD21
HOLD0
HOLD1
LOAD1
DNUP
D0
CAI
D1
CD
CDUD4c.1
Macro Library Reference Manual 270
QI[0:3]
QI3
QI0
QI1
QI0
QI1
QI3
QI2
QI0
QI1
QI2
LX2
LX2
CLK
CD
D2
EN
CAI
DNUP
LD
QI[0:3]
QI0
QI2
QI1
QI3
QI2
QI2
QI3
QI3
QI3
QI2
QI0
QI1
QI2
QI3
QI2
QI3
QI0
CD
QD
FD21
CS HOLD2
HOLD3
CD
QD
FD21
LOAD2
D3
CDUD4c.2
Macro Library Reference Manual 271
Q7QI7
QI2
QI0
QI1
QI6
QI5
QI4
QI3
QI7
QI4
QI0
QI3
QI[0:7]
QI1
QI2
QI3
QI1
QI3
QI0
QI3
QI0
QI1
QI0
QI1
QI0
QI6
QI4
QI5
QI2
QI1
QI[0:7]
QI1
QI3
QI0
QI2
QI3
QI0
QI0
QI2
QI1
QI3
QI0
QI5
QI6
QI0
QI1
QI2
QI3
QI7
CAO
LX2
LX2
CD
D1
CAI
D0
DNUP
LOAD1
HOLD1
HOLD0
CD
QD
FD21
CD
QD
FD21LOAD0
LD
CS
EN
CLK
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CDUD8c.1
Macro Library Reference Manual 272
QI2
QI1
QI0
QI2
QI3
QI1
QI0
QI1
QI0
QI3
QI[0:7]
LX2
LX2
D3
LOAD2
CD
QD
FD21
HOLD3
HOLD2CS
CD
QD
FD21
QI0
QI3
QI2
QI3
QI2
QI1
QI0
QI2
QI3
QI3
QI3
QI2
QI2
QI3
QI1
QI2
QI0
QI[0:7]
LD
DNUP
CAI
EN
D2
CD
CLK
CDUD8c.2
Macro Library Reference Manual 273
QI6
QI5
QI3
QI2
QI1
QI0
QI7
QI3
QI2
QI1
QI0
QI6
QI5
QI2
QI1
QI1
QI2
QI7
QI4
QI[0:7]
QI7
QI5
QI4
QI7
QI6
QI4
QI3
QI0
QI0
QI3
QI4
QI4
QI[0:7]
LX2CS
LD
EN
CAI
DNUP
HOLD4
LOAD4
CLK
CD
CD
QD
FD21
D4
CDUD8c.3
Macro Library Reference Manual 274
QI[0:7]
QI5
QI6
QI4
QI3
QI2
QI1
QI0
QI7
QI4
QI3
QI2
QI1
QI0
QI7
QI2
QI1
QI0
QI1
QI2
QI4
QI3
LX2
QI[0:7]
QI5
QI7
QI5
QI7
QI6
QI5
QI4
QI3
QI0
QI5
EN
CAI
LD
DNUP
CD
CLK
LOAD5
HOLD5
CD
QD
FD21
CS
D5
CDUD8c.4
Macro Library Reference Manual 275
QI[0:7]
QI6
QI1
QI2
QI7
QI0
QI1
QI2
QI3
QI4
QI5
QI0
QI1
QI2
QI3
QI4
QI5
LX2
EN
CAI
DNUP
LD
CD
CLK
QI[0:7]
QI6
QI0
QI3
QI4
QI5
QI6
QI7
QI6
QI7
QI6
LOAD6
HOLD6
CD
QD
FD21
CS
D6
CDUD8c.5
Macro Library Reference Manual 276
QI[0:7]
QI7
QI2
QI1
QI2
QI1
QI0
QI1
QI2
QI3
QI6
QI4
QI5
LX2
CD
CLK
QI[0:7]
QI7
QI7
QI6
QI5
QI4
QI3
QI0
QI7
QI4
QI3
QI0
QI6
QI7
QI5
QI7
EN
CAI
DNUP
LD
CS
LOAD7CD
QD
FD21
HOLD7
D7
CDUD8c.6
Macro Library Reference Manual 277
Gray Code Counters
CGD14
Function: 4-bit gray code down counter with asynchronous clear,synchronous preset, enable, and parallel data load.
Availability: CGD14 is for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
* CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB. Q0: 7 PTQ1: 6 PT Q2: 6 PT Q3: 6 PT
Macro Port Definition:
CGD14 ([Q0..Q3],[D0..D3],CLK,PS,LD,EN,CD);CGD14_1 (Q0,Q1,D0,D1,Q2,Q3,CLK,PS,LD,EN,CD);CGD14_2 (Q2,Q3,D2,D3,Q0,Q1,CLK,PS,LD,EN,CD);
Gray Code Pattern: Refer to CGU14.
Counting Range: 15-0.
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,Q = output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Macro PT GLB Output Level
CGD14 * 1.5 4 1
Input Output
CD PS LD D EN CLK Q
1 x x x x x 00 1 x x x ↑ 10 0 1 d x ↑ d0 0 0 x 0 ↑ Q0 0 0 x 1 ↑ count down
CD
Q0D0
Q1D1
Q2D2
Q3D3
EN
LD
PS
CGD14
Macro Library Reference Manual 278
QI3
QI2
QI1
QI0
QI1
QI0
QI3
QI0
QI1
QI1
QI3
QI2
QI3
QI2
QI0
QI1
QI[0:3]QI0
QI1
QI2
CD
QD
FD21
QI2
QI3
QI1
QI1
QI2
QI0
QI1
QI[0:3]
QI3
QI3
QI2
QI0
HOLD0
LOAD0
LOAD1
HOLD1
CD
QD
FD21
LD
D0
EN
D1
PS
CD
CLK
Q3
Q2
Q1
Q0
CGD14.1
Macro Library Reference Manual 279
QI[0:3]
QI2
QI0
QI1
QI1
QI0
QI3
QI2
CLK
HOLD3
CD
PS
LD
EN
CD
QD
FD21
CD
QD
FD21
D3
D2
LOAD3
LOAD2
HOLD2
QI[0:3]
QI2
QI3
QI2
QI2
QI2
QI0
QI3
QI3
QI0
QI3
QI1
QI1
QI3
CGD14.2
Macro Library Reference Manual 280
CGD24
Function: 4-bit gray code down counter with synchronous clear,synchronous preset, enable, and parallel data load.
Availability: CGD24 is for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
* CLK: 1 PT per GLB if Product Term Clock is used.Q0: 7 PT Q1: 6 PTQ2: 6 PT Q3: 6 PT
Macro Port Definition:
CGD24 ([Q0..Q3],[D0..D3],CLK,PS,LD,EN,CS);CGD24_1 (Q0,Q1,D0,D1,Q2,Q3,CLK,PS,LD,EN,CS);CGD24_2 (Q2,Q3,D2,D3,Q0,Q1,CLK,PS,LD,EN,CS);
Gray Code Pattern: Refer to CGU14.
Counting Range: 15-0.
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,Q = output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Macro PT GLB Output Level
CGD24 * 1.5 4 1
Input Output
PS CS LD D EN CLK Q
1 x x x x ↑ 10 1 x x x ↑ 00 0 1 d x ↑ d0 0 0 x 0 ↑ Q0 0 0 x 1 ↑ count down
CS
Q0D0
Q1D1
Q2D2
Q3D3
EN
LD
PS
CGD24
Macro Library Reference Manual 281
Q0
Q1
Q2
Q3
QI2
QI1
QI0
QI3
QI0
QI2
QI3
QI2
QI3
QI1
QI1
QI0
QI3
QI0
QI[0:3]
QI1
QI0
QI1
QI1
QI2
QI1
QI1QI0
QI1
QI[0:3]
QI3
QI2
QI3
QI2
QI0
QI3
QI2
QD
FD11
LOAD0LD
D0
EN
HOLD1
D1
LOAD1
PS
QD
FD11
CS
HOLD0
CLK
CGD24.1
Macro Library Reference Manual 282
QI[0:3]
QI0
QI1
QI1
QI0
QI3
QI2
QI2
QD
FD11
HOLD3
LOAD3
LD
D3
EN
QD
FD11
HOLD2
D2
LOAD2
PS
CS
CLK
QI1
QI1
QI3
QI0
QI3
QI3
QI0
QI2
QI2
QI2 QI[0:3]
QI2
QI3
QI3
CGD24.2
Macro Library Reference Manual 283
CGU14
Function: 4-bit gray code up counter with asynchronous clear,synchronous preset, enable, and parallel data load.
Availability: CGU14 is for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
* CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.Q0: 7 PT Q1: 6 PTQ2: 6 PT Q3: 6 PT
Gray Code Pattern:
Note that codes for two successive numbers differ by one bit.
Macro Port Definition:
CGU14 ([Q0..Q3],[D0..D3],CLK,PS,LD,EN,CD);CGU14_1 (Q0,Q1,D0,D1,Q2,Q3,CLK,PS,LD,EN,CD);CGU14_2 (Q2,Q3,D2,D3,Q0,Q1,CLK,PS,LD,EN,CD);
Macro PT GLB Output Level
CGU14 * 1.5 4 1 CD
Q0D0
Q1D1
Q2D2
Q3D3
EN
LD
PS
CGU14
Macro Library Reference Manual 284
Counting Range: 0-15.
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,Q = output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Input Output
CD PS LD D EN CLK Q
1 x x x x x 00 1 x x x ↑ 10 0 1 d x ↑ d0 0 0 x 0 ↑ Q0 0 0 x 1 ↑ count up
Gray Code Pattern
0 0 0 0 0 8 1 1 0 01 0 0 0 1 9 1 1 0 12 0 0 1 1 10 1 1 1 13 0 0 1 0 11 1 1 1 04 0 1 1 0 12 1 0 1 05 0 1 1 1 13 1 0 1 16 0 1 0 1 14 1 0 0 17 0 1 0 0 15 1 0 0 0
Macro Library Reference Manual 285
QI1
QI2
QI3
QI0
QI0
QI2
QI3
QI0
QI1
QI1
QI1
QI3
QI2
QI3
QI1
QI2
QI0
QI1
QI[0:3]QI0
Q0
Q1
Q2
Q3
QI3
QI0
QI2
QI1
QI3
QI1
QI2
QI0
QI1
QI[0:3]
QI3
QI2
HOLD0
LOAD0
LOAD1
HOLD1
CD
QD
FD21
CD
QD
FD21
LD
D0
EN
D1
PS
CD
CLK
CGU14.1
Macro Library Reference Manual 286
QI[0:3]
QI2
QI0
QI1
QI1
QI0
QI3
QI3
CLK
HOLD3
CD
PS
LD
EN
QI[0:3]
QI2
QI3
QI2
QI2
QI2
QI0
QI3
QI2
QI3
QI0
QI3
QI1
QI1
CD
QD
FD21
CD
QD
FD21
D3
D2
LOAD3
LOAD2
HOLD2
CGU14.2
Macro Library Reference Manual 287
CGU24
Function: 4-bit gray code up counter with synchronous clear,synchronous preset, enable, and parallel data load.
Availability: CGU24 is for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
* CLK: 1 PT per GLB if Product Term Clock is used.Q0: 7 PT Q1: 6 PTQ2: 6 PT Q3: 6 PT
Macro Port Definition:
CGU24 ([Q0..Q3],[D0..D3],CLK,PS,LD,EN,CS);CGU24_1 (Q0,Q1,D0,D1,Q2,Q3,CLK,PS,LD,EN,CS);CGU24_2 (Q2,Q3,D2,D3,Q0,Q1,CLK,PS,LD,EN,CS);
Gray Code Pattern: Refer to CGU14.
Counting Range: 0-15.
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,Q = output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Macro PT GLB Output Level
CGU24 * 1.5 4 1
Input Output
PS CS LD D EN CLK Q
1 x x x x ↑ 10 1 x x x ↑ 00 0 1 d x ↑ d0 0 0 x 0 ↑ Q0 0 0 x 1 ↑ count up
CS
Q0D0
Q1D1
Q2D2
Q3D3
EN
LD
PS
CGU24
Macro Library Reference Manual 288
QI2
QI1
QI0
QI0
QI1
QI[0:3]
QI0
QI2
QI3
QI0
QI1
QI1
QI1
QI3
QI2
QI3
QI1
QI2
QI0
QI3
Q0
Q1
Q2
Q3
QI1
QI3
QI2
QI0
QI2
QI1
QI3
QI2
QI1
QI[0:3]
QI3
QI0
CLK
HOLD0
CS
QD
FD11
PS
LOAD1
D1
HOLD1
EN
D0
LD LOAD0
QD
FD11
CGU24.1
Macro Library Reference Manual 289
QI2
QI3
QI0
QI3
QI1
QI1
QI0
QI[0:3]
CLK
CS
PS
QI3
QI2
QI[0:3]QI2
QI2
QI2
QI0
QI3
QI2
QI3
QI0
QI3
QI1
QI1
LOAD2
D2
HOLD2
QD
FD11
EN
D3
LD
LOAD3
HOLD3
QD
FD11
CGU24.2
Macro Library Reference Manual 290
CGUD4
Function: 4-bit gray code up/down counter with asynchronousclear, synchronous clear and preset, enable, and parallel data load.
Availability: CGUD4 is for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
* CLK: 1 PT per GLB if Product Term Clock is used.CD: 1 PT per GLB.Q0: 11 PT Q1: 8 PTQ2: 7 PT Q3: 7 PT
Macro Port Definition:
CGUD4 ([Q0..Q3],[D0..D3],CLK,PS,LD,EN,DNUP,CD,CS);CGUD4_1 (Q0,Q1,D0,D1,Q2,Q3,CLK,PS,LD,EN,DNUP,CD,CS);CGUD4_2 (Q2,Q3,D2,D3,Q0,Q1,CLK,PS,LD,EN,DNUP,CD,CS);
Gray Code Pattern: Refer to CGU14.
Counting Range: 0↔15.
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,Q = output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Macro PT GLB Output Level
CGUD4 * 1.75 4 1
Input Output
CD PS CS LD D DNUP EN CLK Q
1 x x x x x x x 00 1 x x x x x ↑ 10 0 1 x x x x ↑ 00 0 0 1 d x x ↑ d0 0 0 0 x x 0 ↑ Q0 0 0 0 x 1 1 ↑ count down0 0 0 0 x 0 1 ↑ count up
DN/UP
PSQ0D0
Q1D1
Q2D2
Q3D3
CS
EN
LD
CD
CGUD4
Macro Library Reference Manual 291
QI0
QI1
QI2
QI3
QI[0:3]QI0
QI1
QI3
QI2
QI3
QI1
QI2
QI3
QI2
QI1
QI3
QI0
QI1
QI2
Q3
Q2
Q1
Q0
QI[0:3]
QI3
QI1
QI2
QI1
QI2
QI3
QI2
QI3
QI1
QI3
QI1
QI2
QI0
CD
CD
QD
FD21
PS
EN
D0
LD LOAD0
CS
DNUP
HOLD0
CLK
CGUD4.1
Macro Library Reference Manual 292
QI0
QI3
QI2
QI0
QI1
QI1
QI0
QI2
QI0
QI3
QI1
QI[0:3]
CD
QD
FD21
D1
LOAD1
HOLD1
QI2
QI3
QI[0:3]
QI0
QI3
QI2
QI1
DNUP
CS
PS
LD
EN
CD
CLK
CGUD4.2
Macro Library Reference Manual 293
QI1
QI0
QI2
QI1
QI0
QI0
QI3
QI2
QI[0:3]
QI1
QI0
QI3
CD
QD
FD21
CD
QD
FD21
LOAD2
HOLD2
HOLD3
LOAD3
QI1
QI3
QI3
QI3
QI3
QI2
QI2
QI3
QI1
QI2
QI0
QI2
QI1
QI[0:3]
QI2
QI0
EN
D2
D3
LD
LD
CS
PS
DNUPCLK
CD
CGUD4.3
Macro Library Reference Manual 294
I/O Pins
This chapter contains information on the following macros:
■ Bidirectional Pins
■ Input Pins
■ Output Pins
Macro Library Reference Manual 295
Bidirectional Pins
BI11, BI14, and BI18
Function:
BI11: 1-bit bidirect pin.BI14: Four BI11s with common Output Enable.BI18: Eight BI11s with common Output Enable.
Availability: BI11 is for pDS, ispDS, and ispDS+. BI14 and BI18 arefor ispDS and ispDS+.
Type: Hard
Boolean Equation:
BI11 (Z0,XB0,A0,OE);BI14 ([Z0..Z3],[XB0..XB3],[A0..A3],OE);BI18 ([Z0..Z7],[XB0..XB7],[A0..A7],OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
d = any pattern of 1s and 0s on an input or set of inputs, x = don’t care,X = X (unknown) state, Z = high impedance state,- = appears in output column if a bidirectional pin acts as an input pin.
Input Output
OE A0~An-1 XB0~XBn-1 XB0~XBn-1 Z0~Zn-1
0 x d - d0 x Z - X1 d Z d d
BI11
BI14
BI18
A
Z
XB
OE
XB0XB1XB2
Z0Z1Z2
OE
A0
A3A2A1
Z3
XB3
Z6
XB3XB2XB1XB0
Z2Z1Z0
A5
A7XB4XB5XB6
Z5
OE
A0
A3A2A1
Z7
XB7
A4
A6
Z3Z4
Macro Library Reference Manual 296
BI21, BI24, and BI28
Function:
BI21: 1-bit bidirect pin with inverted output.BI24: Four BI21s with common Output Enable.BI28: Eight BI21s with common Output Enable.
Availability: BI21 is for pDS, ispDS, and ispDS+. BI24 and BI28 arefor ispDS and ispDS+.
Type: Hard
Boolean Equation:
BI21 (Z0,XB0,A0,OE);BI24 ([Z0..Z3],[XB0..XB3],[A0..A3],OE);BI28 ([Z0..Z7],[XB0..XB7],[A0..A7],OE);
Truth Table:
Do not drive XB0~XBn-1when OE=1.
d = any pattern of 1s and 0s on an input or set of inputs,d = inverse of d, x = don’t care, X = X (unknown) state,Z = high impedance state, - = appears in output column ifa bidirectional pin acts as an input pin.
Input Output
OE A0~An-1 XB0~XBn-1 XB0~XBn-1 Z0~Zn-1
0 x d - d0 x Z - X1 d Z d d
BI21
BI24
BI28
A
Z
XB
OE
XB0XB1XB2
Z0Z1Z2
OE
A0
A3A2A1
Z3
XB3
Z6
XB3XB2XB1XB0
Z2Z1Z0
A5
A7XB4XB5XB6
Z5
OE
A0
A3A2A1
Z7
XB7
A4
A6
Z3Z4
Macro Library Reference Manual 297
BI31, BI34, and BI38
Function:
BI31: 1-bit bidirect pin with active low Output Enable.BI34: Four BI31s with common Output Enable.BI38: Eight BI31s with common Output Enable.
Availability: BI31 is for pDS, ispDS, and ispDS+. BI34 and BI38 arefor ispDS and ispDS+.
Type: Hard
Boolean Equation:
BI31 (Z0,XB0,A0,OE);BI34 ([Z0..Z3],[XB0..XB3],[A0..A3],OE);BI38 ([Z0..Z7],[XB0..XB7],[A0..A7],OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=0.
d = any pattern of 1s and 0s on an input or set of inputs,x = don’t care, X = X (unknown) state, Z = high impedance state,- = appears in output column if a bidirectional pin acts as an input pin.
Input Output
OE A0~An-1 XB0~XBn-1 XB0~XBn-1 Z0~Zn-1
0 d Z d d1 x d - d1 x Z - X
BI31
BI34
BI38
A
ZXB
OE
XB0XB1XB2
Z0Z1Z2
OE
A0
A3A2A1
Z3
XB3
Z6
XB3XB2XB1XB0
Z2Z1Z0
A5
A7XB4XB5XB6
Z5
OE
A0
A3A2A1
Z7
XB7
A4
A6
Z3Z4
Macro Library Reference Manual 298
BI41, BI44, and BI48
Function:
BI41: 1-bit bidirect pin with inverted output and active lowOutput Enable.
BI44: Four BI41s with common Output Enable.BI48: Eight BI41s with common Output Enable.
Availability: BI41 is for pDS, ispDS, and ispDS+. BI44 and BI48 arefor ispDS and ispDS+.
Type: Hard
Boolean Equation:
BI41 (Z0,XB0,A0,OE);BI44 ([Z0..Z3],[XB0..XB3],[A0..A3],OE);BI48 ([Z0..Z7],[XB0..XB7],[A0..A7],OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=0.
d = any pattern of 1s and 0s on an input or set of inputs,d = inverse of d, x = don’t care, X = X (unknown) state,Z = high impedance state,- = appears in output column if a bidirectional pin acts as an input pin.
Input Output
OE A0~An-1 XB0~XBn-1 XB0~XBn-1 Z0~Zn-1
0 d Z d d
1 x d - d1 x Z - X
BI41
BI44
BI48
A
ZXB
OE
XB0XB1XB2
Z0Z1Z2
OE
A0
A3A2A1
Z3
XB3
Z6
XB3XB2XB1XB0
Z2Z1Z0
A5
A7XB4XB5XB6
Z5
OE
A0
A3A2A1
Z7
XB7
A4
A6
Z3Z4
Macro Library Reference Manual 299
BIID11, BIID14, and BIID18
Function:
BIID11: 1-bit bidirect pin with registered input.BIID14: Four BIID11s with common clock and Output
Enable.BIID18: Eight BIID11s with common clock and Output
Enable.
Availability: BIID11 is for pDS, ispDS, and ispDS+. BIID14 andBIID18 are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
BIID11 (Q0,XB0,A0,CLK,OE);BIID14 ([Q0..Q3],[XB0..XB3],[A0..A3],CLK,OE);BIID18 ([Q0..Q7],[XB0..XB7],[A0..A7],CLK,OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
d = any pattern of 1s and 0s on an input or set of inputs,Q’ = previous output of flip-flop or latch, x = don’t care,X = X (unknown) state, Z = high impedance state,- = appears in output column if a bidirectional pin acts as an input pin,↑ = rising clock edge.
Input Output
OE A0~An-1 XB0~XBn-1 CLK XB0~XB n-1 Q0~Qn-1
0 x d ↑ - d0 x Z ↑ - X1 d Z ↑ d d0 x x 0 - Q’0 x x 1 - Q’1 d Z 0 d Q’1 d Z 1 d Q’
BIID11
BIID14
BIID18
D
A
Q
XB
OE
XB3
Q3
Q1Q0
XB0XB1
A3A2A1
OE
A0
Q2
XB2
OE
A0
XB2XB1XB0
XB3
Q2
Q0Q1
Q3
A4
A6
Q7
Q5Q4
XB4XB5
A3A2A1
Q6
XB6XB7
A5
A7
Macro Library Reference Manual 300
BIID21, BIID24, and BIID28
Function:
BIID21: 1-bit bidirect pin with registered input and invertedoutput.
BIID24: Four BIID21s with common clock and OutputEnable.
BIID28: Eight BIID21s with common clock and OutputEnable.
Availability: BIID21 is for pDS, ispDS, and ispDS+. BIID24 andBIID28 are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
BIID21 (Q0,XB0,A0,CLK,OE);BIID24 ([Q0..Q3],[XB0..XB3],[A0..A3],CLK,OE);BIID28 ([Q0..Q7],[XB0..XB7],[A0..A7],CLK,OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
d = any pattern of 1s and 0s on an input or set of inputs,Q’ = previous output of flip-flop or latch, x = don’t care,X = X (unknown) state, Z = high impedance state,- = appears in output column if a bidirectional pin acts as an input pin,↑ = rising clock edge.
Input Output
OE A0~An-1 XB0~XBn-1 CLK XB0~XB n-1 Q0~Qn-1
0 x d ↑ - d0 x Z ↑ - X1 d Z ↑ d d
0 x x 0 - Q’0 x x 1 - Q’1 d Z 0 d Q’1 d Z 1 d Q’
BIID11
BIID14
BIID18
D
A
Q
XB
OE
XB3
Q3
Q1Q0
XB0XB1
A3A2A1
OE
A0
Q2
XB2
OE
A0
XB2XB1XB0
XB3
Q2
Q0Q1
Q3
A4
A6
Q7
Q5Q4
XB4XB5
A3A2A1
Q6
XB6XB7
A5
A7
Macro Library Reference Manual 301
BIID31, BIID34, and BIID38
Function:
BIID31: 1-bit bidirect pin with registered input and activelow enable.
BIID34: Four BIID31s with common clock and OutputEnable.
BIID38: Eight BIID31s with common clock and OutputEnable.
Availability: BIID31 is for pDS, ispDS, and ispDS+. BIID34 andBIID38 are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
BIID31 (Q0,XB0,A0,CLK,OE);BIID34 ([Q0..Q3],[XB0..XB3],[A0..A3],CLK,OE);BIID38 ([Q0..Q7],[XB0..XB7],[A0..A7],CLK,OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
d = any pattern of 1s and 0s on an input or set of inputs,Q’ = previous output of flip-flop or latch, x = don’t care,X = X (unknown) state, Z = high impedance state,- = appears in output column if a bidirectional pin acts as an input pin,↑ = rising clock edge.
Input Output
OE A0~An-1 XB0~XBn-1 CLK XB0~XB n-1 Q0~Qn-1
0 d Z ↑ d d1 x d ↑ - d1 x Z ↑ - X0 d Z 0 d Q’0 d Z 1 d Q’1 x x 0 - Q’1 x x 1 - Q’
BIID31
BIID34
BIID38
D
A
Q
XB
OE
XB3
Q3
Q1Q0
XB0XB1
A3A2A1
OE
A0
Q2
XB2
OE
A0
XB2XB1XB0
XB3
Q2
Q0Q1
Q3
A4
A6
Q7
Q5Q4
XB4XB5
A3A2A1
Q6
XB6XB7
A5
A7
Macro Library Reference Manual 302
BIID41, BIID44, and BIID48
Function:
BIID41: 1-bit bidirect pin with registered input, invertedoutput, and active low enable.
BIID44: Four BIID41s with common clock and OutputEnable.
BIID48: Eight BIID41s with common clock and OutputEnable.
Availability: BIID41 is for pDS, ispDS, and ispDS+. BIID44 andBIID48 are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
BIID41 (Q0,XB0,A0,CLK,OE);BIID44 ([Q0..Q3],[XB0..XB3],[A0..A3],CLK,OE);BIID48 ([Q0..Q7],[XB0..XB7],[A0..A7],CLK,OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
d = any pattern of 1s and 0s on an input or set of inputs, d = inverse of d,Q’ = previous output of flip-flop or latch, x = don’t care, X = X (unknown) state,Z = high impedance state, ↑ = rising clock edge - = appears in output column if a bidirectional pin acts as an input pin.
Input Output
OE A0~An-1 XB0~XBn-1 CLK XB0~XB n-1 Q0~Qn-1
0 d Z ↑ d d
1 x d ↑ - d1 x Z ↑ - X0 d Z 0 d Q’0 d Z 1 d Q’1 x x 0 - Q’1 x x 1 - Q’
BIID41
BIID44
BIID48
D
A
Q
XB
OE
XB3
Q3
Q1Q0
XB0XB1
A3A2A1
OE
A0
Q2
XB2
OE
A0
XB2XB1XB0
XB3
Q2
Q0Q1
Q3
A4
A6
Q7
Q5Q4
XB4XB5
A3A2A1
Q6
XB6XB7
A5
A7
Macro Library Reference Manual 303
BIID51, BIID54, and BIID58
Function:
BIID51: 1-bit bidirect pin with registered input and invertedclock.
BIID54: Four BIID51s with common clock and OutputEnable.
BIID58: Eight BIID51s with common clock and OutputEnable.
Availability: BIID51 is for pDS, ispDS, and ispDS+. BIID54 andBIID58 are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
BIID51 (Q0,XB0,A0,CLK,OE);BIID54 ([Q0..Q3],[XB0..XB3],[A0..A3],CLK,OE);BIID58 ([Q0..Q7],[XB0..XB7],[A0..A7],CLK,OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
d = any pattern of 1s and 0s on an input or set of inputs,Q’ = previous output of flip-flop or latch, x = don’t care,X = X (unknown) state, Z = high impedance state,- = appears in output column if a bidirectional pin acts as an input pin,↓ = falling clock edge.
Input Output
OE A0~An-1 XB0~XBn-1 CLK XB0~XB n-1 Q0~Qn-1
0 x d ↓ - d0 x Z ↓ - X1 d Z ↓ d d0 x x 0 - Q’0 x x 1 - Q’1 d Z 0 d Q’1 d Z 1 d Q’
BIID51
BIID54
BIID58
D
A
Q
XB
OE
XB3
Q3
Q1Q0
XB0
XB1A3A2A1
OE
A0
Q2
XB2
OE
A0
XB2XB1
XB0
XB3
Q2
Q0Q1
Q3
A4
A6
Q7
Q5Q4
XB4
XB5
A3
A2A1
Q6
XB6
XB7
A5
A7
Macro Library Reference Manual 304
BIID61, BIID64, and BIID68
Function:
BIID61: 1-bit bidirect pin with registered input, invertedoutput, and inverted clock.
BIID64: Four BIID61s with common clock and OutputEnable.
BIID68: Eight BIID61s with common clock and OutputEnable.
Availability: BIID61 is for pDS, ispDS, and ispDS+. BIID64 andBIID68 are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
BIID61 (Q0,XB0,A0,CLK,OE);BIID64 ([Q0..Q3],[XB0..XB3],[A0..A3],CLK,OE);BIID68 ([Q0..Q7],[XB0..XB7],[A0..A7],CLK,OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
d = any pattern of 1s and 0s on an input or set of inputs,Q’ = previous output of flip-flop or latch,x = don’t care, X = X (unknown) state, Z = high impedance state,- = appears in output column if a bidirectional pin acts as an input pin,↓ = falling clock edge.
Input Output
OE A0~An-1 XB0~XBn-1 CLK XB0~XB n-1 Q0~Qn-1
0 x d ↓ - d0 x Z ↓ - X1 d Z ↓ d d
0 x x 0 - Q’0 x x 1 - Q’1 d Z 0 d Q’1 d Z 1 d Q’
BIID61
BIID64
BIID68
D
A
Q
XB
OE
XB3
Q3
Q1Q0
XB0XB1
A3A2A1
OE
A0
Q2
XB2
OE
A0
XB2XB1XB0
XB3
Q2
Q0Q1
Q3
A4
A6
Q7
Q5Q4
XB4XB5
A3A2A1
Q6
XB6XB7
A5
A7
Macro Library Reference Manual 305
BIID71, BIID74, and BIID78
Function:
BIID71: 1-bit bidirect pin with registered input, active lowenable, and inverted clock.
BIID74: Four BIID71s with common clock and OutputEnable.
BIID78: Eight BIID71s with common clock and OutputEnable.
Availability: BIID71 is for pDS, ispDS, and ispDS+. BIID74 andBIID78 are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
BIID71 (Q0,XB0,A0,CLK,OE);BIID74 ([Q0..Q3],[XB0..XB3],[A0..A3],CLK,OE);BIID78 ([Q0..Q7],[XB0..XB7],[A0..A7],CLK,OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
d = any pattern of 1s and 0s on an input or set of inputs,Q’ = previous output of flip-flop or latch,x = don’t care, X = X (unknown) state, Z = high impedance state,- = appears in output column if a bidirectional pin acts as an input pin,↓ = falling clock edge.
Input Output
OE A0~An-1 XB0~XBn-1 CLK XB0~XB n-1 Q0~Qn-1
0 d Z ↓ d d1 x d ↓ - d1 x Z ↓ - X0 d Z 0 d Q’0 d Z 1 d Q’1 x x 0 - Q’1 x x 1 - Q’
BIID71
BIID74
BIID78
D
A
Q
XB
OE
XB3
Q3
Q1Q0
XB0
XB1A3A2A1
OE
A0
Q2
XB2
OE
A0
XB2XB1
XB0
XB3
Q2
Q0Q1
Q3
A4
A6
Q7
Q5Q4
XB4
XB5
A3A2A1
Q6
XB6
XB7
A5
A7
Macro Library Reference Manual 306
BIID81, BIID84, and BIID88
Function:
BIID81: 1-bit bidirect pin with registered input, invertedoutput, active low enable, and inverted clock.
BIID84: Four BIID81s with common clock and OutputEnable.
BIID88: Eight BIID81s with common clock and OutputEnable.
Availability: BIID81 is for pDS, ispDS, and ispDS+. BIID84 andBIID88 are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
BIID81 (Q0,XB0,A0,CLK,OE);BIID84 ([Q0..Q3],[XB0..XB3],[A0..A3],CLK,OE);BIID88 ([Q0..Q7],[XB0..XB7],[A0..A7],CLK,OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
d = any pattern of 1s and 0s on an input or set of inputs, d = inverse of d,Q’ = previous output of flip-flop or latch, x = don’t care,X = X (unknown) state, Z = high impedance state, ↓ = falling clock edge.,- = appears in output column if a bidirectional pin acts as an input pin.
Input Output
OE A0~An-1 XB0~XBn-1 CLK XB0~XB n-1 Q0~Qn-1
0 d Z ↓ d d
1 x d ↓ - d1 x Z ↓ - X0 d Z 0 d Q’0 d Z 1 d Q’1 x x 0 - Q’1 x x 1 - Q’
D
A
Q
XB
OEBIID81
BIID84
BIID88
XB3
Q3
Q1
Q0
XB0
XB1A3
A2
A1
OE
A0
Q2
XB2
OE
A0
XB2
XB1
XB0
XB3
Q2
Q0
Q1
Q3
A4
A6
Q7
Q5
Q4
XB4
XB5
A3
A2
A1
Q6
XB6
XB7
A5
A7
Macro Library Reference Manual 307
BIIL11, BIIL14, and BIIL18
Function:
BIIL11: 1-bit bidirect pin with latched input.BIIL14: Four BIIL11s with common G and Output Enable.BIIL18: Eight BIIL11s with common G and Output Enable.
Availability: BIIL11 is for pDS, ispDS, and ispDS+. BIIL14 andBIIL18 are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
BIIL11 (Q0,XB0,A0,G,OE);BIIL14 ([Q0..Q3],[XB0..XB3],[A0..A3],G,OE);BIIL18 ([Q0..Q7],[XB0..XB7],[A0..A7],G,OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
d = any pattern of 1s and 0s on an input or set of inputs, d = inverse of d,Q’ = previous output of flip-flop or latch, x = don’t care, X = X (unknown) state,Z = high impedance state, - = appears in output column if a bidirectional pin actsas an input pin.
Input Output
OE A0~An-1 XB0~XBn-1 G XB0~XBn-1 Q0~Qn-1
0 x x 0 - Q’1 d Z 0 d Q’0 x d 1 - d0 x Z 1 - x1 d Z 1 d d
BIIL11
BIIL14
BIIL18
D
A
Q
XB
OE
XB3
Q3
Q1Q0
XB0XB1
A3A2A1
OE
A0
Q2
XB2
OE
A0
XB2XB1XB0
XB3
Q2
Q0Q1
Q3
A4
A6
Q7
Q5Q4
XB4XB5
A3A2A1
Q6
XB6XB7
A5
A7
G
G
G
Macro Library Reference Manual 308
BIIL21, BIIL24, and BIIL28
Function:
BIIL21: 1-bit bidirect pin with latched input and invertedoutput.
BIIL24: Four BIIL21s with common G and Output Enable.BIIL28: Eight BIIL21s with common G and Output Enable.
Availability: BIIL21 is for pDS, ispDS, and ispDS+. BIIL24 andBIIL28 are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
BIIL21 (Q0,XB0,A0,G,OE);BIIL24 ([Q0..Q3],[XB0..XB3],[A0..A3],G,OE);BIIL28 ([Q0..Q7],[XB0..XB7],[A0..A7],G,OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
d = any pattern of 1s and 0s on an input or set of inputs, d = inverse of d,Q’ = previous output of flip-flop or latch, x = don’t care,X = X (unknown) state, Z = high impedance state,- = appears in output column if a bidirectional pin acts as an input pin.
Input Output
OE A0~An-1 XB0~XBn-1 G XB0~XBn-1 Q0~Qn-1
0 x x 0 - Q’1 d Z 0 d Q’0 x d 1 - d0 x Z 1 - x1 d Z 1 d d
BIIL21
BIIL24
BIIL28
D
A
Q
XB
OE
XB3
Q3
Q1
Q0
XB0
XB1A3
A2
A1
OE
A0
Q2
XB2
OE
A0
XB2
XB1
XB0
XB3
Q2
Q0
Q1
Q3
A4
A6
Q7
Q5
Q4
XB4
XB5
A3
A2
A1
Q6
XB6
XB7
A5
A7
G
G
G
Macro Library Reference Manual 309
BIIL31, BIIL34, and BIIL38
Function:
BIIL31: 1-bit bidirect pin with latched input and active lowenable.
BIIL34: Four BIIL31s with common G and Output Enable.BIIL38: Eight BIIL31s with common G and Output Enable.
Availability: BIIL31 is for pDS, ispDS, and ispDS+. BIIL34 andBIIL38 are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
BIIL31 (Q0,XB0,A0,G,OE);BIIL34 ([Q0..Q3],[XB0..XB3],[A0..A3],G,OE);BIIL38 ([Q0..Q7],[XB0..XB7],[A0..A7],G,OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=0.
d = any pattern of 1s and 0s on an input or set of inputs,Q’ = previous output of flip-flop or latch, x = don’t care,X = X (unknown) state, Z = high impedance state,- = appears in output column if a bidirectional pin acts as an input pin.
Input Output
OE A0~An-1 XB0~XBn-1 G XB0~XBn-1 Q0~Qn-1
0 d Z 0 d Q’1 x x 0 - Q’0 d Z 1 d d1 x d 1 - d1 x Z 1 - X
BIIL31
BIIL34
BIIL38
D
A
Q
XB
OE
XB3
Q3
Q1Q0
XB0XB1
A3A2A1
OE
A0
Q2
XB2
OE
A0
XB2XB1XB0
XB3
Q2
Q0Q1
Q3
A4
A6
Q7
Q5Q4
XB4XB5
A3A2A1
Q6
XB6XB7
A5
A7
G
G
G
Macro Library Reference Manual 310
BIIL41, BIIL44, and BIIL48
Function:
BIIL41: 1-bit bidirect pin with latched input, inverted output,and active low enable.
BIIL44: Four BIIL41s with common G and Output Enable.BIIL48: Eight BIIL41s with common G and Output Enable.
Availability: BIIL41 is for pDS, ispDS, and ispDS+. BIIL44 andBIIL48 are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
BIIL41 (Q0,XB0,A0,G,OE);BIIL44 ([Q0..Q3],[XB0..XB3],[A0..A3],G,OE);BIIL48 ([Q0..Q7],[XB0..XB7],[A0..A7],G,OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=0.
d = any pattern of 1s and 0s on an input or set of inputs, d = inverse of d,Q’ = previous output of flip-flop or latch, x = don’t care,X = X (unknown) state, Z = high impedance state,- = appears in output column if a bidirectional pin acts as an input pin.
Input Output
OE A0~An-1 XB0~XBn-1 G XB0~XBn-1 Q0~Qn-1
0 d Z 0 d Q’1 x x 0 - Q’0 d Z 1 d d1 x d 1 - d1 x Z 1 - X
BIIL41
BIIL44
BIIL48
D
A
Q
XB
OE
XB3
Q3
Q1Q0
XB0XB1
A3A2A1
OE
A0
Q2
XB2
OE
A0
XB2XB1XB0
XB3
Q2
Q0Q1
Q3
A4
A6
Q7
Q5Q4
XB4XB5
A3A2A1
Q6
XB6XB7
A5
A7
G
G
G
Macro Library Reference Manual 311
BIIL51, BIIL54, and BIIL58
Function:
BIIL51: 1-bit bidirect pin with latched input and inverted G.BIIL54: Four BIIL51s with common G and Output Enable.BIIL58: Eight BIIL51s with common G and Output Enable.
Availability: BIIL51 is for pDS, ispDS, and ispDS+. BIIL54 andBIIL58 are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
BIIL51 (Q0,XB0,A0,G,OE);BIIL54 ([Q0..Q3],[XB0..XB3],[A0..A3],G,OE);BIIL58 ([Q0..Q7],[XB0..XB7],[A0..A7],G,OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
d = any pattern of 1s and 0s on an input or set of inputs,Q’ = previous output of flip-flop or latch, x = don’t care,X = unknown state, Z = high impedance state, - = appears in output column if a bidirectional pin acts as an input pin.
Input Output
OE A0~An-1 XB0~XBn-1 G XB0~XBn-1 Q0~Qn-1
0 x d 0 - d0 x Z 0 - X1 d Z 0 d d0 x x 1 - Q’1 d Z 1 d Q’
BIIL51
BIIL54
BIIL58
D
A
Q
XB
OE
XB3
Q3
Q1Q0
XB0XB1
A3A2A1
OE
A0
Q2
XB2
OE
A0
XB2XB1XB0
XB3
Q2
Q0Q1
Q3
A4
A6
Q7
Q5Q4
XB4XB5
A3A2A1
Q6
XB6XB7
A5
A7
G
G
G
Macro Library Reference Manual 312
BIIL61, BIIL64, and BIIL68
Function:
BIIL61: 1-bit bidirect pin with latched input, inverted output,and inverted G.
BIIL64: Four BIIL61s with common G and Output Enable.BIIL68: Eight BIIL61s with common G and Output Enable.
Availability: BIIL61 is for pDS, ispDS, and ispDS+. BIIL64 andBIIL68 are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
BIIL61 (Q0,XB0,A0,G,OE);BIIL64 ([Q0..Q3],[XB0..XB3],[A0..A3],G,OE);BIIL68 ([Q0..Q7],[XB0..XB7],[A0..A7],G,OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
d = any pattern of 1s and 0s on an input or set of inputs, d = inverse of d,Q’ = previous output of flip-flop or latch, x = don’t care,X = unknown state, Z = high impedance state,- = appears in output column if a bidirectional pin acts as an input pin.
Input Output
OE A0~An-1 XB0~XBn-1 G XB0~XBn-1 Q0~Qn-1
0 x d 0 - d0 x Z 0 - X1 d Z 0 d d
0 x x 1 - Q’1 d Z 1 d Q’
BIIL61
BIIL64
BIIL68
D
A
Q
XB
OE
XB3
Q3
Q1Q0
XB0XB1
A3A2A1
OE
A0
Q2
XB2
OE
A0
XB2XB1XB0
XB3
Q2
Q0Q1
Q3
A4
A6
Q7
Q5Q4
XB4XB5
A3A2A1
Q6
XB6XB7
A5
A7
G
G
G
Macro Library Reference Manual 313
BIIL71, BIIL74, and BIIL78
Function:
BIIL71: 1-bit bidirect pin with latched input, active lowenable, and inverted G.
BIIL74: Four BIIL71s with common G and Output Enable.BIIL78: Eight BIIL71s with common G and Output Enable.
Availability: BIIL71 is for pDS, ispDS, and ispDS+. BIIL74 andBIIL78 are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
BIIL71 (Q0,XB0,A0,G,OE);BIIL74 ([Q0..Q3],[XB0..XB3],[A0..A3],G,OE);BIIL78 ([Q0..Q7],[XB0..XB7],[A0..A7],G,OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=0.
d = any pattern of 1s and 0s on an input or set of inputs,Q’ = previous output of flip-flop or latch, x = don’t care,X = unknown state, Z = high impedance state, - = appears in output column if a bidirectional pin acts as an input pin.
Input Output
OE A0~An-1 XB0~XBn-1 G XB0~XBn-1 Q0~Qn-1
0 d Z 0 d d1 x d 0 - d1 x Z 0 - X0 d Z 1 d Q’1 x x 1 - Q’
BIIL71
BIIL74
BIIL78
D
A
Q
XB
OE
XB3
Q3
Q1Q0
XB0XB1
A3A2A1
OE
A0
Q2
XB2
OE
A0
XB2XB1XB0
XB3
Q2
Q0Q1
Q3
A4
A6
Q7
Q5Q4
XB4XB5
A3A2A1
Q6
XB6XB7
A5
A7
G
G
G
Macro Library Reference Manual 314
BIIL81, BIIL84, and BIIL88
Function:
BIIL81: 1-bit bidirect pin with latched input, inverted output,active low enable, and inverted G.
BIIL84: Four BIIL81s with common G and Output Enable.BIIL88: Eight BIIL81s with common G and Output Enable.
Availability: BIIL81 is for pDS, ispDS, and ispDS+. BIIL84 andBIIL88 are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
BIIL81 (Q0,XB0,A0,G,OE);BIIL84 ([Q0..Q3],[XB0..XB3],[A0..A3],G,OE);BIIL88 ([Q0..Q7],[XB0..XB7],[A0..A7],G,OE);
Truth Table:
Do not drive XB0~XBn-1 when OE=0.
d = any pattern of 1s and 0s on an input or set of inputs, d = inverse of d,Q’ = previous output of flip-flop or latch, x = don’t care,X = unknown state, Z = high impedance state, - = appears in output column if a bidirectional pin acts as an input pin.
Input Output
OE A0~An-1 XB0~XBn-1 G XB0~XBn-1 Q0~Qn-1
0 d Z 0 d d
1 x d 0 - d1 x Z 0 - X0 d Z 1 d Q’1 x x 1 - Q’
BIIL81
BIIL84
BIIL88
D
A
Q
XB
OE
XB3
Q3
Q1Q0
XB0XB1
A3A2A1
OE
A0
Q2
XB2
OE
A0
XB2XB1XB0
XB3
Q2
Q0Q1
Q3
A4
A6
Q7
Q5Q4
XB4XB5
A3A2A1
Q6
XB6XB7
A5
A7
G
G
G
Macro Library Reference Manual 315
Input Pins
IB11
Function: 1-bit input pin.
Availability: IB11 is for pDS, ispDS, and ispDS+.
Type: Hard
Macro Port Definition:
IB11(Z0,XI0);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,XI0 = external input pin, Z0 = output.
Input Output
XI0 Z0
d d
XI Z
IB11
Macro Library Reference Manual 316
ID11, ID14, and ID18
Function:
ID11: 1-bit registered input pin.ID14: Four ID11s with common clock.ID18: Eight ID11s with common clock.
Availability: ID11 is for pDS, ispDS, and ispDS+. ID14 and ID18 arefor ispDS and ispDS+.
Type: Hard
Boolean Equation:
ID11 (Q0,XI0,CLK);ID14 ([Q0..Q3],[XI0..XI3],CLK);ID18 ([Q0..Q7],[XI0..XI7],CLK);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch,x = don’t care, ↑ = rising clock edge.
Input Output
XI0~XIn-1 CLK Q0~Qn-1
d ↑ dx 0 Q0’~Qn’x 1 Q0’~Qn’
DXI Q
ID11
ID14
ID18
D
D
D
D
XI0
XI1
XI2
Q0
Q1
Q2
Q3XI3
D
D
D
D
D
D
D
D
Q0
Q1
Q2
Q3XI3
XI2
XI1
XI0
XI4
XI5
XI6
XI7 Q7
Q6
Q5
Q4
Macro Library Reference Manual 317
ID21, ID24, and ID28
Function:
ID21: 1-bit registered input pin with inverted clock.ID24: Four ID21s with common clock.ID28: Eight ID21s with common clock.
Availability: ID21 is for pDS, ispDS, and ispDS+. ID24 and ID28 arefor ispDS and ispDS+.
Type: Hard
Boolean Equation:
ID21 (Q0,XI0,CLK);ID24 ([Q0..Q3],[XI0..XI3],CLK);ID28 ([Q0..Q7],[XI0..XI7],CLK);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch,x = don’t care, ↓ = falling clock edge.
Input Output
XI0~XIn-1 CLK Q0~Qn-1
d ↓ dx 0 Q0’~Qn’x 1 Q0’~Qn’
DXI Q
ID21
ID24
ID28
D
D
D
D
XI0
XI1
XI2
Q0
Q1
Q2
Q3XI3
D
D
D
D
D
D
D
D
Q0
Q1
Q2
Q3XI3
XI2
XI1
XI0
XI4
XI5
XI6
XI7 Q7
Q6
Q5
Q4
Macro Library Reference Manual 318
IL11, IL14, and IL18
Function:
IL11: 1-bit input pin with D latch on input.IL14: Four IL11s with common G.IL18: Eight IL11s with common G.
Availability: IL11 is for pDS, ispDS, and ispDS+. IL14 and IL18 arefor ispDS and ispDS+.
Type: Hard
Boolean Equation:
IL11 (Q0,XI0,G);IL14 ([Q0..Q3],[XI0..XI3],G);IL18 ([Q0..Q7],[XI0..XI7],G);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,G = gate for latch, x = don’t care,Q0’~Qn’ = previous output of flip-flop or latch.
Input Output
XI0~XIn-1 G Q0~Qn-1
x 0 Q0’~Qn’d 1 d
DXI Q
IL11
IL14
IL18
D
D
D
D
XI0
XI1
XI2
Q0
Q1
Q2
Q3XI3
D
D
D
D
D
D
D
D
Q0
Q1
Q2
Q3XI3
XI2
XI1
XI0
XI4
XI5
XI6
XI7 Q7
Q6
Q5
Q4
G
G
G
Macro Library Reference Manual 319
IL21, IL24, and IL28
Function:
IL21: 1-bit input pin with D latch on input, inverted enable.IL24: Four IL21s with common G.IL28: Eight IL21s with common G.
Availability: IL21 is for pDS, ispDS, and ispDS+. IL24 and IL28 arefor ispDS and ispDS+.
Type: Hard
Boolean Equation:
IL21 (Q0,XI0,G);IL24 ([Q0..Q3],[XI0..XI3],G);IL28 ([Q0..Q7],[XI0..XI7],G);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch,x = don’t care.
Input Output
XI0~XIn-1 G Q0~Qn-1
d 0 dx 1 Q0’~Qn’
DXI Q
IL21
IL24
IL28
D
D
D
D
XI0
XI1
XI2
Q0
Q1
Q2
Q3XI3
D
D
D
D
D
D
D
D
Q0
Q1
Q2
Q3XI3
XI2
XI1
XI0
XI4
XI5
XI6
XI7 Q7
Q6
Q5
Q4
G
G
G
Macro Library Reference Manual 320
Output Pins
OB11
Function: 1-bit output pin.
Availability: OB11 is for pDS, ispDS, and ispDS+.
Type: Hard
Macro Port Definition:
OB11 (XO0,A0);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs
Input Output
A0 XO0
d d
A XO
OB11
Macro Library Reference Manual 321
OB21, OB24, and OB28
Function:
OB21: 1-bit inverting output pin.OB24: Four OB21s.OB28: Eight OB21s.
Availability: OB21 is for pDS, ispDS, and ispDS+. OB24 and OB28are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
OB21 (XO0,A0);OB24 ([XO0..XO3],[A0..A3]);OB28 ([XO0..XO7],[A0..A7]);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,d = inverse of d.
Input Output
A0~An-1 XO0~XOn-1
d d
A XO
OB21
XO0A0
XO1A1
XO2A2
A3XO3
OB24
XO0
XO1
XO2
XO3A3
A2
A1
A0
A4
A5
A6
A7XO7
XO6
XO5
XO4
OB28
Macro Library Reference Manual 322
OT11, OT14, and OT18
Function:
OT11: 1-bit 3-state output pin.OT14: Four OT11s with common Output Enable.OT18: Eight OT11s with common Output Enable.
Availability: OT11 is for pDS, ispDS, and ispDS+. OT14 and OT18are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
OT11 (XO0,A0,OE);OT14 ([XO0..XO3],[A0..A3],OE);OT18 ([XO0..XO7],[A0..A7],OE);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,x = don’t care, Z = high impedance state.
Input Output
OE A0~An-1 XO0~XOn-1
0 x Z1 d d
OT11
XOA
OE
XO3A3
XO2A2
XO1A1
OE
A0 XO0
OT14
XO3A3
XO2A2
XO1A1
A0 XO0
XO4A4
A5 XO5
A6 XO6
A7 XO7
OE
OT18
Macro Library Reference Manual 323
OT21, OT24, and OT28
Function:
OT21: 1-bit inverting 3-state output pin.OT24: Four OT21s with common Output Enable.OT28: Eight OT21s with common Output Enable.
Availability: OT21 is for pDS, ispDS, and ispDS+. OT24 and OT28are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
OT21 (XO0,A0,OE);OT24 ([XO0..XO3],[A0..A3],OE);OT28 ([XO0..XO7],[A0..A7],OE);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,d = inverse of d, x = don’t care, Z = high impedance state.
Input Output
OE A0~An-1 XO0~XOn-1
0 x Z1 d d
XO3A3
XO2A2
XO1A1
OE
A0 XO0
OT21
XOA
OE
OT24
XO3A3
XO2A2
XO1A1
A0 XO0
XO4A4
A5 XO5
A6 XO6
A7 XO7
OE
OT28
Macro Library Reference Manual 324
OT31, OT34, and OT38
Function:
OT31: 1-bit 3-state output pin with active low enable.OT34: Four OT31s with common Output Enable.OT38: Eight OT31s with common Output Enable.
Availability: OT31 is for pDS, ispDS, and ispDS+. OT34 and OT38are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
OT31 (XO0,A0,OE);OT34 ([XO0..XO3],[A0..A3],OE);OT38 ([XO0..XO7],[A0..A7],OE);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,x = don’t care, Z = high impedance state.
Input Output
OE A0~An-1 XO0~XOn-1
0 d d1 x Z
OT31
XOA
OE
XO3A3
XO2A2
XO1A1
OE
A0 XO0
OT34
XO3A3
XO2A2
XO1A1
A0 XO0
XO4A4
A5 XO5
A6 XO6
A7 XO7
OE
OT38
Macro Library Reference Manual 325
OT41, OT44, and OT48
Function:
OT41: 1-bit inverting 3-state output pin with active low enable.OT44: Four OT41s with common Output Enable.OT48: Eight OT41s with common Output Enable.
Availability: OT41 is for pDS, ispDS, and ispDS+. OT44 and OT48are for ispDS and ispDS+.
Type: Hard
Boolean Equation:
OT41 (XO0,A0,OE);OT44 ([XO0..XO3],[A0..A3],OE);OT48 ([XO0..XO7],[A0..A7],OE);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,d = inverse of d, x = don’t care, Z = high impedance state.
Input Output
OE A0~An-1 XO0~XOn-1
0 d d
1 x Z
XO3A3
XO2A2
XO1A1
OE
A0 XO0
OT41
XOA
OE
OT44
XO3A3
XO2A2
XO1A1
A0 XO0
XO4A4
A5 XO5
A6 XO6
A7 XO7
OE
OT48
Macro Library Reference Manual 326
Logic Gates
This chapter contains information on logic gate macros.
Macro Library Reference Manual 327
Logic Gates
AND2 Through AND18
Function: 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18input AND gates.
Availability : AND2, AND3, AND4, AND5, AND6, AND7, AND8,AND9, AND10, AND 11, AND12, and AND16 are for pDS, ispDSand ispDS+. AND 13, AND 14, AND 15, AND 17, and AND 18 arefor ispDS and ispDS+.
Type: Logic Primitive
Boolean Equation:
AND2 (Z0,A0,A1);AND3 (Z0,[A0..A2]);AND4 (Z0,[A0..A3]);...AND18 (Z0,[A0..A17]);
Truth Table:
The truth table is the same for all ANDs.
Input Output
All inputs high HighOne or more inputs low Low
AND2
AND3
AND18
. . .
Macro Library Reference Manual 328
BUF and INV
Function:
BUF: single input buffer.INV: single input inverter.
Availability: BUF and INV are for pDS, ispDS, and ispDS+.
Type: Logic Primitive
Macro Port Definition:
BUF (Z0,A0);INV (ZN0,A0);
Truth Tables:
For BUF:
For INV:
Input Output
High HighLow Low
Input Output
High LowLow High
BUF
INV
Macro Library Reference Manual 329
NAND2 Through NAND12 & NAND16
Function: 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 16 input NANDgates.
Availability: NAND2, NAND3, NAND4, NAND5, NAND6,NAND7, NAND8, NAND9, NAND10, NAND11, NAND12, andNAND16 are for pDS, ispDS, and ispDS+.
Type: Logic Primitive
Macro Port Definition:
NAND2 (ZN0,A0,A1);NAND3 (ZN0,[A0..A2]);NAND4 (ZN0,[A0..A3]);...NAND12 (ZN0,[A0..A11]);NAND16 (ZN0,[A0..A15]);
Truth Table:
The truth table is the same for all NANDs.
Input Output
All inputs high LowOne or more inputs low High
NAND2
NAND3
. . .
NAND16
Macro Library Reference Manual 330
NOR2 Through NOR12 & NOR16
Function: 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 16 input NOR gates.
Availability: NOR2, NOR3, NOR4, NOR5, NOR6, NOR7,NOR8, NOR9, NOR10, NOR11, NOR12, and NOR16 are forpDS, ispDS, and ispDS+.
Type: Logic Primitive
Macro Port Definition:
NOR2 (ZN0,A0,A1);NOR3 (ZN0,[A0..A2]);NOR4 (ZN0,[A0..A3]);...NOR12 (ZN0,[A0..A11]);NOR16 (ZN0,[A0..A15]);
Truth Table:
The truth table is the same for all NORs.
Input Output
All inputs low HighOne or more inputs high Low
NOR2
NOR3
NOR16
. . .
Macro Library Reference Manual 331
OR2 Through OR12 and OR16
Function: 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 16 input OR gates.
Availability: OR2, OR3, OR4, OR5, OR6, OR7, OR8, OR9,OR10, OR11, OR12, and OR16 are for pDS, ispDS, and ispDS+.
Type: Logic Primitive
Macro Port Definition:
OR2 (Z0,A0,A1);OR3 (Z0,[A0..A2]);OR4 (Z0,[A0..A3]);...OR12 (Z0,[A0..A11]);OR16 (Z0,[A0..A15]);
Truth Table:
The truth table is the same for all ORs.
Input Output
All inputs low LowOne or more inputs high High
OR2
OR3
OR16
. . .
Macro Library Reference Manual 332
XNOR2, XNOR3, XNOR4, XNOR7, XNOR8,and XNOR9
Function: 2, 3, 4, 7, 8, and 9 input XNOR gates.
Availability: XNOR2, NOR3, NOR4, XNOR7, XNOR8, andXNOR9, are for pDS, ispDS, and ispDS+.
Type:
Logic Primitive: XNOR2, XNOR3, XNOR4.Soft: XNOR9.Hard: XNOR7, XNOR8.
Logic Resources – pDS:
* ZN0: 2 PT B0: 16 PT
Macro Port Definition:
XNOR2 (ZN0,A0,A1);XNOR3 (ZN0,[A0..A2]);XNOR4 (ZN0,[A0..A3]);XNOR7 (ZN0,[A0..A6]);XNOR8 (ZN0,[A0..A7]);XNOR9 (ZN0,[A0..A8]);
XNOR9_1 (B0,[A0..A7]);XNOR9_2 (ZN0,B0,A8);
Truth Table:
The truth table is the same for all XNORs.
Macro PT GLB Output Level
XNOR2 2 .25 1 1XNOR3 4 .25 1 1XNOR4 8 .5 1 1XNOR7 12 0.75 1 1XNOR8 16 1 1 1XNOR9 * 1.25 2 2
Input Output
All inputs low HighOdd number of inputs high LowEven number of inputs high High
XNOR2
XNOR3
XNOR4
XNOR8
XNOR9
XNOR7
Macro Library Reference Manual 333
XOR2, LXOR2, XOR3, XOR4, XOR8, and XOR9
Function: 2, 3, 4, 8, and 9 input XOR gates.
Availability: LXOR2 is for ispDS and ispDS+. XOR2, XOR3,XOR4, XOR8, and XOR9, are for pDS, ispDS, and ispDS+.
Type:
Logic Primitive: XOR2, XOR3, XOR4.Soft: XOR9.Hard: XOR8.Physical (in the silicon):LXOR2.
LXOR2 specifies the use of the physical XOR2 gate in the GLB. It isequivalent to $$ notation in pDS. See the Lattice SemiconductorData Book for more information.
Logic Resources:
* Z0: 2 PT B0: 16 PTLXOR2: depends on usage.
Boolean Equation:
XOR2 (Z0,A0,A1);LXOR2 (Z0,A0,A1);XOR3 (Z0,[A0..A2]);XOR4 (Z0,[A0..A3]);XOR8 (Z0,[A0..A7]);XOR9 (Z0,[A0..A8]);
XOR9_1 (B0,[A0..A7]);XOR9_2 ([Z0,B0,A8);
Truth Table:
The truth table is the same for all XNORs.
Macro PT GLB Output Level
XOR2 2 .25 1 1XOR3 4 .25 1 1XOR4 8 .5 1 1XOR8 16 1 1 1XOR9 * 1.25 2 2
Input Output
All inputs low HighOdd number of inputs high LowEven number of inputs high High
XOR2
XOR3
XOR4
XOR8
XOR9
LXOR2
LX2
Macro Library Reference Manual 334
MUX/DMUX
This chapter contains information on the following macros:
■ Multiplexers
■ Demultiplexers
Macro Library Reference Manual 335
Multiplexers
MUX2 and MUX2E
Function:
MUX2: 1 of 2 input mux.MUX2E: 1 of 2 input mux with enable.
Availability: MUX2 and MUX2E are for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
MUX2 (Z0,A0,A1,S0);MUX2E (Z0,A0,A1,EN,S0);
Truth Table:
Gray areas (EN) apply only to MUX2E.
A0..An-1 = inputs, x = don’t care.
Macro PT GLB Output Level
MUX2 2 .25 1 1MUX2E 2 .25 1 1
Input Output
EN S0 Z0
1 0 A01 1 A10 x 0
Z0
S0
A1
A0
Z0
S0
EN
A1
A0
MUX2
MUX2E
Macro Library Reference Manual 336
MUX4 and MUX4E
Function:
MUX4: 1 of 4 input mux.MUX4E: 1 of 4 input mux with enable.
Availability: MUX4 and MUX4E are for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
MUX4 (Z0,[A0..A3],S0,S1);MUX4E (Z0,[A0..A3],EN,S0,S1);
Truth Table:
Gray areas (EN) apply only to MUX4E.
A0..An-1 = inputs, x = don’t care.
Macro PT GLBs Outputs Levels
MUX4 4 .25 1 1MUX4E 4 .25 1 1
Input Output
EN S1 S0 Z0
1 0 0 A01 0 1 A11 1 0 A21 1 1 A30 x x 0
Z0
EN
S1
S0
A3
A2
A1
A0
MUX4
MUX4E
Z0
S1
S0
A3
A2
A1
A0
Macro Library Reference Manual 337
MUX8 and MUX8E
Function:
MUX8: 1 of 8 input mux.MUX8E: 1 of 8 input mux with enable.
Availability: MUX8 and MUX8E are for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
MUX8 (Z0,[A0..A7],[S0..S2]);MUX8E (Z0,[A0..A7],EN,[S0..S2]);
Truth Table:
Gray areas (EN) apply only to MUX8E.
A0..An-1 = inputs, x = don’t care.
Macro PT GLB Output Level
MUX8 8 .5 1 1MUX8E 8 .5 1 1
Input Output
EN S2 S1 S0 Z0
1 0 0 0 A01 0 0 1 A11 0 1 0 A21 0 1 1 A31 1 0 0 A41 1 0 1 A51 1 1 0 A61 1 1 1 A70 x x x 0
MUX8
MUX8E
Z0
S0
S2
S1
EN
A7
A6
A5A4
A3
A2
A1A0
Z0
S0
S2
S1
A7
A6
A5A4
A3
A2
A1A0
Macro Library Reference Manual 338
MUX16 and MUX16E
Function:
MUX16: One of 16 input mux for 3K device only.MUX16E: One of 16 input mux with enable for 3K device only.
Availability: MUX16 and MUX16E are for pDS, ispDS, andispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
MUX16 (Z0,[A0..A15],[S0..S3]);MUX16E (Z0,[A0..A15],EN,[S0..S3]);
Macro PT GLB Output Level
MUX16 16 1 1 1MUX16E 16 1 1 1
MUX16 MUX16E
A5
A1
A0
A3
A2
A4
Z0
A7
A6
A13
A9
A8
A11
A10
A12
A15
A14
S1
S0
S3
S2
A5
A1
A0
A3
A2
A4
Z0
A7
A6
A13
A9
A8
A11
A10
A12
A15
A14
S1
S0
S3
S2
EN
Macro Library Reference Manual 339
Truth Table:
Gray areas (EN) apply only to MUX16E.
A0..An-1 = inputs, x = don’t care.
Input Output
EN S3 S2 S1 S0 Z0
1 0 0 0 0 A01 0 0 0 1 A11 0 0 1 0 A21 0 0 1 1 A31 0 1 0 0 A41 0 1 0 1 A51 0 1 1 0 A61 0 1 1 1 A71 1 0 0 0 A81 1 0 0 1 A91 1 0 1 0 A101 1 0 1 1 A111 1 1 0 0 A121 1 1 0 1 A131 1 1 1 0 A141 1 1 1 1 A150 x x x x 0
Macro Library Reference Manual 340
S3
A15
A14
A13
A12
A11
A10
A9
S1
S0
S2
A0
A1
A2
A3
A4
A5
A6
Z0
A7
A8
MUX16
Macro Library Reference Manual 341
Z0
A7
A6
A5
A4
A3
A2
A1
A0
A8
A9
A10
A11
A12
A13
A14
MUX16E
Macro Library Reference Manual 342
MUX22 and MUX22E
Function:
MUX22: Dual 1 of 2 input mux with common select line.MUX22E: Dual 1 of 2 input mux with common select line and
enable.
Availability: MUX22 and MUX22E are for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
MUX22 (Z0,Z1,A0,A1,B0,B1,S0);MUX22E (Z0,Z1,A0,A1,B0,B1,EN,S0);
Truth Table:
Gray areas (EN) apply only to MUX22E.
A0..An-1 = inputs, B0..Bn-1 = inputs,x = don’t care.
Macro PT GLB Output Level
MUX22 2/out .5 2 1MUX22E 2/out .5 2 1
Input Output
EN S0 Z0 Z1
1 0 A0 A11 1 B0 B10 x 0 0
MUX22
MUX22E
B0
EN
S0
B1
A0
A1
Z1
Z0
B0
S0
B1
A0
A1
Z1
Z0
Macro Library Reference Manual 343
MUX24 and MUX24E
Function:
MUX24: Dual 1 of 4 input mux with common select line.MUX24E: Dual 1 of 4 input mux with common select line and
enable.
Availability: MUX24 and MUX24E are for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
MUX24 (Z0,Z1,A0,A1,B0,B1,C0,C1,D0,D1,S0,S1);MUX24E (Z0,Z1,A0,A1,B0,B1,C0,C1,D0,D1,EN,S0,S1);
Truth Table:
Gray areas (EN) apply only to MUX24E.
A0..An-1 = inputs, B0..Bn-1 = inputs,x = don’t care.
Macro PT GLB Output Level
MUX24 4/out .5 2 1MUX24E 4/out .5 2 1
Input Output
EN S1 S0 Z0 Z1
1 0 0 A0 A11 0 1 B0 B11 1 0 C0 C11 1 1 D0 D10 x x 0 0
MUX24
MUX24E
Z0Z1
S0
A0A1
B0B1
C0C1
D0D1
EN
S1
Z0Z1
S0
A0A1
B0B1
C0C1
D0D1
S1
Macro Library Reference Manual 344
MUX42 and MUX42E
Function:
MUX42: Quad 1 of 2 input mux with common select line.MUX42E: Quad 1 of 2 input mux with common select line and
enable.
Availability: MUX42 and MUX42E are for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
MUX42 ([Z0..Z3],[A0..A3],[B0..B3],S0);MUX42E ([Z0..Z3],[A0..A3],[B0..B3],EN,S0);
Truth Table:
Gray areas (EN) apply only to MUX42E.
A0..An-1 = inputs, B0..Bn-1 = inputs,x = don’t care.
Macro PT GLB Output Level
MUX42 2/out 1 4 1MUX42E 2/out 1 4 1
Input Output
EN S0 Z0 Z1 Z2 Z3
1 0 A0 A1 A2 A31 1 B0 B1 B2 B30 x 0 0 0 0
MUX24
MUX24E
Z0Z1
S0
A0A1
B0B1
C0C1
D0D1
EN
S1
Z0Z1
S0
A0A1
B0B1
C0C1
D0D1
S1
Macro Library Reference Manual 345
MUX44 and MUX44E
Function:
MUX44: Quad 1 of 4 input mux with common select line.MUX44E: Quad 1 of 4 input mux with common select line and
enable.
Availability: MUX44 and MUX44E are for pDS, ispDS,and ispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
MUX44 ([Z0..Z3],[A0..A3],[B0..B3],[C0..C3],[D0..D3],S0,S1);
MUX44_1 (Z0,Z1,A0,A1,B0,B1,C0,C1, D0,D1,S0,S1);MUX44_2 (Z2,Z3,A2,A3,B2,B3,C2,C3,
D2,D3,S0,S1);MUX44E ([Z0..Z3],[A0..A3],[B0..B3],
[C0..C3],[D0..D3],EN,S0,S1);MUX44E_1 (Z0,Z1,A0,A1,B0,B1,C0,C1, D0,D1,EN,S0,S1);MUX44E_2 (Z2,Z3,A2,A3,B2,C3,C2,C3,
D2,D3,EN,S0,S1);
Truth Table:
Gray areas (EN) apply only to MUX44E.
A0..An-1 = inputs, B0..Bn-1 = inputs, x = don’t care,C0..Cn-1 = inputs, D0..Dn-1 = inputs.
Macro PT GLB Output Level
MUX44 4/out 2 4 1MUX44E 4/out 2 4 1
Input Output
EN S1 S0 Z0 Z1 Z2 Z3
1 0 0 A0 A1 A2 A31 0 1 B0 B1 B2 B31 1 0 C0 C1 C2 C31 1 1 D0 D1 D2 D30 x x 0 0 0 0
MUX44 MUX44E
Z0
Z1
Z2
Z3
EN
S1
A0
A1
A2
A3
B0
B1
B2
B3
S0
D3
D2
C3
C2
C1
C0
D1
D0
Z0
Z1
Z2
Z3
S1
A0
A1
A2
A3
B0
B1
B2
B3
S0
D3
D2
C3
C2
C1
C0
D1
D0
Macro Library Reference Manual 346
S0
D3
A2
A3
C3
B3
B0
C0
Z0
A0
A1
A2
A3
S0
S1
MUX4
Z0
A0
A1
A2
A3
S0
S1
MUX4
D2
S1
Z3
Z2
Z0
Z1D1
C1
B1
A1
A0
D0
Z0
A0
A1
A2
A3
S0
S1
MUX4
Z0
A0
A1
A2
A3
S0
S1
MUX4
B2
C2
MUX44A
Macro Library Reference Manual 347
Z3
Z2
Z1
Z0
A0
B0
C0
D0
A1
B1
C1
D1
A2
B2
C2
D2
A3
B3
C3
D3
EN
S0
S1
Z0
EN
S1
S0
A3
A2
A1
A0
MUX4E
Z0
EN
S1
S0
A3
A2
A1
A0
MUX4E
Z0
EN
S1
S0
A3
A2
A1
A0
MUX4E
Z0
EN
S1
S0
A3
A2
A1
A0
MUX4E
MUX44AE
Macro Library Reference Manual 348
MUX44A and MUX44AE
Function:
MUX44A: Quad 1 of 4 input mux with commonselect line for 3K device only.
MUX44AE: Quad 1 of 4 input mux with commonselect line and enable for 3K device only.
Availability: MUX44A and MUX44AE are for pDS, ispDS,and ispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
MUX44A ([Z0..Z3],[A0..A3],[B0..B3],[C0..C3],[D0..D3],S0,S1);
MUX44AE ([Z0..Z3],[A0..A3],[B0..B3],[C0..C3],[D0..D3],EN,S0,S1);
Truth Table:
Gray areas (EN) apply only to MUX44AE.
A0..An-1 = inputs, B0..Bn-1 = inputs, x = don’t care,C0..Cn-1 = inputs, D0..Dn-1 = inputs.
Macro PT GLB Output Level
MUX44A 4/out 1 4 1MUX44AE 4/out 1 4 1
Input Output
EN S1 S0 Z0 Z1 Z2 Z3
1 0 0 A0 A1 A2 A31 0 1 B0 B1 B2 B31 1 0 C0 C1 C2 C31 1 1 D0 D1 D2 D30 x x 0 0 0 0
MUX44A MUX44AE
Z0
Z1
Z2
Z3
EN
S1
A0
A1
A2
A3
B0
B1
B2
B3
S0
D3
D2
C3
C2
C1
C0
D1
D0
Z0
Z1
Z2
Z3
S1
A0
A1
A2
A3
B0
B1
B2
B3
S0
D3
D2
C3
C2
C1
C0
D1
D0
Macro Library Reference Manual 349
MUX82 and MUX82E
Function:
MUX82: Octal 1 of 2 input mux with common select line.MUX82E: Octal 1 of 2 input mux with common select line and
enable.
Availability: MUX82 and MUX82E are for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
MUX82 ([Z0..Z7],[A0..A7],[B0..B7],S0);MUX82_1 ([Z0..Z3],[A0..A3],[B0..B3],S0);MUX82_2 ([Z4..Z7],[A4..A7],[B4..B7],S0);
MUX82E ([Z0..Z7],[A0..A7],[B0..B7],EN,S0);MUX82E_1 ([Z0..Z3],[A0..A3],[B0..B3],EN,S0);MUX82E_2 ([Z4..Z7],[A4..A7],[B4..B7],EN,S0);
Truth Table:
Gray areas (EN) apply only to MUX82E.
A0..An-1 = inputs, B0..Bn-1 = inputs, x = don’t care.
Macro PT GLB Output Level
MUX82 2/out 2 8 1MUX82E 2/out 2 8 1
Input Output
EN S0 Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z7
1 0 A0 A1 A2 A3 A4 A5 A6 A71 1 B0 B1 B2 B3 B4 B5 B6 B70 x 0 0 0 0 0 0 0 0
MUX82
MUX82E
Z0Z1Z2Z3Z4Z5Z6Z7
A4A5A6A7
B0B1B2B3B4B5B6B7
A0A1A2A3
ENS0
Z0Z1Z2Z3Z4Z5Z6Z7
A4A5A6A7
B0B1B2B3B4B5B6B7
A0A1A2A3
S0
Macro Library Reference Manual 350
Demultiplexers
DMUX2 and DMUX2E
Function:
DMUX2: 1 of 2 output demux.DMUX2E: 1 of 2 output demux with enable.
Availability: DMUX2 and DMUX2E are for pDS, ispDS, andispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
DMUX2 (Z0,Z1,A0,S0);DMUX2E Z0,Z1,A0,EN,S0);
Truth Table:
Gray areas (EN) apply only to DMUX2E.
A0..An-1 = inputs, x = don’t care.
Macro PT GLB Output Level
DMUX2 1/out .5 2 1DMUX2E 1/out .5 2 1
Input Output
EN S0 Z0 Z1
1 0 A0 01 1 0 A00 x 0 0
Z1
Z0A0
EN
S0
DMUX2
DMUX2E
Z1
Z0A0
S0
Macro Library Reference Manual 351
DMUX4 and DMUX4E
Function:
DMUX4: 1 of 4 output demux.DMUX4E: 1 of 4 output demux with enable.
Availability: DMUX4 and DMUX4E are for pDS, ispDS, andispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
DMUX4 ([Z0..Z3],A0,S0,S1);DMUX4E ([Z0..Z3],A0,EN,S0,S1);
Truth Table:
Gray areas (EN) apply only to DMUX4E.
A0..An-1 = inputs, x = don’t care.
Macro PT GLB Output Level
DMUX4 1/out 1 4 1DMUX4E 1/out 1 4 1
Input Output
EN S1 S0 Z0 Z1 Z2 Z3
1 0 0 A0 0 0 01 0 1 0 A0 0 01 1 0 0 0 A0 01 1 1 0 0 0 A00 x x 0 0 0 0
DMUX4
DMUX4E
Z3
Z2
Z1
Z0A0
EN
S0
S1
Z3
Z2
Z1
Z0A0
S0
S1
Macro Library Reference Manual 352
DMUX22 and DMUX22E
Function:
DMUX22: Dual 1 of 2 output demux with common select line.DMUX22E: Dual 1 of 2 output demux with common select line
and enable.
Availability: DMUX22 and DMUX22E are for pDS, ispDS, andispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
DMUX22 (Y0,Y1,Z0,Z1,A0,A1,S0);DMUX22E (Y0,Y1,Z0,Z1,A0,A1,EN,S0);
Truth Table:
Gray areas (EN) apply only to DMUX22E.
A0..An-1 = inputs, x = don’t care.
Macro PT GLB Output Level
DMUX22 1/out 1 4 1DMUX22E 1/out 1 4 1
Input Output
EN S0 Y0 Y1 Z0 Z1
1 0 A0 A1 0 01 1 0 0 A0 A10 x 0 0 0 0
DMUX22
DMUX22E
S0
A0
EN
A1 Y1
Y0
Z0
Z1
S0
A0
A1 Y1
Y0
Z0
Z1
Macro Library Reference Manual 353
DMUX24 and DMUX24E
Function:
DMUX24: Dual 1 of 4 output demux with common select line.DMUX24E: Dual 1 of 4 output demux with common select line
and enable.
Availability: DMUX24 and DMUX24E are for pDS, ispDS, andispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
DMUX24 (W0,W1,X0,X1,Y0,Y1,Z0,Z1,A0,A1,S0,S1);DMUX24_1 (W0,X0,Y0,Z0,A0,S0,S1);DMUX24_2 (W1,X1,Y1,Z1,A1,S0,S1);
DMUX24E (W0,W1,X0,X1,Y0,Y1,Z0,Z1,A0,A1,EN,S0,S1);DMUX24E_1 (W0,X0,Y0,Z0,A0,EN,S0,S1);DMUX24E_2 (W1,X1,Y1,Z1,A1,EN,S0,S1);
Truth Table:
Gray areas (EN) apply only to DMUX24E.
A0..An-1 = inputs, x = don’t care.
Macro PT GLB Output Level
DMUX24 1/out 2 8 1DMUX24E 1/out 2 8 1
Input Output
EN S1 S0 W0 W1 X0 X1 Y0 Y1 Z0 Z1
1 0 0 A0 A1 0 0 0 0 0 01 0 1 0 0 A0 A1 0 0 0 01 1 0 0 0 0 0 A0 A1 0 01 1 1 0 0 0 0 0 0 A0 A1
x 0 0 0 0 0 0 0 0
DMUX24
DMUX24E
Z1
Z0
Y0
Y1
A0
A1
EN
S0
X1
X0
W1
W0
S1
Z1
Z0
Y0
Y1
A0
A1
S0
X1
X0
W1
W0
S1
Macro Library Reference Manual 354
DMUX42 and DMUX42E
Function:
DMUX42: Quad 1 of 2 output demux with common select line.DMUX42E: Quad 1 of 2 output demux with common select line
and enable.
Availability: DMUX42 and DMUX42E are for pDS, ispDS, andispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
DMUX42 ([Y0..Y3],[Z0..Z3],[A0..A3],S0);DMUX42_1 (Y0,Y1,Z0,Z1,A0,A1,S0);DMUX42_2 (Y2,Y3,Z2,Z3,A2,A3,S0);
DMUX42E ([Y0..Y3],[Z0..Z3],[A0..A3],EN,S0);DMUX42E_1 (Y0,Y1,Z0,Z1,A0,A1,EN,S0);DMUX42E_2 (Y2,Y3,Z2,Z3,A2,A3,EN,S0);
Truth Table:
Gray areas (EN) apply only to DMUX42E.
A0..An-1 = inputs, x = don’t care.
Macro PT GLB Output Level
DMUX42 1/out 2 8 1DMUX42E 1/out 2 8 1
Input Output
EN S0 Y0 Y1 Y2 Y3 Z0 Z1 Z2 Z3
1 0 A0 A1 A2 A3 0 0 0 01 1 0 0 0 0 A0 A1 A2 A30 x 0 0 0 0 0 0 0 0
DMUX42
DMUX42E
S0
EN
A0
A1
Z3
Z2
Z1
Z0
Y3
Y2
Y1
Y0
A3
A2
S0
A0
A1
Z3
Z2
Z1
Z0
Y3
Y2
Y1
Y0
A3
A2
Macro Library Reference Manual 355
DMUX44 and DMUX44E
Function:
DMUX44: Quad 1 of 4 output demux with common select line.DMUX44E: Quad 1 of 4 output demux with common select line
enable.
Availability: DMUX44 and DMUX44E are for pDS, ispDS, andispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
DMUX44 ([W0..W3],[X0..X3],[Y0..Y3], [Z0..Z3],[A0..A3],S0,S1);DMUX44_1 (W0,X0,Y0,Z0,A0,S0,S1);DMUX44_2 (W1,X1,Y1,Z1,A1,S0,S1);DMUX44_3 (W2,X2,Y2,Z2,A2,S0,S1);DMUX44_4 (W3,X3,Y3,Z3,A3,S0,S1);
DMUX44E ([W0..W3],[X0..X3],[Y0..Y3],[Z0..Z3],[A0..A3],EN,S0,S1);DMUX44E_1 (W0,X0,Y0,Z0,A0,EN,S0,S1);DMUX44E_2 (W1,X1,Y1,Z1,A1,EN,S0,S1);DMUX44E_3 (W2,X2,Y2,Z2,A2,EN,S0,S1);DMUX44E_4 (W3,X3,Y3,Z3,A3,EN,S0,S1);
Truth Table:
Gray areas (EN) apply only to DMUX44E.
A0..An-1 = inputs, x = don’t care.
Macro PT GLB Output Level
DMUX44 1/out 4 16 1DMUX44E 1/out 4 16 1
Input Output
EN S1 S0 W0 W1 W2 W3 X0 X1 X2 X3 Y0 Y1 Y2 Y3 Z0 Z1 Z2 Z3
1 0 0 A0 A1 A2 A3 0 0 0 0 0 0 0 0 0 0 0 01 0 1 0 0 0 0 A0 A1 A2 A3 0 0 0 0 0 0 0 01 1 0 0 0 0 0 0 0 0 0 A0 A1 A2 A3 0 0 0 01 1 1 0 0 0 0 0 0 0 0 0 0 0 0 A0 A1 A2 A30 x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMUX44 DMUX44E
EN
Z3
Z2
Z1
Z0
Y3
Y2
Y1
Y0
A0
A1
A2
A3
S1
S0
X3
X2
X1
X0
W3
W2
W1
W0
Z3
Z2
Z1
Z0
Y3
Y2
Y1
Y0
A0
A1
A2
A3
S1
S0
X3
X2
X1
X0
W3
W2
W1
W0
Macro Library Reference Manual 356
DMUX82 & DMUX82E
Function:
DMUX82: Octal 1 of 2 output demux with common select line.DMUX82E: Octal 1 of 2 output demux with common select line
and enable.
Availability: DMUX82 and DMUX82E are for pDS, ispDS, andispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
DMUX82 ([Y0..Y7],[Z0..Z7],[A0..A7],S0);DMUX82_1 (Y0,Y1,Z0,Z1,A0,A1,S0);DMUX82_2 (Y2,Y3,Z2,Z3,A2,A3,S0);DMUX82_3 (Y4,Y5,Z4,Z5,A4,A5,S0);DMUX82_4 (Y6,Y7,Z6,Z7,A6,A7,S0);
DMUX82E ([Y0..Y7],[Z0..Z7],[A0..A7],EN,S0);DMUX82E_1 (Y0,Y1,Z0,Z1,A0,A1,EN,S0);DMUX82E_2 (Y2,Y3,Z2,Z3,A2,A3,EN,S0);DMUX82E_3 (Y4,Y5,Z4,Z5,A4,A5,EN,S0);DMUX82E_4 (Y6,Y7,Z6,Z7,A6,A7,EN,S0);
Truth Table:
Gray areas (EN) apply only to DMUX82E.
A0..An-1 = inputs, x = don’t care.
Macro PT GLB Output Level
DMUX82 1/out 4 16 1DMUX82E 1/out 4 16 1
Input Output
EN S0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z7
1 0 A0 A1 A2 A3 A4 A5 A6 A7 0 0 0 0 0 0 0 01 1 0 0 0 0 0 0 0 0 A0 A1 A2 A3 A4 A5 A6 A70 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMUX82 DMUX82E
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Z0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
A4
A5
A6
A7
A3
A2
A1
A0
EN
S0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Z0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
A4
A5
A6
A7
A3
A2
A1
A0
S0
Macro Library Reference Manual 357
Registers
This chapter contains information on the following macros:
■ D Flip-Flops
■ JK Flip-Flops
■ Toggle Flip-Flops
■ D Latches
■ SR Latches
■ Shift Registers
Macro Library Reference Manual 358
D Flip-flops
FD11, FD14, and FD18
Function:
FD11: 1-bit D flip-flop.FD14: 4-bit D flip-flop.FD18: 8-bit D flip-flop.
Availability: FD11 and FD14 are for pDS, ispDS, and ispDS+. FD18is for ispDS and ispDS+.
Type:
Logic Primitive: FD11Soft: FD14 and FD18
Logic Resources:
* Add 1 PT per GLB if Product Term Clock is used.
Boolean Equation:
FD11 (Q0,D0,CLK);FD14 ([Q0..Q3],[D0..D3],CLK);FD18 ([Q0..Q7],[D0..D7],CLK);
Truth Table:
d = any pattern of 1s and 0s in an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch,x = don’t care, ↑ = rising clock edge.
Macro PT GLB Output Level
FD11 1* .25 1 1FD14 1/out* 1 4 1FD18 1/out* 2 8 1
Input Output
D0~Dn-1 CLK Q0~Qn-1
d ↑ dx 0 Q0’~Qn’x 1 Q0’~Qn’
FD11
FD18
D Q
FD14
Q3
Q2
Q1
Q0D0
D1
D2
D3
Q3
Q2
Q1
Q0D0
D1
D2
D3
D7
D6
D5
D4 Q4
Q5
Q6
Q7
Macro Library Reference Manual 359
FD21, FD24, and FD28
Function:
FD21: 1-bit D flip-flop with asynchronous clear.FD24: 4-bit D flip-flop with asynchronous clear.FD28: 8-bit D flip-flop with asynchronous clear.
Availability: FD21 and FD24 are for pDS, ispDS, and ispDS+. FD28is for ispDS and ispDS+.
Type:
Logic Primitive: FD21Soft: FD24 and FD28
Logic Resources:
* Add 1 PT per GLB for CD and 1 per GLB if Product TermClock is used.
Boolean Equation:
FD21 (Q0,D0,CLK,CD);FD24 ([Q0..Q3],[D0..D3],CLK,CD);FD28 ([Q0..Q7],[D0..D7],CLK,CD);
Truth Table:
d = any pattern of 1s and 0s in an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Macro PT GLB Output Level
FD21 1* .25 1 1FD24 1/out* 1 4 1FD28 1/out* 2 8 1
Input Output
CD D0~Dn-1 CLK Q0~Qn-1
1 x x 00 d ↑ d0 x 0 Q0’~Qn’0 x 1 Q0’~Qn’
FD21
FD28
D Q
FD24
Q3
Q2
Q1
Q0D0
D1
D2
D3
Q3
Q2
Q1
Q0D0
D1
D2
D3
D7
D6
D5
D4 Q4
Q5
Q6
Q7
CD
CD
CD
Macro Library Reference Manual 360
FD31, FD34, and FD38
Function:
FD31: 1-bit D flip-flop with synchronous preset.FD34: 4-bit D flip-flop with synchronous preset.FD38: 8-bit D flip-flop with synchronous preset.
Availability: FD31 and FD34 are for pDS, ispDS, and ispDS+. FD38is for ispDS and ispDS+.
Type: Soft
Logic Resources:
* Add 1 PT per GLB if Product Term Clock is used.
Boolean Equation:
FD31 (Q0,D0,CLK,PS);FD34 ([Q0..Q3],[D0..D3],CLK,PS);FD38 ([Q0..Q7],[D0..D7],CLK,PS);
Truth Table:
d = any pattern of 1s and 0s in an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch,x = don’t care, ↑ = rising clock edge.
Macro PT GLB Output Level
FD31 1* .25 1 1FD34 1/out* 1 4 1FD38 2/out* 2 8 1
Input Output
PS D0~Dn-1 CLK Q0~Qn-1
1 x ↑ 10 d ↑ dx x 0 Q0’~Qn’x x 1 Q0’~Qn’
FD31
FD38
D Q
FD34
Q3
Q2
Q1
Q0D0
D1
D2
D3
D7
D6
D5
D4 Q4
Q5
Q6
Q7
PS
PS
PS
Q3
Q2
Q1
Q0D0
D1
D2
D3
Macro Library Reference Manual 361
FD41, FD44, and FD48
Function:
FD41: 1-bit D flip-flop with asynchronous clear dominant oversynchronous preset.
FD44: 4-bit D flip-flop with asynchronous clear dominant oversynchronous preset.
FD48: 8-bit D flip-flop with asynchronous clear dominant oversynchronous preset.
Availability: FD41 and FD44 are for pDS, ispDS, and ispDS+. FD48is for ispDS and ispDS+.
Type: Soft
Logic Resources:
* Add 1 PT per GLB for CD and 1 per GLB if Product TermClock is used.
Boolean Equation:
FD41 (Q0,D0,CLK,PS,CD);FD44 ([Q0..Q3],[D0..D3],CLK,PS,CD);FD48 ([Q0..Q7],[D0..D7],CLK,PS,CD);
Truth Table:
d = any pattern of 1s and 0s in an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch,x = don’t care, ↑ = rising clock edge.
Macro PT GLB Output Level
FD41 1* .25 1 1FD44 1/out* 1 4 1FD48 2/out* 2 8 1
Input Output
CD PS D0~Dn-1 CLK Q0~Qn-1
1 x x x 00 1 x ↑ 10 0 d ↑ d0 x x 0 Q0’~Qn’0 x x 1 Q0’~Qn’
FD41
FD48
D Q
FD44
Q3
Q2
Q1
Q0D0
D1
D2
D3
D7
D6
D5
D4 Q4
Q5
Q6
Q7
PS
PS
PS
Q3
Q2
Q1
Q0D0
D1
D2
D3
CD
CD
CD
Macro Library Reference Manual 362
FD51, FD54, and FD58
Function:
FD51: 1-bit D flip-flop with synchronous preset dominant oversynchronous clear.
FD54: 4-bit D flip-flop with synchronous preset dominant oversynchronous clear.
FD58: 8-bit D flip-flop with synchronous preset dominant oversynchronous clear.
Availability: FD51 and FD54 are for pDS, ispDS, and ispDS+. FD58is for ispDS and ispDS+.
Type: Soft
Logic Resources:
* Add 1 p-term per GLB for the clock if Product Term Clockis used.
Boolean Equation:
FD51 (Q0,D0,CLK,PS,CS);FD54 ([Q0..Q3],[D0..D3],CLK,PS,CS);FD58 ([Q0..Q7],[D0..D7],CLK,PS,CS);
Truth Table:
d = any pattern of 1s and 0s in an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch,x = don’t care, ↑ = rising clock edge.
Macro PT GLB Output Level
FD51 2* .25 1 1FD54 2/out* 1 4 1FD58 2/out* 2 8 1
Input Output
PS CS D0~Dn-1 CLK Q0~Qn-1
1 x x ↑ 10 1 x ↑ 00 0 d ↑ dx x x 0 Q0’~Qn’x x x 1 Q0’~Qn’
FD51
FD58
D Q
FD54
Q3
Q2
Q1
Q0D0
D1
D2
D3
D7
D6
D5
D4 Q4
Q5
Q6
Q7
PS
PS
PS
Q3
Q2
Q1
Q0D0
D1
D2
D3
CS
CS
CS
Macro Library Reference Manual 363
FD61, FD64, and FD68
Function:
FD61: 1-bit D flip-flop with scan.FD64: 4-bit D flip-flop with scan.FD68: 8-bit D flip-flop with scan.
Availability: FD61, FD64, and FD68 are for ispDS and ispDS+.
Type: Soft
Logic Resources – ispDS+:
* Add 1 PT per GLB if Product Term Clock is used.
Boolean Equation for ispDS+:
FD61 (Q0,D0,TI0,CLK,TE);FD64 ([Q0..Q3],[D0..D3],[TI0..TI3],CLK,TE);FD68 ([Q0..Q7],[D0..D7],[TI0..TI7],CLK,TE);
Truth Table:
d = any pattern of 1s and 0s in an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch,x = don’t care, ↑ = rising clock edge.
Macro PT GLB Output Level
FD61 2* .25 1 1FD64 2/out* 1 4 1FD68 2/out* 2 8 1
Input Output
TE TI0~TIn-1 D0~Dn-1 CLK Q0~Qn-1
0 x d ↑ d1 d x ↑ dx x x 0 Q0’~Qn’x x x 1 Q0’~Qn’
TI0
Q4
Q5
Q6
Q7
D4
D5
D6
D7
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TI1
TI2
TI3
TI4
TI5
TI6
TI7
TE
TE
TI3
TI2
TI1
TI0
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TIQD
TE
FD61
FD68
FD64
Macro Library Reference Manual 364
FD71, FD74, and FD78
Function:
FD71: 1-bit D flip-flop with scan and asynchronous clear.FD74: 4-bit D flip-flop with scan and asynchronous clear.FD78: 8-bit D flip-flop with scan and asynchronous clear.
Availability: FD71, FD74, and FD78 are for ispDS and ispDS+.
Type: Soft
Logic Resources – ispDS+:
* Add 1 PT per GLB for CD and 1 per GLB if Product TermClock is used.
Boolean Equation for ispDS+:
FD71 (Q0,D0,TI0,CLK,CD,TE);FD74 ([Q0..Q3],[D0..D3],[TI0..TI3],CLK,CD,TE);FD78 ([Q0..Q7],[D0..D7],[TI0..TI7],CLK,CD,TE);
Truth Table:
d = any pattern of 1s and 0s in an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Macro PT GLB Output Level
FD71 2* .25 1 1FD74 2/out* 1 4 1FD78 2/out* 2 8 1
Input Output
CD TE TI0~TIn-1 D0~Dn-1 CLK Q0~Qn-1
1 x x x x 00 0 x d ↑ d0 1 d x ↑ d0 x x x 0 Q0’~Qn’0 x x x 1 Q0’~Qn’
TI0
Q4
Q5
Q6
Q7
D4
D5
D6
D7
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TI1
TI2
TI3
TI4
TI5
TI6
TI7
TE
TE
TI3
TI2
TI1
TI0
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TIQD
TE
FD71
FD78
FD74
CD
CD
CD
Macro Library Reference Manual 365
FD81, FD84, and FD88
Function:
FD81: 1-bit D flip-flop with scan and synchronous preset.FD84: 4-bit D flip-flop with scan and synchronous preset.FD88: 8-bit D flip-flop with scan and synchronous preset.
Availability: FD81, FD84, and FD88 are for ispDS and ispDS+.
Type: Soft
Logic Resources – ispDS+:
* Add 1 PT per GLB if Product Term Clock is used.
Boolean Equation for ispDS+:
FD81 (Q0,D0,TI0,CLK,PS,TE);FD84 ([Q0..Q3],[D0..D3],[TI0..TI3],CLK,PS,TE);FD88 ([Q0..Q7],[D0..D7],[TI0..TI7],CLK,PS,TE);
Truth Table:
d = any pattern of 1s and 0s in an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Macro PT GLB Output Level
FD81 3* .25 1 1FD84 3/out* 1 4 1FD88 3/out* 2 8 1
Input Output
PS TE TI0~TIn-1 D0~Dn-1 CLK Q0~Qn-1
1 x x x ↑ 10 0 x d ↑ d0 1 d x ↑ dx x x x 0 Q0’~Qn’x x x x 1 Q0’~Qn’
TI0
Q4
Q5
Q6
Q7
D4
D5
D6
D7
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TI1
TI2
TI3
TI4
TI5
TI6
TI7
TE
TE
TI3
TI2
TI1
TI0
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TIQD
TE
FD81
FD88
FD84
PS
PS
PS
Macro Library Reference Manual 366
FD91, FD94, and FD98
Function:
FD91: 1-bit D flip-flop with scan and asynchronous cleardominant over synchronous preset.
FD94: 4-bit D flip-flop with scan and asynchronous cleardominant over synchronous preset.
FD98: 8-bit D flip-flop with scan and asynchronous cleardominant over synchronous preset.
Availability: FD91, FD94, and FD98 are for ispDS and ispDS+.
Type: Soft
Logic Resources – ispDS+:
* Add 1 PT per GLB for CD and 1 per GLB if Product TermClock is used.
Boolean Equation for ispDS+:
FD91 (Q0,D0,TI0,CLK,PS,CD,TE);FD94 ([Q0..Q3],[D0..D3],[TI0..TI3],CLK,PS,CD,TE);FD98 ([Q0..Q7],[D0..D7],[TI0..TI7],CLK,PS,CD,TE);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch,x = don’t care, ↑ = rising clock edge.
Macro PT GLB Output Level
FD91 3* .25 1 1FD94 3/out* 1 4 1FD98 3/out* 2 8 1
Input Output
CD PS TE TI0~TIn-1 D0~Dn-1 CLK Q0~Qn-1
1 x x x x x 00 1 x x x ↑ 10 0 0 x d ↑ d0 0 1 d x ↑ d0 x x x x 0 Q0’~Qn’0 x x x x 1 Q0’~Qn’
TI0
Q4
Q5
Q6
Q7
D4
D5
D6
D7
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TI1
TI2
TI3
TI4
TI5
TI6
TI7
TE
TE
TI3
TI2
TI1
TI0
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TIQD
TE
FD91
FD98
FD94
PS
PS
PS
CD
CD
CD
Macro Library Reference Manual 367
FDA1, FDA4, and FDA8
Function:
FDA1: 1-bit D flip-flop with scan and synchronous presetdominant over synchronous clear.
FDA4: 4-bit D flip-flop with scan and synchronous presetdominant over synchronous clear.
FDA8: 8-bit D flip-flop with scan and synchronous presetdominant over synchronous clear.
Availability: FDA1, FDA4, and FDA8 are for ispDS and ispDS+.
Type: Soft
Logic Resources – ispDS+:
* Add 1 PT per GLB if Product Term Clock is used.
Boolean Equation for ispDS+:
FDA1 (Q0,D0,TI0,CLK,PS,CS,TE);FDA4 ([Q0..Q3],[D0..D3],[TI0..TI3],CLK,PS,CS,TE);FDA8 ([Q0..Q7],[D0..D7],[TI0..TI7],CLK,PS,CS,TE);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch,x = don’t care, ↑ = rising clock edge.
Macro PT GLB Output Level
FDA1 3* .25 1 1FDA4 3/out* 1 4 1FDA8 3/out* 2 8 1
Input Output
PS CS TE TI0~TIn-1 D0~Dn-1 CLK Q0~Qn-1
1 x x x x ↑ 10 1 x x x ↑ 00 0 0 x d ↑ d0 0 1 d x ↑ dx x x x x 0 Q0’~Qn’x x x x x 1 Q0’~Qn’
TI0
Q4
Q5
Q6
Q7
D4
D5
D6
D7
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TI1
TI2
TI3
TI4
TI5
TI6
TI7
TE
TE
TI3
TI2
TI1
TI0
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TIQD
TE
FDA1
FDA8
FDA4
PS
PS
PS
CS
CS
CS
Macro Library Reference Manual 368
JK Flip-flops
FJK11 and FJK21
Function:
FJK11: JK flip-flop.FJK21: JK flip-flop with asynchronous clear.
Availability: FJK11 and FJK21 are for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
* Add 1 PT per GLB if Product Term Clock is used.** Add 1 PT per GLB for CD and 1PT per GLB if Product
Term Clock is used.
Macro Port Definition:
FJK11 (Q0,J0,K0,CLK);FJK21 (Q0,J0,K0,CLK,CD);
Truth Table:
Gray areas (CD) apply only to FJK21.
Q0’ = previous output of flip-flop or latch,Q0’ = inverse of Q0’, x = don’t care,↑ = rising clock edge.
Macro PT GLB Output Level
FJK11 2* .25 1 1FJK21 2** .25 1 1
Input Output
CD J0 K0 CLK CD
1 x x x 00 0 0 ↑ Q0’0 0 1 ↑ 00 1 0 ↑ 10 1 1 ↑ Q0’0 x x 0 Q0’0 x x 1 Q0’
FJK11
FJK21
J
K
Q
QJ
K
CD
Macro Library Reference Manual 369
FJK31 and FJK41
Function:
FJK31: JK flip-flop with scan.FJK41: JK flip-flop with scan and asynchronous clear.
Availability: FJK31 and FJK41 are for ispDS and ispDS+.
Type: Soft
Logic Resources – ispDS+:
* Add 1 PT per GLB if Product Term Clock is used.
Boolean Equation for ispDS+:
FJK31 (Q0,J0,K0,TI0,CLK,TE);FJK41 (Q0,J0,K0,TI0,CLK,CD,TE);
Truth Table:
Gray areas (CD) apply only to FJK41.
d = any pattern of 1s and 0s on an input or set of inputs,Q0’ = previous output of flip-flop or latch, Q0’ = inverse of Q0’,x = don’t care, ↑ = rising clock edge.
Macro PT GLB Output Level
FJK31 3* .25 1 1FJK41 4* .25 1 1
Input Output
CD TE TI0 J0 K0 CLK Q0
1 x x x x x 00 0 x 0 0 ↑ Q0’0 0 x 0 1 ↑ 00 0 x 1 0 ↑ 10 0 x 1 1 ↑ Q0’0 1 d x x ↑ d0 x x x x 0 Q0’0 x x x x 1 Q0’
J Q
K
TI
TE
J Q
K
TI
TE
FJK31
FJK41
CD
Macro Library Reference Manual 370
FJK51
Function:
JK flip-flop with asynchronous clear and synchronous preset.
Availability: FJK51 is for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
* Add 1 PT per GLB for CD and 1PT per GLB if ProductTerm Clock is used.
Macro Port Definition:
FJK51 (Q0,J0,K0,CLK,PS,CD);
Truth Table:
Q0’ = previous output of flip-flop or latch,Q0’ = inverse of Q0’, x = don’t care, ↑ = rising clock edge.
Macro PT GLB Output Level
FJK51 3* .25 1 1
Input Output
CD PS J0 K0 CLK Q0
1 x x x x 00 1 x x ↑ 10 0 0 0 ↑ Q0’0 0 0 1 ↑ 00 0 1 0 ↑ 10 0 1 1 ↑ Q0’0 x x x 0 Q0’0 x x x 1 Q0’
FJK51
CD
PS
K
QJ
Macro Library Reference Manual 371
Toggle Flip-flops
FT11 and FT21
Function:
FT11: Toggle flip-flop with asynchronous clear.FT21: Toggle flip-flop with synchronous clear and preset,
preset dominant.
Availability: FT11 and FT21 is for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
* Add 1 PT per GLB for CD and 1PT per GLB if ProductTerm Clock is used.
** Add 1 PT per GLB if Product Term Clock is used.
Macro Port Definition:
FT11 (Q0,D0,CLK,CD);FT21 (Q0,D0,CLK,PS,CS);
Truth Tables:
FT11: FT21:
Q0’ = previous output of flip-flop or latch,Q0’ = inverse of Q0’, x = don’t care,↑ = rising clock edge.
Macro PT GLB Output Level
FT11 2* .25 1 1FT21 3** .25 1 1
Input Output Input Output
CD D0 CLK Q PS CS D0 CLK Q
1 x x 0 1 x x ↑ 10 0 ↑ Q0’ 0 1 x ↑ 00 1 ↑ Q0’ 0 0 0 ↑ Q0’0 x 0 Q0’ 0 0 1 ↑ Q0’0 x 1 Q0’ x x x 0 Q0’
x x x 1 Q0’
FT11
FT21
QD
CD
Q
CS
PSD
Macro Library Reference Manual 372
D Latches
LD11, LD14, and LD18
Function:
LD11: 1-bit D latch.LD14: 4-bit D latch.LD18: 8-bit D latch.
Availability: LD21 and LD24 are for pDS, ispDS, and ispDS+. LD28is for ispDS and ispDS+.
Type: Hard
Logic Resources:
Boolean Equation:
LD11 (Q0,D0,G);LD14 ([Q0..Q3],[D0..D3],G);LD18 ([Q0..Q7],[D0..D7],G);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
Macro PT GLB Output Level
LD11 3 .25 1 1LD14 3/out 1 4 1LD18 3/out 2 8 1
Input Output
D0~Dn-1 G Q0~Qn-1
d 1 dx 0 Q0’~Qn’
LD11
LD18
D Q
LD14
Q3
Q2
Q1
Q0D0
D1
D2
D3
Q3
Q2
Q1
Q0D0
D1
D2
D3
D7
D6
D5
D4 Q4
Q5
Q6
Q7
G
G
G
Macro Library Reference Manual 373
LD21, LD24, and LD28
Function:
LD21: 1-bit D latch with asynchronous clear.LD24: 4-bit D latch with asynchronous clear.LD28: 8-bit D latch with asynchronous clear.
Availability: LD21 and LD24 are for pDS, ispDS, and ispDS+. LD28is for ispDS and ispDS+.
Type: Hard
Logic Resources:
Boolean Equation:
LD21 (Q0,D0,G,CD);LD24 ([Q0..Q3],[D0..D3],G,CD);LD28 ([Q0..Q7],[D0..D7],G,CD);
Truth Table:
d = any pattern of 1s and 0s on input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
Macro PT GLB Output Level
LD21 3 .25 1 1LD24 3/out 1 4 1LD28 3/out 2 8 1
Input Output
CD D0~Dn-1 G Q0~Qn-1
1 x x 00 d 1 d0 x 0 Q0’~Qn’
LD11
LD18
D Q
LD14
Q3
Q2
Q1
Q0D0
D1
D2
D3
Q3
Q2
Q1
Q0D0
D1
D2
D3
D7
D6
D5
D4 Q4
Q5
Q6
Q7
G
G
G
Macro Library Reference Manual 374
LD31, LD34, and LD38
Function:
LD31: 1-bit D latch with asynchronous preset.LD34: 4-bit D latch with asynchronous preset.LD38: 8-bit D latch with asynchronous preset.
Availability: LD31 and LD34 are for pDS, ispDS, and ispDS+. LD38is for ispDS and ispDS+.
Type: Hard
Logic Resources:
Boolean Equation:
LD31 (Q0,D0,G,PD);LD34 ([Q0..Q3],[D0..D3],G,PD);LD38 ([Q0..Q7],[D0..D7],G,PD);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
Macro PT GLB Output Level
LD31 4 .25 1 1LD34 4/out 1 4 1LD38 4/out 2 8 1
Input Output
PD D0~Dn-1 G Q0~Qn-1
1 x x 10 d 1 d0 x 0 Q0’~Qn’
LD31
LD38
D Q
LD34
Q3
Q2
Q1
Q0D0
D1
D2
D3
D7
D6
D5
D4 Q4
Q5
Q6
Q7
PD
PD
PD
Q3
Q2
Q1
Q0D0
D1
D2
D3
G
G
G
Macro Library Reference Manual 375
LD41, LD44, and LD48
Function:
LD41: 1-bit D latch with asynchronous clear dominant overasynchronous preset.
LD44: 4-bit D latch with asynchronous clear dominant overasynchronous preset.
LD48: 8-bit D latch with asynchronous clear dominant overasynchronous preset.
Availability: LD41 and LD44 are for pDS, ispDS, and ispDS+. LD48is for ispDS and ispDS+.
Type: Hard
Logic Resources:
Boolean Equation:
LD41 (Q0,D0,G,PD,CD);LD44 ([Q0..Q3],[D0..D3],G,PD,CD);LD48 ([Q0..Q7],[D0..D7],G,PD,CD);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
Macro PT GLB Output Level
LD41 4 .25 1 1LD44 4/out 1 4 1LD48 4/out 2 8 1
Input Output
CD PD D0~Dn-1 G Q0~Qn-1
1 x x x 00 1 x x 10 0 d 1 d0 0 x 0 Q0’~Qn’
LD41
LD48
D Q
LD44
Q3
Q2
Q1
Q0D0
D1
D2
D3
D7
D6
D5
D4 Q4
Q5
Q6
Q7
PD
PD
PD
Q3
Q2
Q1
Q0D0
D1
D2
D3
CD
CD
CD
G
G
G
Macro Library Reference Manual 376
LD51, LD54, and LD58
Function:
LD51: 1-bit D latch with asynchronous preset dominant overasynchronous clear.
LD54: 4-bit D latch with asynchronous preset dominant overasynchronous clear.
LD58: 8-bit D latch with asynchronous preset dominant overasynchronous clear.
Availability: LD51 and LD54 are for pDS, ispDS, and ispDS+. LD58is for ispDS and ispDS+.
Type: Hard
Logic Resources:
Boolean Equation:
LD51 (Q0,D0,G,PD,CD);LD54 ([Q0..Q3],[D0..D3],G,PD,CD);LD58 ([Q0..Q7],[D0..D7],G,PD,CD);
Truth Table:
d = any pattern of 1s and 0s on an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
Macro PT GLB Output Level
LD51 4 .25 1 1LD54 4/out 1 4 1LD58 4/out 2 8 1
Input Output
PD CD D0~Dn-1 G Q0~Qn-1
1 x x x 10 1 x x 00 0 d 1 d0 0 x 0 Q0’~Qn’
LD51
LD58
D Q
LD54
Q3
Q2
Q1
Q0D0
D1
D2
D3
D7
D6
D5
D4 Q4
Q5
Q6
Q7
PD
PD
PD
Q3
Q2
Q1
Q0D0
D1
D2
D3
CD
CD
CD
G
G
G
Macro Library Reference Manual 377
LD61, LD64, and LD68
Function:
LD61: 1-bit D latch with scan.LD64: 4-bit D latch with scan.LD68: 8-bit D latch with scan.
Availability: LD61, LD64, and LD68 are for ispDS and ispDS+.
Type: Soft
Logic Resources – ispDS+:
Boolean Equation for ispDS+:
LD61 (Q0,D0,TI0,G,TG);LD64 ([Q0..Q3],[D0..D3],[TI0..TI3],G,TG);LD68 ([Q0..Q7],[D0..D7],[TI0..TI7],G,TG);
Truth Table:
* In proper operation, G and TG should NOT both be 1 at the same time.d = any pattern of 1s and 0s on an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
Macro PT GLB Output Level
LD61 5 .25 1 1LD64 5/out 1.25 4 1LD68 5/out 2.5 8 1
Input Output
D0~Dn-1 G TI0~TIn-1 TG Q0~Qn-1
x 0 x 0 Q0’~Qn’x 0 d 1 dd 1 x 0 d1 1 x 1 1*x 1 1 1 1*0 1 0 1 0*
TI0
Q4
Q5
Q6
Q7
D4
D5
D6
D7
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TI1
TI2
TI3
TI4
TI5
TI6
TI7
TG
TG
TI3
TI2
TI1
TI0
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TIQD
TG
FD61
FD68
FD64
G
G
G
Macro Library Reference Manual 378
LD71, LD74, and LD78
Function:
LD71: 1-bit D latch with scan and asynchronous clear.LD74: 4-bit D latch with scan and asynchronous clear.LD78: 8-bit D latch with scan and asynchronous clear.
Availability: LD71, LD74, and LD78 are for ispDS and ispDS+..
Type: Soft
Logic Resources – ispDS+:
Boolean Equation for ispDS+:
LD71 (Q0,D0,TI0,G,CD,TG);LD74 ([Q0..Q3],[D0..D3],[TI0..TI3],G,CD,TG);LD78 ([Q0..Q7],[D0..D7],[TI0..TI7],G,CD,TG);
Truth Table:
* In proper operation, G and TG should NOT both be 1 at the same time.d = any pattern of 1s and 0s on an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
Macro PT GLB Output Level
LD71 5 .25 1 1LD74 5/out 1.25 4 1LD78 5/out 2.5 8 1
Input Output
CD D0~Dn-1 G TI0~TIn-1 TG Q0~Qn-1
1 x x x x 00 x 0 x 0 Q0’~Qn’0 x 0 d 1 d0 d 1 x 0 d0 1 1 x 1 1*0 x 1 1 1 1*0 0 1 0 1 0*
TI0
Q4
Q5
Q6
Q7
D4
D5
D6
D7
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TI1
TI2
TI3
TI4
TI5
TI6
TI7
TG
TG
TI3
TI2
TI1
TI0
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TIQD
TG
LD71
LD78
LD74
CD
CD
CD
G
G
G
Macro Library Reference Manual 379
LD81, LD84, and LD88
Function:
LD81: 1-bit D latch with scan and asynchronous preset.LD84: 4-bit D latch with scan and asynchronous preset.LD88: 8-bit D latch with scan and asynchronous preset.
Availability: LD81, LD84, and LD88 are for ispDS and ispDS+.
Type: Soft
Logic Resources – ispDS+:
Boolean Equation for ispDS+:
LD81 (Q0,D0,TI0,G,PD,TG);LD84 ([Q0..Q3],[D0..D3],[TI0..TI3],G,PD,TG);LD88 ([Q0..Q7],[D0..D7],[TI0..TI7],G,PD,TG);
Truth Table:
* In proper operation, G and TG should NOT both be 1 at the same time.d = any pattern of 1s and 0s on an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
Macro PT GLB Output Level
LD81 6 .25 1 1LD84 6/out 2 4 1LD88 6/out 4 8 1
Input Output
PD D0~Dn-1 G TI0~TIn-1 TG Q0~Qn-1
1 x x x x 10 x 0 x 0 Q0’~Qn’0 x 0 d 1 d0 d 1 x 0 d0 1 1 x 1 1*0 x 1 1 1 1*0 0 1 0 1 0*
TG
TI
TI0
Q4
Q5
Q6
Q7
D4
D5
D6
D7
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TI1
TI2
TI3
TI4
TI5
TI6
TI7
TG
TG
TI3
TI2
TI1
TI0
D3
D2
D1
D0
Q3
Q2
Q1
Q0
QD
LD81
LD88
LD84
PD
PD
PD
G
G
G
Macro Library Reference Manual 380
LD91, LD94, and LD98
Function:
LD91: 1-bit D latch with scan and asynchronous cleardominant over asynchronous preset.
LD94: 4-bit D latch with scan and asynchronous cleardominant over asynchronous preset.
LD98: 8-bit D latch with scan and asynchronous cleardominant over asynchronous preset.
Availability: LD91, LD94, and LD98 are for ispDS and ispDS+.
Type: Soft
Logic Resources – ispDS+:
Boolean Equation for ispDS+:
LD91 (Q0,D0,TI0,G,PD,CD,TG);LD94 ([Q0..Q3],[D0..D3],[TI0..TI3],G,PD,CD,TG);LD98 ([Q0..Q7],[D0..D7],[TI0..TI7],G,PD,CD,T
Truth Table:
* In proper operation, G and TG should NOT both be 1 at the same time.d = any pattern of 1s and 0s on an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
Macro PT GLB Output Level
LD91 6 .25 1 1LD94 6/out 2 4 1LD98 6/out 4 8 1
Input Output
CD PD D0~Dn-1 G TI0~TIn-1 TG Q0~Qn-1
1 x x x x x 00 1 x x x x 10 0 x 0 x 0 Q0’~Qn’0 0 x 0 d 1 d0 0 d 1 x 0 d0 0 1 1 x 1 1*0 0 x 1 1 1 1*0 0 0 1 0 1 0*
TI0
Q4
Q5
Q6
Q7
D4
D5
D6
D7
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TI1
TI2
TI3
TI4
TI5
TI6
TI7
TG
TG
TI3
TI2
TI1
TI0
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TIQD
TG
LD91
LD98
LD94
PD
PD
PD
CD
CD
CD
G
G
G
Macro Library Reference Manual 381
LDA1, LDA4, and LDA8
Function:
LDA1: 1-bit D latch with scan and asynchronous presetdominant over asynchronous clear.
LDA4: 4-bit D latch with scan and asynchronous presetdominant over asynchronous clear.
LDA8: 8-bit D latch with scan and asynchronous presetdominant over asynchronous clear.
Availability: LDA1, LDA4, and LDA8 are for ispDS and ispDS+.
Type: Soft
Logic Resources – ispDS+:
Boolean Equation for ispDS+:
LDA1 (Q0,D0,TI0,G,PD,CD,TG);LDA4 ([Q0..Q3],[D0..D3],[TI0..TI3],G,PD,CD,TG);LDA8 ([Q0..Q7],[D0..D7],[TI0..TI7],G,PD,CD,TG);
Truth Table:
* In proper operation, G and TG should NOT both be 1 at the same time.d = any pattern of 1s and 0s on an input or set of inputs,Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
Macro PT GLB Output Level
LDA1 6 .25 1 1LDA4 6/out 2 4 1LDA8 6/out 4 8 1
Input Output
PD CD D0~Dn-1 G TI0~TIn-1 TG Q0~Qn-1
1 x x x x x 10 1 x x x x 00 0 x 0 x 0 Q0’~Qn’0 0 x 0 d 1 d0 0 d 1 x 0 d0 0 1 1 x 1 1*0 0 x 1 1 1 1*0 0 0 1 0 1 0*
TI0
Q4
Q5
Q6
Q7
D4
D5
D6
D7
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TI1
TI2
TI3
TI4
TI5
TI6
TI7
TG
TG
TI3
TI2
TI1
TI0
D3
D2
D1
D0
Q3
Q2
Q1
Q0
TIQD
TG
LDA1
LDA8
LDA4
PD
PD
PD
CD
CD
CD
G
G
G
Macro Library Reference Manual 382
SR Latches
LSR1 and LSR2
Function:
LSR1: Simple SR latch.LSR2: SR latch with OR on S and R inputs.
Availability: LSR1 and LSR2 are for pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
Macro Port Definition:
LSR1 (Q0,S0,R0);LSR2 (Q0,S0,S1,R0,R1);
Truth Tables:
LSR1 LSR2
* These outputs are not entirely stable. They may not remain when both S and R return to 1.** S = 1 when S0 or S1 = 1. S = 0 when S0 and S1 = 0.
R = 1 when R0 or R1 = 1. R=0 when R0 and R1 = 0.Q0 = output of flip-flop or latch.
Macro PT GLB Output Level
LSR1 2 .25 1 1LSR2 3 .25 1 1
Input Output Input OutputS0 R0 Q0 S** R** Q01 1 Q0 1 1 Q00 1 1 0 1 11 0 0 1 0 00 0 1* 0 0 1*
R
S Q
LSR1
LSR2
S0
S1
R0
R1
Q
Macro Library Reference Manual 383
Shift Registers
SRR11, SRR14, and SRR18
Function:
SRR11: 1-bit right shift register with asynchronous reset.SRR14: 4-bit version.SRR18: 8-bit version.
Availability: SRR11, SRR18, and SRR14 are for pDS, ispDS, andispDS+.
Type: Soft
Logic Resources – pDS:
* Add 1 PT per GLB for CD and 1 per GLB if Product TermClock is used.
Macro Port Definition:
SRR11 (Q0,CAI,CLK,CD);SRR14 ([Q0..Q3],CAI,CLK,CD);SRR18 ([Q0..Q7],CAI,CLK,CD);
SRR18_1 ([Q0..Q3],CAI,CLK,CD);SRR18_2 ([Q4..Q7],Q3,CLK,CD);
Truth Table:
The SRR11 has only Q0 as an output. The SRR14 has Q0 to Q3.The SRR18 has Q0 to Q7.
d = any pattern of 1s and 0s on an input or set of inputs,Q0’ = previous output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Macro PT GLB Output Level
SRR11 1* .25 1 1SRR14 1/out* 1 4 1SRR18 1/out* 2 8 1
Input Output
CD CAI CLK Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
1 x x 0 0 0 0 0 0 0 00 d ↑ d Q0’ Q1’ Q2’ Q3’ Q4’ Q5’ Q6’0 x 0 Q0’ Q1’ Q2’ Q3’ Q4’ Q5’ Q6’ Q7’0 x 1 Q0’ Q1’ Q2’ Q3’ Q4’ Q5’ Q6’ Q7’
CAI
CD
Q0
SRR11
SRR18
SRR14
Q3
Q2
Q1
Q0
CD
CAI
CAI
CD
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Macro Library Reference Manual 384
CD
CLK
CAI Q0
CD
QD
FD21
SRR11
Macro Library Reference Manual 385
SRR11
CAI
CD
Q0
SRR11
CAI
CD
Q0
SRR11
CAI
CD
Q0
SRR11
CAI
CD
Q0
CAI
CLK
CD
Q0
Q1
Q2
Q3
SRR14
Macro Library Reference Manual 386
SRR11
CAI
CD
Q0
SRR11
CAI
CD
Q0
SRR11
CAI
CD
Q0 Q3
Q2
Q1
Q0
CD
CLK
CAI
SRR11
CAI
CD
Q0
SRR11
CAI
CD
Q0
Q7
Q6
Q5
Q4
SRR11
CAI
CD
Q0
SRR11
CAI
CD
Q0
SRR11
CAI
CD
Q0
SRR11
Macro Library Reference Manual 387
SRR21, SRR24, and SRR28
Function:
SRR21: 1-bit right shift register with asynchronous reset and enable.SRR24: 4-bit version.SRR28: 8-bit version.
Availability: SRR21, SRR24, and SRR28 are for pDS, ispDS, andispDS+.
Type: Soft
Logic Resources – pDS:
* Add 1 PT per GLB for CD and 1 per GLB if Product TermClock is used.
Macro Port Definition:
SRR21 (Q0,CAI,CLK,EN,CD);SRR24 ([Q0..Q3],CAI,CLK,EN,CD);SRR28 ([Q0..Q7],CAI,CLK,EN,CD);
SRR28_1 ([Q0..Q3],CAI,CLK,EN,CD);SRR28_2 ([Q4..Q7],Q3,CLK,EN,CD);
Truth Table:
The SRR21 has only Q0 as an output. The SRR24 has Q0 to Q3.The SRR28 has Q0 to Q7.
d = any pattern of 1s and 0s on an input or set of inputs,Q0’ = previous output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Macro PT GLB Output Level
SRR21 2* .25 1 1SRR24 2/out* 1 4 1SRR28 2/out* 2 8 1
Input Output
CD EN CAI CLK Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
1 x x x 0 0 0 0 0 0 0 00 1 d ↑ d Q0’ Q1’ Q2’ Q3’ Q4’ Q5’ Q6’0 0 x ↑ Q0’ Q1’ Q2’ Q3’ Q4’ Q5’ Q6’ Q7’0 x x 0 Q0’ Q1’ Q2’ Q3’ Q4’ Q5’ Q6’ Q7’0 x x 1 Q0’ Q1’ Q2’ Q3’ Q4’ Q5’ Q6’ Q7’
CAI
CD
Q0
SRR21
SRR28
SRR24
Q3
Q2
Q1
Q0
CD
CAI
CAI
CD
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
EN
EN
EN
Macro Library Reference Manual 388
Q0
CAI
CD
QD
FD21
EN
CLK
CD
SRR21
Macro Library Reference Manual 389
EN
CAI
CD
EN
Q0
SRR21
CAI
CD
EN
Q0
SRR21
CAI
CD
EN
Q0
SRR21
CAI
CD
EN
Q0
SRR21
Q3
Q2
Q1
Q0
CD
CAI
CLK
SRR24
Macro Library Reference Manual 390
CAI
Q4
Q5
Q6
Q7
CLK
CD
Q0
Q1
Q2
Q3
CAI
CD
EN
Q0
SRR21
CAI
CD
EN
Q0
SRR21
CAI
CD
EN
Q0
SRR21
CAI
CD
EN
Q0
SRR21
CAI
CD
EN
Q0
SRR21
CAI
CD
EN
Q0
SRR21
CAI
CD
EN
Q0
SRR21
CAI
CD
EN
Q0
SRR21
EN
SRR28
Macro Library Reference Manual 391
SRR31, SRR34, and SRR38
Function: 1-, 4-, and 8-bit right shift registerswith asynchronous reset, enable, parallel dataload, and synchronous preset.
Availability: SRR31, SRR34, and SRR38 arefor pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
* Add 1 PT per GLB for CD and 1 per GLBif Product Term Clock is used.
Macro Port Definition:
SRR31 (Q0,D0,CAI,CLK,PS,LD,EN,CD);SRR34 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CD);SRR38 ([Q0..Q7],[D0..D7],CAI,CLK,PS,LD,EN,CD);
SRR38_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CD);SRR38_2 ([Q4..Q7],[D4..D7],Q3,CLK,PS,LD,EN,CD);
Truth Table:
The SRR31 has only Q0 as an output. The SRR34 has Q0 to Q3.The SRR38 has Q0 to Q7.
d = any pattern of 1s and 0s on an input or set of inputs,D0..Dn-1 = load inputs for counters and shift registers,Q0’ = previous output of flip-flop or latch, x = don’t care,↑ = rising clock edge.
Macro PT GLB Output Level
SRR31 4* .25 1 1SRR34 4/out* 1 4 1SRR38 4/out* 2 8 1
Input Output
CD PS LD D0~D7 EN CAI CLK Q0 Q1 Q2 Q3 Q4 Q5
1 x x x x x x 0 0 0 0 0 00 1 x x x x ↑ 1 1 1 1 1 10 0 1 d x x ↑ D0 D1 D2 D3 D4 D50 0 0 x 1 d ↑ d Q0’ Q1’ Q2’ Q3’ Q4’0 0 0 x 0 x ↑ Q0’ Q1’ Q2’ Q3’ Q4’ Q5’0 x x x x x 0 Q0’ Q1’ Q2’ Q3’ Q4’ Q5’0 x x x x x 1 Q0’ Q1’ Q2’ Q3’ Q4’ Q5’
SRR31 SRR38SRR34
CAI
CD
D0
EN
LD
PS
Q0
CAI
CD
D0
D2
D3
EN
LD
D1
PS
Q0
Q1
Q2
Q3
CAI
CD
D0
D2
D3
D4
D5
D7
EN
LD
D6
D1
PS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Macro Library Reference Manual 392
Q0
CD
QD
FD21CLK
CD
LD
EN
CAI
D0
PS
SRR31
Macro Library Reference Manual 393
D3
D2
D1
D0
LD
CD
CLK
PS
SRR31
CAI
CD
D0
EN
LD
PS
Q0
Q1
SRR31
CAI
CD
D0
EN
LD
PS
Q0
SRR31
CAI
CD
D0
EN
LD
PS
Q0
SRR31
CAI
CD
D0
EN
LD
PS
Q0 Q3
Q2
Q0
EN
CAI
SRR34.
Macro Library Reference Manual 394
Q3
Q2
Q1
Q0
SRR31
CAI
CD
D0
EN
LD
PS
Q0
Q5
SRR31
CAI
CD
D0
EN
LD
PS
Q0
SRR31
CAI
CD
D0
EN
LD
PS
Q0
SRR31
CAI
CD
D0
EN
LD
PS
Q0Q7
Q6
Q4CAI
EN
SRR31
CAI
CD
D0
EN
LD
PS
Q0
SRR31
CAI
CD
D0
EN
LD
PS
Q0
SRR31
CAI
CD
D0
EN
LD
PS
Q0
SRR31
CAI
CD
D0
EN
LD
PS
Q0
PS
CLK
CD
LD
D0
D1
D2
D3
D4
D5
D6
D7
SRR38
Macro Library Reference Manual 395
SRR41, SRR44, and SRR48
Function: 1-, 4-, and 8-bit right shift registers withsynchronous reset, enable, parallel data load,and synchronous preset.
Availability: SRR41, SRR44, and SRR48 arefor pDS, ispDS, and ispDS+.
Type: Soft
Logic Resources – pDS:
* Add 1 PT per GLB if Product Term Clockis used.
Macro Port Definition:
SRR41 (Q0,D0,CAI,CLK,PS,LD,EN,CS);SRR44 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CS);SRR48 ([Q0..Q7],[D0..D7],CAI,CLK,PS,LD,EN,CS);
SRR48_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CS);SRR48_2 ([Q4..Q7],[D4..D7],Q3,CLK,PS,LD,EN,CS);
Truth Table:
The SRR41 has only Q0 as an output. The SRR44 has Q0 to Q3.The SRR48 has Q0 to Q7.
d = any pattern of 1s and 0s on an input or set of inputs,D0..Dn-1 = load inputs for shift registers,Q0’ = previous output of flip-flop, x = don’t care,↑ = rising clock edge.
Macro PT GLB Output Level
SRR41 4* .25 1 1SRR44 4/out* 1 4 1SRR48 4/out* 2 8 1
Input Output
PS CS LD D0~D7 EN CAI CLK Q0 Q1 Q2 Q3 Q4 Q5 Q6
1 x x x x x ↑ 1 1 1 1 1 1 10 1 x x x x ↑ 0 0 0 0 0 0 00 0 1 d x x ↑ D0 D1 D2 D3 D4 D5 D60 0 0 x 1 d ↑ d Q0’ Q1’ Q2’ Q3’ Q4’ Q5’0 0 0 x 0 x ↑ Q0’ Q1’ Q2’ Q3’ Q4’ Q5’ Q6’x x x x x x 0 Q0’ Q1’ Q2’ Q3’ Q4’ Q5’ Q6’x x x x x x 1 Q0’ Q1’ Q2’ Q3’ Q4’ Q5’ Q6’
SRR41 SRR48SRR44
CAI
CS
D0
EN
LD
PS
Q0
CAI
CS
D0
D2
D3
EN
LD
D1
PS
Q0
Q1
Q2
Q3
CAI
CS
D0
D2
D3
D4
D5
D7
EN
LD
D6
D1
PS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Macro Library Reference Manual 396
Q0
CS
QD
FD11CLK
EN
CAI
LD
D0
PS
SRR41
Macro Library Reference Manual 397
SRR41
Q0
PS
LD
EN
D0
CS
CAI
SRR41
Q0
PS
LD
EN
D0
CS
CAI
SRR41
Q0
PS
LD
EN
D0
CS
CAI
SRR41
Q0
PS
LD
EN
D0
CS
CAICAI
EN
Q0
Q2
Q3
Q1
PS
CLK
CS
LD
D0
D1
D2
D3
SRR44
Macro Library Reference Manual 398
SRR41
Q0
PS
LD
EN
D0
CS
CAIQ3
SRR41
Q0
PS
LD
EN
D0
CS
CAI
SRR41
Q0
PS
LD
EN
D0
CS
CAI
SRR41
Q0
PS
LD
EN
D0
CS
CAI
SRR41
Q0
PS
LD
EN
D0
CS
CAI
SRR41
Q0
PS
LD
EN
D0
CS
CAI
SRR41
Q0
PS
LD
EN
D0
CS
CAI
SRR41
Q0
PS
LD
EN
D0
CS
CAI
D7
D6
D5
D4
D3
D2
D1
D0
LD
CS
CLK
PS
Q1
Q2
Q0
EN
CAIQ4
Q6
Q7
Q5
SRR48
Macro Library Reference Manual 399
SRRL1, SRRL4, and SRRL8
Function: 1-, 4-, and 8-bit right/left shift registers withasynchronous reset, enable, parallel data load,synchronous preset, and synchronous reset.
Availability: SRRL1, SRRL4, and SRRL8 are for pDS, ispDS,and ispDS+.
An additional symbol appears on the following page.
Type: Soft
Logic Resources – pDS:
* Add 1 PT per GLB for CD and 1 per GLB if Product TermClock is used.
Macro Port Definition:
SRRL1 (Q0,D0,CAIR,CAIL,CLK,PS,LD,EN,RL,CD,CS);SRRL4 ([Q0..Q3],[D0..D3],CAIR,CAIL,CLK,PS,LD,EN,RL,CD,CS);
SRRL4_1 (Q0,Q1,D0,D1,CAIR,Q2,CLK,PS,LD,EN,RL,CD,CS);SRRL4_2 (Q2,Q3,D2,D3,Q1,CAIL,CLK,PS,LD,EN,RL,CD,CS);
SRRL8 ([Q0..Q7],[D0..D7],CAIR,CAIL,CLK,PS,LD,EN,RL,CD,CS);SRRL8_1 ([Q0..Q2],[D0..D2],CAIR,Q3,CLK,PS,LD,EN,RL,CD,CS);SRRL8_2 ([Q3..Q5],[D3..D5],Q2,Q6,CLK,PS,LD,EN,RL,CD,CS);SRRL8_3 (Q6,Q7,D6,D7,Q5,CAIL,CLK,PS,LD,EN,RL,CD,CS);
Macro PT GLB Output Level
SRRL1 5* 0.5 1 1SRRL4 5/out* 1.5 4 1SRRL8 5/out* 2.75 8 1
SRRL1 SRRL4
R/L
Q0
PSCAIR
LD
EN
CSCD
CAIL
D0
R/L
D0
D2
D3
CAIL
CD CS
EN
LD
CAIR
D1
PS
Q0
Q1
Q2
Q3
Macro Library Reference Manual 400
Truth Table:
The SRRL1 has only Q0 as an output. The SRRL4 has Q0 to Q3.The SRRL8 has Q0 to Q7.
CAIL = shift left serial input, CAIR = shift right serial input,d = any pattern of 1s and 0s on an input or set of inputs,D0..Dn-1 = input to D or T flip-flop/latch; load inputs for counters and shift registers,Q0’ = previous output of flip-flop or latch, x = don’t care, ↑ = rising clock edge.
Input
CD PS CS LD D0~D7 RL EN CAIR CAIL CLK
1 x x x x x x x x x0 1 x x x x x x x ↑0 0 1 x x x x x x ↑0 0 0 1 d x x x x ↑0 0 0 0 x 0 1 x d ↑0 0 0 0 x 1 1 d x ↑0 0 0 0 x x 0 x x ↑0 x x x x x x x x 00 x x x x x x x x 1
Output
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0 0 0 0 0 01 1 1 1 1 1 1 10 0 0 0 0 0 0 0
D0 D1 D2 D3 D4 D5 D6 D7Q1 Q2 Q3 Q4 Q5 Q6 Q7 CAIL
CAIR Q0 Q1 Q2 Q3 Q4 Q5 Q6Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
SRRL8
R/L
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
PS
D1
CAIR
D6
LD
EN
CSCD
CAIL
D7
D5
D4
D3
D2
D0
Macro Library Reference Manual 401
Q0
EN
RL
LD
CS
. LD=HI : Parallel data load
. EN=LO : Keep the previous state
. EN=HI & RL=LO & LD=LO : Shift CAIL to the left
Note:
. CS & PS & CD are active hi
. EN=HI & RL=HI & LD=LO : Shift CAIR to the right
CAIR
CAIL
D0
PS
CD
QD
FD21CLK
CD
SRRL1
Macro Library Reference Manual 402
CAIL
Q3
CAIR
CS
CD
CLK
EN
LD
RL
Q0
PS
CAIR
LD
EN
CSCD
CAIL
D0
SRRL1
R/L
Q0
PS
CAIR
LD
EN
CSCD
CAIL
D0
SRRL1
R/L
Q0
PS
CAIR
LD
EN
CSCD
CAIL
D0
SRRL1
R/L
PS
D0 Q0
D1 Q1
D2 Q2
D3
Note:
CS & PS & CD are active hi
EN=HI & RL=HI & LD=LO: Shift CAIR to the right
EN=HI & RL=LO & LD=LO: Shift CAIL to the left
EN=LO: Keep the previous state
LD=HI: Parallel data load
Q0
PS
CAIR
LD
EN
CSCD
CAIL
D0
SRRL1
R/L
SRRL4
Macro Library Reference Manual 403
CAIR
CS
CD
CLK
EN
LD
RL
Q0
PS
CAIR
LD
EN
CSCD
CAIL
D0
SRRL1
R/L
Q0
PS
CAIR
LD
EN
CSCD
CAIL
D0
SRRL1
R/L
Q0
PS
CAIR
LD
EN
CSCD
CAIL
D0
SRRL1
R/L
PS
D0 Q0
Q0
PS
CAIR
LD
EN
CSCD
CAIL
D0
SRRL1
R/L
D1 Q1
D2
D3
Q5Q0
PS
CAIR
LD
EN
CSCD
CAIL
D0
SRRL1
R/L
D5
Q2
Q3
D4 Q0
PS
CAIR
LD
EN
CSCD
CAIL
D0
SRRL1
R/L
Q4
Note:
CS & PS & CD are active hi
EN=HI & RL=HI & LD=LO: Shift CAIR to the right
EN=HI & RL=LO & LD=LO: Shift CAIL to the left
EN=LO: Keep the previous state
LD=HI: Parallel data load
CAIL
Q7
Q0
PS
CAIR
LD
EN
CSCD
CAIL
D0
SRRL1
R/L
Q0
PS
CAIR
LD
EN
CSCD
CAIL
D0
SRRL1
R/L
D6 Q6
D7
SRRL8
Macro Library Reference Manual 404
Module Macros
This chapter contains information on the following Module Macros:
■ Control Blocks
■ Timer/Counter Modules
■ RAM Modules
■ FIFO Modules
■ Register File Modules
Macro Library Reference Manual 405
Control Blocks
This section illustrates the PIN-OUT and truth tables of control blocks used to set/modify userprogrammable features of the module macros.
ALECTRL8, ALECTRL9
These are used to program the value of the Almost Empty flag of theFIFOs.
ALECTRL8: 8-bit almost empty flag control block (used in FIFO1and FIFO2)
ALECTRL9: 9-bit almost empty flag control block (used in FIFO3and FIFO4)
Availability: ALECTRL8 and ALECTRL9 are for ispDS+ only.
Truth Table:
ALEIN ALEVAL
High HighLow Low
ALEIN0ALEIN1ALEIN2ALEIN3ALEIN4ALEIN5ALEIN6ALEIN7ALEIN8
ALEVAL0ALEVAL1ALEVAL2ALEVAL3ALEVAL4ALEVAL5ALEVAL6ALEVAL7ALEVAL8
ALECTRL9
ALEIN0ALEIN1ALEIN2ALEIN3ALEIN4ALEIN5ALEIN6ALEIN7
ALEVAL0ALEVAL1ALEVAL2ALEVAL3ALEVAL4ALEVAL5ALEVAL6ALEVAL7
ALECTRL8
Macro Library Reference Manual 406
ALFCTRL8, ALFCTRL9
These blocks are used to program the value of the Almost Full flagof the FIFOs.
ALFCTRL8: 8-bit almost full flag control block (used in FIFO1 andFIFO2)
ALFCTRL9: 9-bit almost full flag control block (used in FIFO3 andFIFO4)
Availability: ALFCTRL8 and ALFCTRL9 are for ispDS+ only.
Truth Table:
ALFIN ALFVAL
High HighLow Low
ALFIN0ALFIN1ALFIN2ALFIN3ALFIN4ALFIN5ALFIN6ALFIN7ALFIN8
ALFVAL0ALFVAL1ALFVAL2ALFVAL3ALFVAL4ALFVAL5ALFVAL6ALFVAL7ALFVAL8
ALFCTRL9
ALFIN0ALFIN1ALFIN2ALFIN3ALFIN4ALFIN5ALFIN6ALFIN7
ALFVAL0ALFVAL1ALFVAL2ALFVAL3ALFVAL4ALFVAL5ALFVAL6ALFVAL7
ALFCTRL8
Macro Library Reference Manual 407
PSCTRL
This block is used to program the custom preset values for the timermodule (T4R4CPV).
PSCTRL: Custom Preset value control block
Availability: PSCTRL is for ispDS+ only.
Truth Table:
PSI PSO
High HighLow Low
PSI0PSI1PSI2PSI3PSI4PSI5PSI6PSI7PSI8
PSO0PSO1PSO2PSO3PSO4PSO5PSO6PSO7PSO8
PSCTRL
PSI9PSI10PSI11PSI12PSI13PSI14PSI15
PSO9PSO10PSO11PSO12PSO13PSO14PSO15
Macro Library Reference Manual 408
POLCTRL
This block is used to control/modify the polarity of module controlsignals EN, MRST, RW, ACS, of other memory/register file modules,etc. The functionality of all in POLCTRL blocks is identical while thesize of the block is dependent on the number of control signals in themodules.
POLCTRL1: 1-bit polarity control block
POLCTRL2: 2-bit polarity control block
POLCTRL4: 4-bit polarity control block
POLCTRL8: 8-bit polarity control block
Availability: POLCTRL1, POLCTRL2, POLCTRL4, and POLCTRL8is for ispDS+ only.
Truth Table:
POLIN POL
High HighLow Low
POLIN0POLIN1POLIN2POLIN3POLIN4POLIN5POLIN6POLIN7
POL0POL1POL2POL3POL4POL5POL6POL7
POLIN0POLIN1POLIN2POLIN3
POL0POL1POL2POL3
POLIN0POLIN1
POL0POL1
POLIN0 POL0
POLCTRL1
POLCTRL8
POLCTRL4
POLCTRL2
Macro Library Reference Manual 409
CAOCTRL
CAOCTRL: Carry out control block is used to control thevalue of the carry-out signal in timer/counter modules.
Availability: CAOCTRL is for ispDS+ only.
Truth Table:
BK_IN BK_CAOCTRL
High HighLow Low
BK_IN BK_CAOCTRL
CAOCTRL
Macro Library Reference Manual 410
Timer/Counter Modules
C4R4AL
Availability: C4R4AL is for ispDS+ only.
Description: 4-bank register 8/16-bit up/down counter with adjacentload-enable. Banks 1, 3, 5, and 7 are counters while 0, 2, 4, and 6are registers.
* These inputs, once set, are fixed and can only be connected to VCC/GND.‡ Refer to User Programmable Features table
Input
DI[15:0] 16-bit parallel data-in.B[1,3,5,7]PLEN Adjacent bank parallel load enable input. When
active high, loads the adjacent register [0,2,4,6] intothe corresponding counter bank.
B[1,3,5,7]SZ* Bank size select input. Controls the size of thecorresponding counter bank. 1 is 16-bit, 0 is 8-bit.
BS[2:0] Bank select inputs.B[1,3,5,7]UD* Bank up/down select input. Controls the up/down
counting of the corresponding counter bank. 1 isup, 0 is down.
B[1,3,5,7]CH Bank count/hold select input. Controls the count/hold operation of the corresponding counter bank. 1is count, 0 is hold the count.
B[0:7]CLK Bank clock input.MRST Module reset signal. When active high resets the
counter banks to zero.EN‡ Parallel data load enable input. When active high,
loads the DI[15:0] input into the counter bankselected by the input BS[2:0].
Output
B[1,3,5,7]CO‡ Active high. Indicates the corresponding counterbank has reached its terminal count.
DO[15:0] 16-bit parallel data-out from the counter.
DI0DI1DI2DI3DI4DI5DI6DI7DI8DI9DI10DI11DI12DI13DI14DI15
B1SZB3SZB5SZB7SZ
BS0BS1BS2
B1UDB3UDB5UDB7UDB1CHB3CHB5CHB7CH
B0CLKB1CLKB2CLKB3CLKB4CLKB5CLKB6CLKB7CLK
MRST
EN
B1COB3COB5COB7CO
DO0DO1DO2DO3DO4DO5DO6DO7DO8DO9
DO10DO11DO12DO13DO14DO15
C4R4AL
B1PLENB3PLENB5PLENB7PLEN
Macro Library Reference Manual 411
C4R4AL
† Refer to the section on Control Blocks for functionality
#Carry-Out Control Block(Applicable only when the counter reaches terminal count.)
ProgrammablePin
Control BlockAttached Description
EN POLCTRL1† Polarity controlled by POLEN, which has adefault value of high.
B[1,3,5,7]CO# CAOCTRL† Output carry-out signal is controlled byRP[1,3,5,7] which is low by default.
RP[1,3,5,7]B[1,3,5,7]CH
High Low
High B[1,3,5,7]CO=High B[1,3,5,7]CO=High
Low B[1,3,5,7]CO=Low B[1,3,5,7]CO=High
Macro Library Reference Manual 412
C4R4PL
Availability: C4R4PL is for ispDS+ only.
Description: 4-bank register 8/16-bit up/down counter with parallelload-enable. Banks 1, 3, 5, and 7 are counters while 0, 2, 4, and 6are registers.
* These inputs, once set, are fixed and can only be connected to VCC/GND.‡ Refer to User Programmable Features table
Input
DI[15:0] 16-bit parallel data-in.B[1,3,5,7]SZ* Bank size select input. Controls the size of the
corresponding counter bank. 1 is a 16-bit, 0 is an8-bit.
BS[2:0] Bank select inputs.B[1,3,5,7]UD* Bank up/down select input. Controls the up/down
counting of the corresponding counter bank. 1 isup, 0 is down.
B[1,3,5,7]CH Bank count/hold select input. Controls the count/hold operation of the corresponding counter bank.1 is count, 0 is hold the count.
B[0:7]CLK Bank clock input.MRST Module reset signal. When active high, resets the
counter banks to zero.EN‡ Parallel data load enable input. When active high,
loads the DI[15:0] input into the counter bankselected by the input BS[2:0].
Output
B[1,3,5,7]CO‡ Active high. Indicates the corresponding counterbank has reached its terminal count.
DO[15:0] 16-bit parallel data-out from the counter.
DI0DI1DI2DI3DI4DI5DI6DI7DI8DI9DI10DI11DI12DI13DI14DI15
B1SZB3SZB5SZB7SZ
BS0BS1BS2
B1UDB3UDB5UDB7UD
B1CHB3CHB5CHB7CH
B0CLKB1CLKB2CLKB3CLKB4CLKB5CLKB6CLKB7CLK
MRST
EN
B1COB3COB5COB7CO
DO0DO1DO2DO3DO4DO5DO6DO7DO8DO9
DO10DO11DO12DO13DO14DO15
C4R4PL
Macro Library Reference Manual 413
C4R4PL
† Refer to the section on Control Blocks for functionality
#Carry-Out Control(Applicable only when the counter reaches terminal count.)
ProgrammablePin
Control BlockAttached Description
EN POLCTRL1† Polarity controlled by POLEN, which has a defaultvalue of high.
B[1,3,5,7]CO# CAOCTRL† Carry-out signal is controlled by RP[1,3,5,7] whichis low by default.
RP[1,3,5,7]B[1,3,5,7]CH
High Low
High B[1,3,5,7]CO=High B[1,3,5,7]CO=High
Low B[1,3,5,7]CO=Low B[1,3,5,7]CO=High
Macro Library Reference Manual 414
T4R4AL
Availability: T4R4AL is for ispDS+ only.
Description: 4-bank register 8/16-bit up/down timer with adjacentload-enable. Banks 1, 3, 5, and 7 are timers while 0, 2, 4, and 6 areregisters.
* These inputs, once set, are fixed and can only be connected to VCC/GND.‡ Refer to User Programmable Features table
Input
DI[15:0] 16-bit parallel data-in.B[1,3,5,7]PLEN Adjacent bank parallel load enable input. When active
high, loads the adjacent register 0,2,4,6] into thecorresponding timer bank.
B[1,3,5,7]SZ* Bank size select input. Controls the size of thecorresponding timer bank. 1 is a 16-bit, 0 is an 8-bit.
BS[2:0] Bank select inputs.B[1,3,5,7]UD* Bank up/down select input. Controls the up/down
counting of the corresponding timer bank. 1 is up, 0 isdown.
B[1,3,5,7]CH Bank count/hold select input. Controls the count/holdoperation of the corresponding timer bank. 1 is count,0 is hold the count.
B[0:7]CLK Bank clock input.MRST Module reset signal. When active high, resets the
timer banks to zero.EN‡ Parallel data load enable input. When active high,
loads the DI[15:0] input into the timer bank selectedby the input BS[2:0].
Output
B[1,3,5,7TC‡ Active high. Indicates the corresponding timer bankhas reached its terminal count.
DO[15:0] 16-bit parallel data-out from the timer.
DI0DI1DI2DI3DI4DI5DI6DI7DI8DI9DI10DI11DI12DI13DI14DI15
B1SZB3SZB5SZB7SZ
BS0BS1BS2
B1UDB3UDB5UDB7UDB1CHB3CHB5CHB7CH
B0CLKB1CLKB2CLKB3CLKB4CLKB5CLKB6CLKB7CLK
MRST
EN
B1TCB3TCB5TCB7TC
DO0DO1DO2DO3DO4DO5DO6DO7DO8DO9
DO10DO11DO12DO13DO14DO15
T4R4AL
B1PLENB3PLENB5PLENB7PLEN
Macro Library Reference Manual 415
T4R4AL
† Refer to the section on Control Blocks for functionality
#Carry-Out Control(Applicable only when the counter reaches terminal count.)
Programmable Pin Control BlockAttached Description
EN POLCTRL1† Polarity controlled by POLEN, which has a defaultvalue of high.
B[1,3,5,7]TC# CAOCTRL† Carry-out signal is controlled by RP[1,3,5,7] whichis low by default.
RP[1,3,5,7]B[1,3,5,7]CH
High Low
High B[1,3,5,7]TC=High B[1,3,5,7]TC=High
Low B[1,3,5,7]TC=Low B[1,3,5,7]TC=High
Macro Library Reference Manual 416
T4R4PL
Availability: T4R4PL is for ispDS+ only.
Description: A 4-bank register 8/16-bit up/down timer with parallelload-enable. Banks 1, 3, 5, and 7 are timers while 0, 2, 4, and 6 areregisters.
* These inputs, once set, are fixed and can only be connected to VCC/GND.‡ Refer to User Programmable Features table
Input
DI[15:0] 16-bit parallel data-in.B[1,3,5,7]SZ* Bank size select input. Controls the size of the
corresponding timer bank. 1 is 16-bit, 0 is 8-bit.BS[2:0] Bank select inputs.B[1,3,5,7]UD* Bank up/down select input. Controls the up/down
counting of the corresponding timer bank. 1 is up, 0 isdown.
B[1,3,5,7]CH Bank count/hold select input. Controls the count/holdoperation of the corresponding timer bank. 1 is count,0 is hold the count.
B[0:7]CLK Bank clock input.MRST Module reset signal. When active high, resets the
timer banks to zero.EN‡ Parallel data load enable input. When active high,
loads the DI[15:0] input into the timer bank selectedby the input BS[2:0].
Output
B[1,3,5,7]TC‡ Active high. Indicates the corresponding timer bankhas reached its terminal count.
DO[15:0] 16-bit parallel data-out from the timer.
DI0DI1DI2DI3DI4DI5DI6DI7DI8DI9DI10DI11DI12DI13DI14DI15
B1SZB3SZB5SZB7SZ
BS0BS1BS2
B1UDB3UDB5UDB7UD
B1CHB3CHB5CHB7CH
B0CLKB1CLKB2CLKB3CLKB4CLKB5CLKB6CLKB7CLK
MRST
EN
B1TCB3TCB5TCB7TC
DO0DO1DO2DO3DO4DO5DO6DO7DO8DO9
DO10DO11DO12DO13DO14DO15
T4R4PL
Macro Library Reference Manual 417
T4R4PL
† Refer to the section on Control Blocks for functionality
#Carry-Out Control(Applicable only when the timer reaches terminal count.)
ProgrammablePin
Control BlockAttached Description
EN POLCTRL1† Polarity controlled by POLEN, which has adefault value of high.
B[1,3,5,7]TC# CAOCTRL† Carry-out signal is controlled by RP[1,3,5,7]which is low by default.
RP[1,3,5,7]B[1,3,5,7]CH
High Low
High B[1,3,5,7]TC=High B[1,3,5,7]TC=High
Low B[1,3,5,7]TC=Low B[1,3,5,7]TC=High
Macro Library Reference Manual 418
T4R4CPV
Availability: T4R4CPV is for ispDS+ only.
Description: 4-bank register 8/16 bit up/down timer with custom-preset value enable options.
* These inputs, once set, are fixed and can only be connected to VCC/GND.‡ Refer to User Programmable Features table
Input
DI[15:0] 16-bit parallel data-in.B[1,3,5,7]PLEN‡ Preset load value load enable input. When active
high, loads the custom preset value into thecorresponding timer bank.
B[1,3,5,7]SZ* Bank size select input. Controls the size of thecorresponding timer bank. 1 is 16-bit, 0 is 8-bit.
BS[2:0] Bank select inputs.B[1,3,5,7]UD* Bank up/down select input. Controls the up/down
counting of the corresponding timer bank. 1 is up, 0 isdown.
B[1,3,5,7]CH Bank count/hold select input. Controls the count/holdoperation of the corresponding timer bank. 1 is count,0 is hold the count.
B[0:7]CLK Bank clock input.MRST Module reset signal. When active high, resets the
timer banks to zero.EN‡ Parallel data load enable input. When active high,
loads the DI[15:0] input into the timer bank selectedby the input BS[2:0].
Output
B[1,3,5,7]TC‡ Active high. Indicates the corresponding timer bankhas reached its terminal count.
DO[15:0] 16-bit parallel data-out from the timer.
DI0DI1DI2DI3DI4DI5DI6DI7DI8DI9DI10DI11DI12DI13DI14DI15
B1SZB3SZB5SZB7SZ
BS0BS1BS2
B1UDB3UDB5UDB7UDB1CHB3CHB5CHB7CH
B0CLKB1CLKB2CLKB3CLKB4CLKB5CLKB6CLKB7CLK
MRST
EN
B1TCB3TCB5TCB7TC
DO0DO1DO2DO3DO4DO5DO6DO7DO8DO9
DO10DO11DO12DO13DO14DO15
T4R4CPV
B1PLENB3PLENB5PLENB7PLEN
Macro Library Reference Manual 419
T4R4CPV
† Refer to the section on Control Blocks for functionality
#Carry-Out Control(Applicable only when the timer reaches terminal count.)
ProgrammablePin
Control BlockAttached Description
EN POLCTRL1† Polarity controlled by POLEN, which has a defaultvalue of high.
B[1,3,5,7]TC# CAOCTRL† Carry-out signal is controlled by RP[1,3,5,7] whichis low by default.
B[1,3,5,7]PLEN PSCTRL [1,3,5,7]† When active high, the custom preset value inputsCPV[1,3,5,7]-[15:0] determine the preset loadvalue; CPV[1,3,5,7] [0] is the LSB. The defaultvalue is zero.
RP[1,3,5,7]B[1,3,5,7]CH
High Low
High B[1,3,5,7]TC=High B[1,3,5,7]TC=High
Low B[1,3,5,7]TC=Low B[1,3,5,7]TC=High
Macro Library Reference Manual 420
RAM Modules
Port A interfaces with external logic through dedicated I/O pins and port B isinternal to the device through the GRP.
RAM1
Availability: RAM1 is for ispDS+ only.
Description: 256 x 18 single port RAM using A port.
‡ Refer to User Programmable Features table** ADI, ADO are required to share I/O pins so must be connected
to bidirectional pins.
Input
ADI[17:0]** 18-bit data-in at port A.ARW‡ Read/write enable. By default, when ARW is low,
function is write enable; when ARW is high, functionis read enable.
AA[7:0] Memory address.ACS‡ Chip select. By default, ACS is active low. When
ACS is active, RAM responds to read/write enable.
Output
ADO[17:0]** 18-bit data-out.
ADI0ADI1ADI2ADI3ADI4ADI5ADI6ADI7ADI8ADI9ADI10ADI11ADI12ADI13ADI14ADI15
ARW
AA0AA1AA2AA3AA4AA5AA6AA7
ACS
ADO0ADO1ADO2ADO3ADO4ADO5ADO6ADO7ADO8ADO9
ADO10ADO11ADO12ADO13ADO14ADO15
ADI16ADI17
ADO16ADO17
RAM1
Macro Library Reference Manual 421
RAM1
† Refer to the section on Control Blocks for functionality
ProgrammablePin
Control BlockAttached Description
ACS POLCTRL2† Polarity controlled by POL_CHS, which has adefault value of high.
ARW POLCTRL2† Polarity controlled by POL_WRL, which has adefault value of high.
Macro Library Reference Manual 422
RAM2
Availability: RAM2 is for ispDS+ only.
Description: 256 x 18 single port RAM using B port.
Input
BDI[17:0] 18-bit data-in.BRW Read/write enable. By default, when BRW is low, the
function is write enable; when BRW is high, thefunction is read enable.
BA[7:0] Memory addressBCS Chip Select. By default, BCS is active low. When
BCS is active, RAM responds to read/write enable.
Output
BDO[17:0] 18-bit data-out.
BDI0BDI1BDI2BDI3BDI4BDI5BDI6BDI7BDI8BDI9BDI10BDI11BDI12BDI13BDI14BDI15
BRW
BA0BA1BA2BA3BA4BA5BA6BA7
BCS
BDO0BDO1BDO2BDO3BDO4BDO5BDO6BDO7BDO8BDO9
BDO10BDO11BDO12BDO13BDO14BDO15
BDI16BDI17
BDO16BDO17
RAM2
Macro Library Reference Manual 423
RAM3
Availability: RAM3 is for ispDS+ only.
Description: 256 x 18 single port RAM using A port with 9-bitwrite/read.
‡ Refer to User Programmable Features table** ADI, ADO are required to share I/O pins so must be connected
to bidirectional pins.
Input
ADI[17:0]** 18-bit data-in.ARWL‡ Read/write enable from/to lower 9-bit location of
memory. By default, when ARWL is low, thefunction is write enable; when ARWL is high, thefunction is read enable.
ARWH‡ Read/write enable from/to upper 9-bit location ofmemory. By default, when ARWH is low, thefunction is write enable; when ARWH is high, thefunction is read enable.
AA[7:0] Memory address.ACS‡ Chip Select. By default, ACS is active low. When
ACS is active, RAM responds to read/write enable.
Output
ADO[17:0]** 18-bit data-out.
ADI0ADI1ADI2ADI3ADI4ADI5ADI6ADI7ADI8ADI9ADI10ADI11ADI12ADI13ADI14ADI15
ARWL
AA0AA1AA2AA3AA4AA5AA6AA7
ACS
ADO0ADO1ADO2ADO3ADO4ADO5ADO6ADO7ADO8ADO9
ADO10ADO11ADO12ADO13ADO14ADO15
ADI16ADI17
ADO16ADO17
RAM3
ARWH
Macro Library Reference Manual 424
RAM3
† Refer to the section on Control Blocks for functionality
ProgrammablePin
Control BlockAttached Description
ACS POLCTRL2† Polarity controlled by POL_CHS, which has adefault value of high.
ARWL POLCTRL1† Polarity controlled by POL_WRL, which has adefault value of high.
ARWH POLCTRL2† Polarity controlled by POL_WRH, which has adefault value of high.
Macro Library Reference Manual 425
RAM4
Availability: RAM4 is for ispDS+ only.
Description: 256 x 18 single port RAM using B port with 9-bitwrite/read.
Input
BDI[17:0] 18-bit data-in.BRWL Read/write enable from/to lower 9-bit location of
memory. By default, if BRWL is low, the function iswrite enable; if BRWL is high, the function is readenable.
BRWH Read/write enable from/to upper 9-bit location ofmemory. By default, if BRWH is low, the function iswrite enable; if BRWH is high, the function is readenable.
BA[7:0] Memory address.BCS Chip Select. By default, BCS is active low. When
BCS is active, RAM responds to read/write enable.
Output
BDO[17:0] 18-bit data-out.
BDI0BDI1BDI2BDI3BDI4BDI5BDI6BDI7BDI8BDI9BDI10BDI11BDI12BDI13BDI14BDI15
BRWL
BA0BA1BA2BA3BA4BA5BA6BA7
BCS
BDO0BDO1BDO2BDO3BDO4BDO5BDO6BDO7BDO8BDO9
BDO10BDO11BDO12BDO13BDO14BDO15
BDI16BDI17
BDO16BDO17
RAM4
BRWH
Macro Library Reference Manual 426
RAM5
Availability: RAM5 is for ispDS+ only.
Description: 512 x 9 single port using A port.
‡ Refer to User Programmable Features table** ADI, ADO are required to share I/O pins so must be connected
to bidirectional pins.
Input
ADI[8:0]** 9-bit data-in.ARWL‡ Read/write enable. By default, when ARWL is
low, function is write enable; when ARWL ishigh, function is read enable.
AA[8:0] Memory address.ACS‡ Chip Select. By default, ACS is active low.
When ACS is activ e, RAM responds to read/write enable.
Output
ADO[8:0]** 9-bit data-out.
ADI0ADI1ADI2ADI3ADI4ADI5ADI6ADI7ADI8
ARWL
AA0AA1AA2AA3AA4AA5AA6AA7
ACS
ADO0ADO1ADO2ADO3ADO4ADO5ADO6ADO7ADO8
RAM5
AA8
Macro Library Reference Manual 427
RAM5
† Refer to the section on Control Blocks for functionality
ProgrammablePin
Control BlockAttached Description
ACS POLCTRL2† Polarity controlled by POL_CHS, which has adefault value of high.
ARWL POLCTRL2† Polarity controlled by POL_WRL, which has adefault value of high.
Macro Library Reference Manual 428
RAM6
Availability: RAM6 is for ispDS+ only.
Description: 512 x 9 single port using B port.
Input
BDI[8:0] 9-bit data-in.BRWL Read/write enable. By default, when BRWL is low,
the function is write enable; when BRWL is high,the function is read enable.
BA[8:0] Memory address.BCS Chip Select. By default, BCS is active low. When
BCS is active, RAM responds to read/write enable.
Output
BDO[8:0] 9-bit data-out.
BDI0BDI1BDI2BDI3BDI4BDI5BDI6BDI7BDI8
BRWL
BA0BA1BA2BA3BA4BA5BA6BA7
BCS
BDO0BDO1BDO2BDO3BDO4BDO5BDO6BDO7BDO8
RAM6
BA8
Macro Library Reference Manual 429
RAM7
Availability: RAM7 is for ispDS+ only.
Description: Two 128 x 18, single port RAM.
‡ Refer to User Programmable Features table** ADI, ADO are required to share I/O pins so must be connected
to bidirectional pins.
Input
ADI[17:0]** 18-bit data-in to port A.BDI[17:0] 18-bit data-in to port B.ARW‡ Read/write enable for port A. By default, when
ARW is low, the function is write enable; whenARW is high, the function is read enable.
BRW Read/write enable for port B. By default, whenBRW is low, the function is write enable; whenBRW is high, the function is read enable.
AA[6:0] Memory address to port A.BA[6:0] Memory address to port B.ACS‡ Chip select to port A. By default, ACS is active low.
When ACS is active, port A of RAM responds toread/write enable.
BCS Chip select to port B. By default, BCS is active low.When BCS is active, port B of RAM responds toread/write enable.
Output
ADO[17:0]** 18-bit data-out from port A.BDO[17:0] 18-bit data-out from port B.
RAM7
ADI0ADI1ADI2ADI3ADI4ADI5ADI6ADI7ADI8ADI9ADI10ADI11ADI12ADI13ADI14ADI15
ARW
AA0AA1AA2AA3AA4AA5AA6
ACS
ADI16ADI17
BCS
BA0BA1BA2BA3BA4BA5BA6
BDI0BDI1BDI2BDI3BDI4BDI5ADI6BDI7BDI8BDI9BDI10BDI11BDI12BDI13BDI14BDI15BDI16BDI17
BRW
ADO0ADO1ADO2ADO3ADO4ADO5ADO6ADO7ADO8ADO9
ADO10ADO11ADO12ADO13ADO14ADO15ADO16ADO17
BDO0BDO1BDO2BDO3BDO4BDO5BDO6BDO7BDO8BDO9
BDO10BDO11BDO12BDO13BDO14BDO15BDO16BDO17
Macro Library Reference Manual 430
RAM7
† Refer to the section on Control Blocks for functionality
ProgrammablePin
Control BlockAttached Description
ACS POLCTRL2† Polarity controlled by POL_CHS, which has adefault value of high.
ARWL POLCTRL2† Polarity controlled by POL_WRL, which has adefault value of high.
Macro Library Reference Manual 431
RAM8
Availability: RAM8 is for ispDS+ only.
Description: Two 128 x 18, single port RAM with 9-bit write/read.
‡ Refer to User Programmable Features table** ADI, ADO are required to share I/O pins so must be connected to bidirectional pins.
Input
ADI[17:0]** 18-bit data-in to port A.BDI[17:0] 18-bit data-in to port B.ARWL‡ Read/write enable for port A from/to lower 9-bit
location of memory. By default, when ARWL is low,the function is write enable; when ARWL is high, thefunction is read enable.
ARWH‡ Read/write enable for port A from/to upper 9-bitlocation of memory. By default, when ARWH is low,the function is write enable; when ARWH is high, thefunction is read enable.
BRWL Read/write enable for port B from/to lower 9-bitlocation of memory. By default, when BRWL is low,the function is write enable; when BRWL is high, thefunction is read enable.
BRWH Read/write enable for port B from/to upper 9-bitlocation of memory. By default, when BRWH is low,the function is write enable; when BRWH is high, thefunction is read enable.
AA[6:0] Memory address to port A.BA[6:0] Memory address to port B.ACS‡ Chip select to port A. By default, ACS is active low.
When ACS is active, port A of RAM responds toread/write enable.
BCS Chip select to port B. By default, BCS is active low.When BCS is active, port B of RAM responds toread/write enable.
Output
ADO[17:0]** 18-bit data-out from port A.BDO[17:0] 18-bit data-out from port B.
ADI0ADI1ADI2ADI3ADI4ADI5ADI6ADI7ADI8ADI9ADI10ADI11ADI12ADI13ADI14ADI15
ARWH
AA0AA1AA2AA3AA4AA5AA6
ACS
ADI16ADI17
BCS
BA0BA1BA2BA3BA4BA5BA6
BDI0BDI1BDI2BDI3BDI4BDI5ADI6BDI7BDI8BDI9BDI10BDI11BDI12BDI13BDI14BDI15BDI16BDI17
BRWH
ADO0ADO1ADO2ADO3ADO4ADO5ADO6ADO7ADO8ADO9
ADO10ADO11ADO12ADO13ADO14ADO15ADO16ADO17
RAM8
ARWL
BRWL
BDO0BDO1BDO2BDO3BDO4BDO5BDO6BDO7BDO8BDO9
BDO10BDO11BDO12BDO13BDO14BDO15BDO16BDO17
Macro Library Reference Manual 432
RAM8
† Refer to the section on Control Blocks for functionality
ProgrammablePin
Control BlockAttached Description
ACS POLCTRL2† Polarity controlled by POL_CHS, which has adefault value of high.
ARWL POLCTRL1† Polarity controlled by POL_WRL, which has adefault value of high.
ARWH POLCTRL2† Polarity controlled by POL_WRH, which has adefault value of high.
Macro Library Reference Manual 433
RAM9
Availability: RAM9 is for ispDS+ only.
Description: Two 256 x 9, single port RAM.
‡ Refer to User Programmable Features table** ADI, ADO are required to share I/O pins so must be connected
to bidirectional pins.
Input
ADI[8:0]** 9-bit data-in to port A.BDI[8:0] 9-bit data-in to port B.ARWL‡ Read/write enable for port A. By default, when
ARWL is low, the function is write enable; whenARWL is high, the function is read enable.
BRWL Read/write enable for port B. By default, whenBRWL is low, the function is write enable; whenBRWL is high, the function is read enable.
AA[7:0] Memory address to port A.BA[7:0] Memory address to port B.ACS‡ Chip select to port A. By default, ACS is active low.
When ACS is active, port A of RAM responds toread/write enable.
BCS Chip select to port B. By default, BCS is active low.When BCS is active, port B of RAM responds toread/write enable.
Output
ADO[8:0]** 9-bit data-out from port A.BDO[8:0] 9-bit data-out from port B.
ADI0ADI1ADI2ADI3ADI4ADI5ADI6ADI7ADI8
ARWL
AA0AA1AA2AA3AA4AA5AA6AA7
BCS
ADO0ADO1ADO2ADO3ADO4ADO5ADO6ADO7ADO8
RAM9
ACS
BDI0BDI1BDI2BDI3BDI4BDI5BDI6BDI7BDI8
BA0BA1BA2BA3BA4BA5BA6BA7
BRWL
BDO0BDO1BDO2BDO3BDO4BDO5BDO6BDO7BDO8
Macro Library Reference Manual 434
RAM9
† Refer to the section on Control Blocks for functionality
ProgrammablePin
Control BlockAttached Description
ACS POLCTRL2† Polarity controlled by POL_CHS, which has adefault value of high.
ARWL POLCTRL2† Polarity controlled by POL_WRL, which has adefault value of high.
Macro Library Reference Manual 435
RAM10
Availability: RAM10 is for ispDS+ only.
Description: 256 x 18, dual port RAM with port A and B.
‡ Refer to User Programmable Features table** ADI, ADO are required to share I/O pins so must be connected
to bidirectional pins.
Input
ADI[17:0]** 18-bit data-in to port A.BDI[17:0] 18-bit data-in to port B.ARW‡ Read/write enable for port A. By default, when ARW
is low, the function is write enable; when ARW ishigh, the function is read enable.
BRW Read/write enable for port B. By default, when BRWis low, the function is write enable; when BRW ishigh, the function is read enable.
AA[7:0] Address to port A.BA[7:0] Address to port B.ACS‡ Chip select to port A. By default, ACS is active low.
When ACS is active, port A of RAM responds toread/write enable.
BCS Chip select to port B. By default, BCS is active low.When BCS is active, port B of RAM responds toread/write enable.
Output
ADO[17:0]** 18-bit data-out to port A.BDO[17:0] 18-bit data-out to port B.ABUSY Busy flag from port A. Active high. Becomes active
when the same address is used by port B.BBUSY Busy flag from port B. Active high. Becomes active
when the same address is used by port A.
ADI0ADI1ADI2ADI3ADI4ADI5ADI6ADI7ADI8ADI9ADI10ADI11ADI12ADI13ADI14ADI15
ARW
AA0AA1AA2AA3AA4AA5AA6
ACS
ADI16ADI17
BCS
BA0BA1BA2BA3BA4BA5BA6
BDI0BDI1BDI2BDI3BDI4BDI5ADI6BDI7BDI8BDI9BDI10BDI11BDI12BDI13BDI14BDI15BDI16BDI17
BRW
ADO0ADO1ADO2ADO3ADO4ADO5ADO6ADO7ADO8ADO9
ADO10ADO11ADO12ADO13ADO14ADO15ADO16ADO17
RAM10
BDO0BDO1BDO2BDO3BDO4BDO5BDO6BDO7BDO8BDO9
BDO10BDO11BDO12BDO13BDO14BDO15BDO16BDO17
AA7
BA7
ABUSY
BBUSY
Macro Library Reference Manual 436
RAM10
† Refer to the section on Control Blocks for functionality
ProgrammablePin
Control BlockAttached Description
ACS POLCTRL2† Polarity controlled by POL_CHS, which has adefault value of high.
ARWL POLCTRL2† Polarity controlled by POL_WRL, which has adefault value of high.
Macro Library Reference Manual 437
RAM11
Availability: RAM11 is for ispDS+ only.
Description: 256 x 18, dual port RAM with 9-bit write/read.
‡ Refer to User Programmable Features table** ADI, ADO are required to share I/O pins so must be connected to bidirectional pins.
Input
ADI[17:0]** 18-bit data-in to port A.BDI[17:0] 18-bit data-in to port B.ARWL‡ Read/write enable for port A from/to lower 9-bit
location of memory. By default, when ARWL is low,the function is write enable; when ARWL is high, thefunction is read enable.
ARWH‡ Read/write enable for port A from/to upper 9-bitlocation of memory. By default, when ARWH is low,the function is write enable; when ARWH is high, thefunction is read enable.
BRWL Read/write enable for port B from/to lower 9-bitlocation of memory. By default, when BRWL is low,the function is write enable; when BRWL is high, thefunction is read enable.
BRWH Read/write enable for port B from/to upper 9-bitlocation of memory. By default, when BRWH is low,the function is write enable; when BRWH is high, thefunction is read enable.
AA[7:0] Memory address to port A.BA[7:0] Memory address to port B.ACS‡ Chip select to port A. By default, ACS is active low.
When ACS is active, port A of RAM responds toread/write enable.
BCS Chip select to port B. By default, BCS is active low.When BCS is active, port B of RAM responds toread/write enable.
Output
ADO[17:0]** 18-bit data-out to port A.BDO[17:0] 18-bit data-out to port B.ABUSY Busy flag from port A. Active high. Becomes active
when the same address is used by port B.BBUSY Busy flag from port B. Active high. Becomes active
when the same address is used by port A.
ADI0ADI1ADI2ADI3ADI4ADI5ADI6ADI7ADI8ADI9ADI10ADI11ADI12ADI13ADI14ADI15
BRWH
AA0AA1AA2AA3AA4AA5AA6
ACS
ADI16ADI17
BCS
BA0BA1BA2BA3BA4BA5BA6
BDI0BDI1BDI2BDI3BDI4BDI5ADI6BDI7BDI8BDI9BDI10BDI11BDI12BDI13BDI14BDI15BDI16BDI17ARWL
ADO0ADO1ADO2ADO3ADO4ADO5ADO6ADO7ADO8ADO9
ADO10ADO11ADO12ADO13ADO14ADO15ADO16ADO17
RAM11
BDO0BDO1BDO2BDO3BDO4BDO5BDO6BDO7BDO8BDO9
BDO10BDO11BDO12BDO13BDO14BDO15BDO16BDO17
AA7
BA7
ABUSY
BBUSY
ARWHBRWL
Macro Library Reference Manual 438
RAM11
† Refer to the section on Control Blocks for functionality
ProgrammablePin
Control BlockAttached Description
ACS POLCTRL2† Polarity controlled by POL_CHS, which has adefault value of high.
ARWH POLCTRL2† Polarity controlled by POL_WRL, which has adefault value of high.
ARWL POLCTRL1† Polarity controlled by POL_WRH, which has adefault value of high.
Macro Library Reference Manual 439
RAM12
Availability: RAM12 is for ispDS+ only.
Description: 512 x 9 dual port RAM.
‡ Refer to User Programmable Features table** ADI, ADO are required to share I/O pins so must be connected to bidirectional pins.
Input
ADI[8:0]** 9-bit data-in to port A.BDI[8:0] 9-bit data-in to port B.ARWL‡ Read/write enable for port A. By default, when
ARWL is low, the function is write enable; whenARWL is high, the function is read enable.
BRWL Read/write enable for port B. By default, whenBRWL is low, the function is write enable; whenBRWL is high, the function is read enable.
AA[8:0] Memory address to port A.BA[8:0] Memory address to port B.ACS‡ Chip select to port A. By default, ACS is active low.
When ACS is active, port A of RAM responds toread/write enable.
BCS Chip select to port B. By default, BCS is active low.When BCS is active, port B of RAM responds toread/write enable.
Output
ADO[8:0]** 9-bit data-out from port A.BDO[8:0] 9-bit data-out from port B.ABUSY Busy flag from port A. Active high. Becomes active
when the same address is used by port B.BBUSY Busy flag from port B. Active high. Becomes active
when the same address is used by port A.
ADI0ADI1ADI2ADI3ADI4ADI5ADI6ADI7ADI8
ARWL
AA0AA1AA2AA3AA4AA5AA6AA7
BCS
ADO0ADO1ADO2ADO3ADO4ADO5ADO6ADO7ADO8
RAM12
ACS
BDI0BDI1BDI2BDI3BDI4BDI5BDI6BDI7BDI8
BA0BA1BA2BA3BA4BA5BA6BA7
BRWL BDO0BDO1BDO2BDO3BDO4BDO5BDO6BDO7BDO8
BA8
AA8
ABUSY
BBUSY
Macro Library Reference Manual 440
RAM12
† Refer to the section on Control Blocks for functionality
ProgrammablePin
Control BlockAttached Description
ACS POLCTRL2† Polarity controlled by POL_CHS, which has adefault value of high.
ARWL POLCTRL2† Polarity controlled by POL_WRL, which has adefault value of high.
Macro Library Reference Manual 441
FIFO Modules
The FIFO can be configured in two directions: Port A to B, where data flows from the dedicatedFIFO I/O pins to the GRP; and Port B to A, where data flows from the GRP to I/O pins. Accessbetween ports can be asynchronous.
FIFO1
Availability: FIFO1 is for ispDS+ only.
Description: 256 x 18 FIFO from port A to port B.
‡ Refer to User Programmable Features table§ Data-in can only be external input signals. No logic can be connected.
Input
MRST‡ Reset. Active low.ADI[17:0]§ 18-bit data-in at port A.AWR‡ Write enable at port A. Positive edge triggered and
the data at ADI is written into memory.BRD Read enable at port B. Positive edge triggered and
the data from the memory is read into BDO.
Output
BDO[17:0] 18-bit data-out at port B.ALE‡ Almost empty flag. Active high. When the number of
data words stored in the memory is equal to or fallsbelow the preset value, ALE goes high.
ALF‡ Almost full flag. Active high. When the number ofdata words stored in the memory is equal to orexceeds the preset value, ALF goes high.
EF Empty flag. Active low.FF Full flag. Active low.
ADI0ADI1ADI2ADI3ADI4ADI5ADI6ADI7ADI8ADI9ADI10ADI11ADI12ADI13ADI14ADI15
AWR
MRST
BDO0BDO1BDO2BDO3BDO4BDO5BDO6BDO7BDO8BDO9
BDO10BDO11BDO12BDO13BDO14BDO15
ADI16ADI17
BDO16BDO17
FIFO1
BRD
ALE
ALF
EF
FF
Macro Library Reference Manual 442
FIFO1
† Refer to the section on Control Blocks for functionality
ProgrammablePin
Control BlockAttached Description
MRST POLCTRL2† Polarity controlled by POL_RST, which has adefault value of high.
AWR POLCTRL2† Polarity of port A write signal controlled byPOL_WRL, which has a default value of high.
ALE ALECTRL8† Value of almost empty flag is controlled by inputsALEOPT[7:0]; ALEOPT0 is the LSB. Default valueis 63.
ALF ALFCTRL8† Value of almost full flag is controlled by inputsALFOPT[7:0]; ALFOPT0 is the LSB. Default valueis 128.
Macro Library Reference Manual 443
FIFO2
Availability: FIFO2 is for ispDS+ only.
Description: 256 x 18 FIFO from port B to port A.
‡ Refer to User Programmable Features table§§ Data-out can only be external output signals. No logic can be connected.
Input
MRST‡ Reset. Active low.BDI[17:0] 18-bit data-in at port B.ARD‡ Read enable at port A. Positive edge-triggered and
the data from the memory is read into ADO.BWR Write enable at port B. Positive edge-triggered and
the data at BDI is written into memory.
Output
ADO[17:0]§§ 18-bit data-out at port A.ALE‡ Almost empty flag. Active high. When the number of
data words stored in the memory is equal to or fallsbelow the preset value, ALE goes high.
ALF‡ Almost full flag. Active high. When the number ofdata words stored in the memory is equal to orexceeds the preset value, ALF goes high.
EF Empty flag. Active low.FF Full flag. Active low.
BDI0BDI1BDI2BDI3BDI4BDI5BDI6BDI7BDI8BDI9BDI10BDI11BDI12BDI13BDI14BDI15
ARD
MRST
ADO0ADO1ADO2ADO3ADO4ADO5ADO6ADO7ADO8ADO9
ADO10ADO11ADO12ADO13ADO14ADO15
BDI16BDI17
ADO16ADO17
FIFO2
BWR
ALE
ALF
EF
FF
Macro Library Reference Manual 444
FIFO2
† Refer to the section on Control Blocks for functionality
ProgrammablePin
Control BlockAttached Description
MRST POLCTRL2† Polarity controlled by POL_RST, which has adefault value of high.
ARD POLCTRL2† Polarity of port A read signal controlled byPOL_WRL, which has a default value of high.
ALE ALECTRL8† Value of almost empty flag is controlled by inputsALEOPT[7:0]; ALEOPT0 is the LSB. Defaultvalue is 63.
ALF ALFCTRL8† Value of almost full flag is controlled by inputsALFOPT[7:0]; ALFOPT0 is the LSB. Default valueis 128.
Macro Library Reference Manual 445
FIFO3
Availability: FIFO3 is for ispDS+ only.
Description: 512 x 9 FIFO from port A to port B.
‡ Refer to User Programmable Features table§ Data-in can only be external input signals. No logic can be connected.
Input
MRST‡ Reset. Active low.ADI[8:0] 9-bit data-in at port A.AWRL‡ Write enable at port A. Positive edge-triggered and
the data at ADI is written into memory.BRDL Read enable at port B. Positive edge-triggered and
the data from the memory is read into BDO.
Output
BDO[8:0] 9-bit data-out at port B.ALE‡ Almost empty flag. Active high. When the number of
data words stored in the memory is equal to or fallsbelow the preset value, ALE goes high.
ALF‡ Almost full flag. Active high. When the number ofdata words stored in the memory is equal to orexceeds the preset value, ALF goes high.
EF Empty flag. Active low.FF Full flag. Active low.
ADI0ADI1ADI2ADI3ADI4ADI5ADI6ADI7ADI8
AWRL
MRST
BDO0BDO1BDO2BDO3BDO4BDO5BDO6BDO7BDO8
FIFO3
BRDLALF
ALE
EF
FF
Macro Library Reference Manual 446
FIFO3
† Refer to the section on Control Blocks for functionality
ProgrammablePin
Control BlockAttached Description
MRST POLCTRL2† Polarity of module reset controlled by POL_RST,which has a default value of high.
AWRL POLCTRL2† Polarity of port A write signal controlled byPOL_WRL, which has a default value of high.
ALE ALECTRL9† Value of ALE flag is controlled by inputsALEOPT[8:0]; ALEOPT0 is the LSB. Defaultvalue is 63.
ALF ALFCTRL9† Value of ALF flag is controlled by inputsALFOPT[8:0]; ALFOPT0 is the LSB. Defaultvalue is 384.
Macro Library Reference Manual 447
FIFO4
Availability: FIFO4 is for ispDS+ only.
Description: 512 X 9 FIFO from port B to port A.
‡ Refer to User Programmable Features table§§ Data-out can only be external output signals. No logic can be connected.
Input
MRST‡ Reset. Active low.BDI[8:0] 9-bit data-in at port B.ARDL‡ Read enable at port B. Positive edge-triggered
and the data from the memory is read into ADO.BWRL Write enable at port A. Positive edge-triggered
and the data at BDI is written into memory.
Output
ADO[8:0]§§ 9-bit data-out at port A.ALE‡ Almost empty flag. Active high. When the number
of data words stored in the memory is equal to orfalls below the preset value, ALE goes high.
ALF‡ Almost full flag. Active high. When the number ofdata words stored in the memory is equal to orexceeds the preset value, ALF goes high.
EF Empty flag. Active low.FF Full flag. Active low.
BDI0BDI1BDI2BDI3BDI4BDI5BDI6BDI7BDI8
ARDL
MRST
ADO0ADO1ADO2ADO3ADO4ADO5ADO6ADO7ADO8
FIFO4
BWRL
ALEALF
EF
FF
Macro Library Reference Manual 448
FIFO4
† Refer to the section on Control Blocks for functionality
ProgrammablePin
Control BlockAttached Description
MRST POLCTRL2† Polarity of module reset controlled by POL_RST,which has a default value of high.
ARDL POLCTRL2† Polarity of port A read signal controlled byPOL_WRL, which has a default value of high.
ALE ALECTRL9† Value of ALE flag is controlled by inputsALEOPT[8:0]; ALEOPT0 is the LSB. Defaultvalue is 63.
ALF ALFCTRL9† Value of ALF flag is controlled by inputsALFOPT[8:0]; ALFOPT0 is the LSB. Default valueis 384.
Macro Library Reference Manual 449
Register File Modules
PSSR8X16
Availability: PSSR8X16 is for ispDS+ only.
Description: Parallel to serial, 8-bank, 16-bit shift register.
‡ Refer to User Programmable Features table
Input
MRST Module reset input. Resets the register value tozero when active high.
DI[15:0] 16-bit parallel data-in.BS[2:0] Bank select input.SEN Serial shift enable input signal. When active high,
serially shifts the data through the data registerswith LSB being the first output.
CLK Bank clock input.EN‡ Parallel data load enable input. Loads the DI[15:0]
value into the bank selected by BS[2:0] when activehigh. It has a higher priority than SEN (serial shiftenable) input when both are active high.
Output
SDO Serial data-out. If data-in shifted into bank 0, theoutput can be observed exactly after 7x16 clockpulses with LSB being the first output.
DI0DI1DI2DI3DI4DI5DI6DI7DI8DI9DI10DI11DI12DI13DI14DI15
BS0BS1BS2
SEN
CLK
MRST
EN
SDO
PSSR8X16
Macro Library Reference Manual 450
PSSR8x16
† Refer to the section on Control Blocks for functionality
ProgrammablePin
Control BlockAttached Description
EN POLCTRL1† Polarity controlled by POLEN, which has adefault value of high.
Macro Library Reference Manual 451
SSSR128
Availability: SSSR128 is for ispDS+ only.
Description: Serial to serial, 8-bank, 16-bit shift register.
Input
MRST Module reset input. Resets the register value tozero when active high.
SDI Serial data-in.CLK Bank clock input.SEN Serial shift enable input signal. When active high,
serially shifts the data through the data registerswith LSB being the first output.
Output
SDO Serial data-out. If data-in shifted into bank 0, theoutput can be observed exactly after 7x16 clockpulses with LSB being the first output.
SDI
CLK
MRST
SEN
SDO
SSSR128
Macro Library Reference Manual 452
SPSR8X16
Availability: SPSR8X16 is for ispDS+ only.
Description: Serial to parallel, 8-bank, 16-bit shift register.
Input
MRST Module reset input. Resets the register value tozero when active high.
SDI Serial data-in.BS[2:0] Bank select input.CLK Bank clock input.SEN Serial shift enable input signal. When active high,
serially shifts the data through the data registerswith LSB being the first output.
Output
DO[15:0] Parallel data-out.
SDI
BS0BS1BS2
CLK
MRST
SEN
DO0DO1DO2DO3DO4DO5DO6DO7DO8DO9
DO10DO11DO12DO13DO14DO15
SPSR8X16
Macro Library Reference Manual 453
RF8X16
Availability: RF8X16 is for ispDS+ only.
Description: Parallel to parallel, 8-bank, 16-bit shift register.
‡ Refer to User Programmable Features table
RF8x16
† Refer to the section on Control Blocks for functionality
Input
MRST Module reset input. Resets the register value tozero when active high.
DI[15:0] 16-bit parallel data-in.BS[2:0] Bank select input.B[0:7]CLK Bank clock input.EN‡ Parallel data-in load enable input. When active
high loads the DI[15:0] values into the bankselected by BS[2:0].
Output
DO[15:0] Parallel data-out.
ProgrammablePin
Control BlockAttached Description
EN POLCTRL1† Polarity controlled by POLEN, whichhas a default value of high.
DI0DI1DI2DI3DI4DI5DI6DI7DI8DI9DI10DI11DI12DI13DI14DI15
BS0BS1BS2
B0CLKB1CLKB2CLKB3CLKB4CLKB5CLKB6CLKB7CLK
MRST
EN
DO0DO1DO2DO3DO4DO5DO6DO7DO8DO9
DO10DO11DO12DO13DO14DO15
RF8X16
Macro Library Reference Manual 454
Index
AADDF1 50ADDF16A 50ADDF2 50ADDF4 50ADDF8 50ADDF8A 50ADDH16A 65ADDH2 65ADDH3 65ADDH4 65ADDH8 65ADDH8A 65ALECTRL 406ALECTRL8 406ALFCTRL8 407ALFCTRL9 407AND2 Through AND18 328Arithmetic Functions 49
BBI11 296BI14 296BI18 296BI21 297BI24 297BI28 297BI31 298BI34 298BI38 298BI41 299BI44 299BI48 299Bidirectional Pins 296BIID11 300BIID14 300BIID18 300BIID21 301BIID24 301BIID28 301BIID31 302BIID34 302
BIID38 302BIID41 303BIID44 303BIID48 303BIID51 304BIID54 304BIID58 304BIID61 305BIID64 305BIID68 305BIID71 306BIID74 306BIID78 306BIID81 307BIID84 307BIID88 307BIIL11 308BIIL14 308BIIL18 308BIIL21 309BIIL24 309BIIL28 309BIIL31 310BIIL34 310BIIL38 310BIIL41 311BIIL44 311BIIL48 311BIIL51 312BIIL54 312BIIL58 312BIIL61 313BIIL64 313BIIL68 313BIIL71 314BIIL74 314BIIL78 314BIIL81 315BIIL84 315BIIL88 315BIN27 116Binary Counters 125BUF 329
Macro Library Reference Manual 455
Index
CC4R4AL 411C4R4PL 413CAOCTRL 410CBD11 125CBD12 125CBD14 125CBD18 125CBD21 131CBD22 131CBD24 131CBD28 131CBD31 137CBD32 137CBD34 137CBD38 137CBD41 144CBD42 144CBD44 144CBD48 144CBD516 151CBD616 151CBU11 161CBU12 161CBU14 161CBU18 161CBU21 167CBU22 167CBU24 167CBU28 167CBU31 173CBU32 173CBU34 173CBU38 173CBU41 180CBU42 180CBU44 180CBU48 180CBU516 187CBU616 187CBU716 196CBUD1 202CBUD2 202CBUD4 202CBUD8 202CDD14 212CDD18 212CDD24 218CDD28 218CDD34 224
CDD38 224CDD44 230CDD48 230CDU14 234CDU18 234CDU24 240CDU28 240CDU34 246CDU38 246CDU44 252CDU48 252CDUD4 258CDUD4c 268CDUD8 258CDUD8c 268CGD14 278CGD24 281CGU14 284CGU24 288CGUD4 291CMP2 78CMP4 78CMP8 78Coders 115Comparators 78Control Blocks 406Counters 124
DD Flip-flops 359D Latches 373DEC2 118DEC2E 118DEC3 119DEC3E 119DEC4 120DEC4E 120Decade Counters 234Decoders 116Demultiplexers 351DMUX2 351DMUX22 353DMUX22E 353DMUX24 354DMUX24E 354DMUX2E 351DMUX4 352DMUX42 355DMUX42E 355DMUX44 356
Macro Library Reference Manual 456
Index
DMUX44E 356DMUX4E 352DMUX82 357DMUX82E 357Documentation Conventions 10
EEncoders 121
FF3ADD 50F3SUB 91FD11 359FD14 359FD18 359FD21 360FD24 360FD28 360FD31 361FD34 361FD38 361FD41 362FD44 362FD48 362FD51 363FD54 363FD58 363FD61 364FD64 364FD68 364FD71 365FD74 365FD78 365FD81 366FD84 366FD88 366FD91 367FD94 367FD98 367FDA1 368FDA4 368FDA8 368FIFO Modules 442FIFO1 442FIFO2 444FIFO3 446FIFO4 448FJK11 369FJK21 369FJK31 370
FJK41 370FJK51 371FT11 372FT21 372
GGrey Code Counters 278
II/O Pins 295IB11 316ID11 317ID14 317ID18 317ID21 318ID24 318ID28 318IL11 319IL14 319IL18 319IL21 320IL24 320IL28 320Input Pins 316INV 329
JJK Flip-flops 369
LLD11 373LD14 373LD18 373LD21 374LD24 374LD28 374LD31 375LD34 375LD38 375LD41 376LD44 376LD48 376LD51 377LD54 377LD58 377LD61 378LD64 378LD68 378LD71 379
Macro Library Reference Manual 457
Index
LD74 379LD78 379LD81 380LD84 380LD88 380LD91 381LD94 381LD98 381LDA1 382LDA4 382LDA8 382Logic Gates 327, 328Logic Resources 15LSR1 383LSR2 383LXOR 334
MMacro Table, Quick Reference 17MAG2 79MAG4 79MAG8 79Module Macro Truth Tables 13MULT24 81MULT44 81Multiplexers 336Multipliers 81MUX/DMUX 335MUX16 339MUX16E 339MUX2 336MUX22 343MUX22E 343MUX24 344MUX24E 344MUX2E 336MUX4 337MUX42 345MUX42E 345MUX44 346MUX44A 349MUX44AE 349MUX44E 346MUX4E 337MUX8 338MUX82 350MUX82E 350MUX8E 338
NNAND16 330NAND2 Through NAND12 330NOR16 331NOR2 Through NOR12 331
OOB11 321OB21 322OB24 322OB28 322OR16 332OR2 Through OR12 332OT11 323OT14 323OT18 323OT21 324OT24 324OT28 324OT31 325OT34 325OT38 325OT41 326OT44 326OT48 326Output Pins 321Overview 8
PPG1 85PG2 85PG3 85PG4 85Pin Labeling 14POLCTRL 409Preface 8PREN10 122PREN10E 122PREN16 123PREN16E 123PREN8 121PREN8E 121Programmable Macro Reference 46Propagate-Generate 85PSCTRL 408PSSR8X16 450Purpose and Scope 9
Macro Library Reference Manual 458
Index
RRAM Modules 421RAM1 421RAM10 436RAM11 438RAM12 440RAM2 423RAM3 424RAM4 426RAM5 427RAM6 429RAM7 430RAM8 432RAM9 434Register File Modules 450Registers 358RF8X16 454
SShift Registers 384Signal Names 10SPSR8X16 453SR Latches 383SRR11 384SRR14 384SRR18 384SRR21 388SRR24 388SRR28 388SRR31 392SRR34 392SRR38 392SRR41 396SRR44 396SRR48 396SRRL1 400SRRL4 400SRRL8 400SSSR128 452SUBF1 91SUBF16A 91SUBF2 91SUBF4 91SUBF8 91SUBF8A 91
SUBH1 102SUBH16A 102SUBH2 102SUBH3 102SUBH4 102SUBH8 102SUBH8A 102Subtractors 91
TT4R4AL 415T4R4CPV 419T4R4PL 417Timer/Counter Modules 411Toggle Flip-flops 372Truth Tables 12
UUsing the NOMIN Attribute 16
XXNOR2 333XNOR3 333XNOR4 333XNOR7 333XNOR8 333XNOR9 333XOR2 334XOR3 334XOR4 334XOR8 334XOR9 334
Macro Library Reference Manual 459