Low Power Solutions: A System Design Perspective

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Low Power Solutions: A System Design Perspective. Nik Sumikawa. Low Power: Why?. 1. Standard Embedded Solutions. 2. 3. 3. Innovative Solutions. 4. 4. Solutions for Mobile Platforms. Contents. Low Power: Why?. Power vs. Performance Technology Scaling VLSI Embedded Technology Trend - PowerPoint PPT Presentation

Transcript of Low Power Solutions: A System Design Perspective

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Low Power Solutions:A System Design Perspective

Nik Sumikawa

Nik Sumikawa

Contents

Low Power: Why?1

Standard Embedded Solutions2

Innovative Solutions33

Solutions for Mobile Platforms44

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Low Power: Why?Power vs. Performance

Technology Scaling VLSI Embedded

Technology Trend Green Stimulus Scaling Size

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What You Should Think AboutLow power design strategies

Components: Microcontrollers, peripherals, ect.

Low power design with hardware Low power design with software Low power design in mobile device

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Low Power Embedded Systems

TELOS: Low power wireless

embedded system Low duty cycle

principle Minimizes dynamic

power consumption

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Nik Sumikawa

Low Duty Cycle Principle

WakeUp

Process

SleepPrepDeep

Sleep

Sleep Mode

Timer or Interrupt event

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Low Duty CycleLow processing to sleep ratio

Extended sleep period

Responsively: fast wake-up and sleep times

Minimize Interrupts: Context switching overhead

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Low Duty Cycle: DMADirect Memory Access (DMA):

Controls bus and transfers data with minimal processor overhead

Significance Transfer data while sleeping Minimize processor overhead

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Low Duty CycleFails with significant

processing

Alternatives: Dynamic Voltage and

Frequency Scaling (DVFS)

Dynamic Power Management (DPM)

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Image: http://www.domainmagnate.com/wp-content/uploads/2009/03/failure-success.jpg

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Dynamic Power

DynamicPower

P = CVdd2f

Capacitance

Frequency

Voltage

Energy Source

Battery

Design Variables

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Reducing Dynamic Power

Dynamic Voltage and Frequency Scaling Scale voltage when sleeping/Idle

Voltage term quad. proportional to power Reduce frequency Minimize line capacitance

Long traces have large capacitance

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Dynamic Power Management

Generalize power management

Multiple policies Single-policy Multiple-policy Task-scaling

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Rajami and Brock [2]

Single-policy StrategyIdle Scaling (IS)

Operate at full speed when processing workload

Reduce the frequency and voltage when idleGoal:

Reduce the CPU and bus frequencies Meet continuous DMA requirements Provide acceptable latency when resuming

from idle

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Rajami and Brock [2]

Multi-policy StrategiesLoad scaling (LS):

Balance system operating point with current or predicted processing demands

Run system with minimal idle timeOther:

Manage systems state based on status of the systems energy source

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Rajami and Brock [2]

Task-scaling StrategiesApplication scaling (AS):

Used for workloads that are difficult to power manage• Audio and video processing• Begin processing next sample immediately

Operate a lower operating point Increases to higher operating point when it

begins to fall behind.

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Rajami and Brock [2]

Results of DPM

IS: Idle Scaling LS: Load Scaling AS: Application Scaling

Frame-Scaling (FS): perfect knowledge of processing requirements of video frame

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Rajami and Brock [2]

Too Many Low Power States

Disadvantages: Confusion Wrong low power

state

Solution: Minimize the number

of state Decrease complexity

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Image: http://kunaljanu.files.wordpress.com/2009/02/ ist2_1457667confusion-1.jpg

Sources of Power ConsumptionMicrocontrollerBus architecture

On chip communication External communication

Memory hierarchyPeripherals

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Rajami and Brock [2]

Communication ArchitecturesAdvanced Microcontroller Bus Architecture

ARM bus protocol for system-on-a-chip (SOC) Advanced High Performance Bus (AHB)

• Pipelined• Memory mapped• Up to 16 masters, 16 slaves

Advanced Peripheral Bus (APB)• Non pipelined• Single master, up to 16 peripherals

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Rajami and Brock [2]

AMBA On-chip BusNik Sumikawa

Rajami and Brock [2]

Power ProfilingNik Sumikawa

Rajami and Brock [2]

86% power consumed by logic14% power consumed by bus lines

Power Reduction TechniquesPower Management

Shut down bus interfaces to idle slavesBus Encoding

Reduces # of line transitions, but not bus transactions

Traffic Sequencing Reduce multiple masters interleaving bus

access

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Rajami and Brock [2]

Power Reduction TechniquesNik Sumikawa

Rajami and Brock [2]

No technique achieves large saving alone

Power vs EnergyPower is amount of energy over an

amount of time (Watts = Joules / second)Battery provides finite amount of energy

Goal: minimize energy use, not just powerIn mobile systems we care about energy

Budget energy to prolong battery life

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Rajami and Brock [2]

Static System OptimizationCompiler techniques

Instruction energy consumption profiling• Done empirically

Instruction reordering• Without affecting correctness• Improve register utilization• Reduce memory accesses• Reduce pipeline stalls

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Static System OptimizationCode Compression

Post compilation static optimization Reduces storage size of instructions Can have a large impact Requires complex design space exploration Goal for mobile system: reduce power

consumption while preserving performance

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Code Compression ChallengesRandom access decompression

Defining decodable block beginnings Jump to new locations in program without

decoding all blocks betweenSolutions

Begin compressed blocks on byte boundaries Store translation table

• More efficient the compression, larger the table Recalculate branch offsets to compressed

addresses

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Code Compression RequirementsAdditional hardware

Additional memory to store table Decompression unit

Design decisions Table generation/lookup Compression technique

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Code Compression ImplementationSPARC ISAOptimize consumption of complete SOCMultiple iterations on binaryInstructions split into 4 categories

Group 1: immediate instructions (code = 0) Group 2: branch instructions (code = 11) Group 3: dictionary instructions (code = 100) Group 4: uncompressed instr (code = 101)

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Diagram

Optimized Binary

CompiledBinary

Update branch offsets

Branch compression

Markov model

Phase 4

Phase 3Immediate compression

Phase 2

Phase 1

As a Result…Bus Compaction

Instructions transmitted no longer require entire bus

Use the extra lines to transmit the next compressed instruction

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Decompression ArchitecturePre-Cache

Decompression engine between memory/cache

Post-Cache Decompression engine between cache/cpu

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SimulationFull SOC simulation7 sample apps run

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ResultsNik Sumikawa

INCLUDE?Nik Sumikawa

ResultsNet energy saving observed

22-82% power savings from code compression

What about additional hardware?Bonus

Increased performance Reduced area

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VerdictStatic power optimization

Potentially large payoff for little preprocessingStill more sources of consumption

We’ve observed SOC savings What about peripherals?

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Energy Budget

Voice Call

SMS

Emails

Pictures

localization

Energy Budget

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Energy Budget: Localization

How much of the energy budget should be given to localization? Depends on the user

Grant increase allotment when localization is a higher priority

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Localizations Methods

1

GPS• Very accurate• Power

Hungry

2

GSM• Lower accuracy• Lower power

requirement

3

WiFi• Mod. Accurate• Mod. Power

requirement

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Constandache, Gaonkar, Sayler, Choudhury, Cox [3]

Power vs. Precision

Power: amount of energy required by peripheral in order to determine location

Localization

Precision:Accuracy of the device used for localization

Power Consumptionwww.themegallery.com

Constandache, Gaonkar, Sayler, Choudhury, Cox [3]

30 Second sampling intervals

Power Consumption: GPS: High baseline WiFi: Low baseline with high spikes GSM: Low baseline with varying spikes

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Power Consumptionwww.themegallery.com

30 Second sampling intervals

Results: GPS: increased

baseline

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Localization Accuracy

Accuracy varied based on location

ALE: Average Location Error

Wifi and GSM oversampled

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