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ECE C03 Lecture 8 1
Lecture 8Memory Elements and Clocking
Hai Zhou
ECE 303
Advanced Digital Design
Spring 2002
ECE C03 Lecture 8 2
Outline
• Sequential logic networks• Latches (RS Latch)• Flip-flops (D and JK)• Timing issues (setup and hold times)• READING: Katz 6.1, 6.2, 6.3, Dewey 8.1, 8.2
3
Sequential Switching Networks
Circuits with Feedback:
Outputs values (in the steady state) depend not only on the present input values but also on the history of previous inputs.
=> Needs storage elements (or mechanism) to memorize the history.
Traffic Light Controller is a complex sequential logic network
Sequential logic forms basis for building "memory" into circuits
These memory elements are primitive sequential circuits
ECE C03 Lecture 8 4
Simple Circuits with Feedback
Primitive memory elements created from cascaded gates
Simplest gate component: inverter
Basis for commercial static RAM designs
Cross-coupled NOR gates and NAND gates also possible
Cascaded Inverters: Static Memory Cell"0"
"1"
Selectively break feedback path to load new value into cell
Z
LD
\LD
LD
\LD
A
ECE C03 Lecture 8 5
100
R
S
Q
\ Q
RS LatchJust like cascaded inverters,
with capability to force outputto 0 (reset) or 1 (set)
Timing Waveform
Reset Hold Set
ForbiddenState
Reset Set
ForbiddenState
Race
R
R
S
S
Q
\Q
ECE C03 Lecture 8 6
State Behavior of RS Latch
Truth Table Summary of R-S Latch Behavior
Q Q Q Q
Q Q
0 1 1 0
0 0
Q Q1 1
Q
hold 0 1
unstable
S
0 0 1 1
R
0 1 0 1
ECE C03 Lecture 8 7
Theoretical RS Latch State Diagram
Q Q Q Q
Q Q
0 1 1 0
0 0
SR = 1 0
SR = 0 1
SR = 0 1
SR = 1 1
SR = 1 0
SR = 1 1
SR = 00, 01 SR = 00, 10
Q Q1 1
SR = 0 0
SR = 0 0, 11
SR = 11
SR = 1 0SR = 0 1
ECE C03 Lecture 8 8
Observed RS Latch Behavior
Q Q Q Q
Q Q
0 1 1 0
0 0
SR = 1 0
SR = 0 1
SR = 0 1
SR = 1 1
SR = 1 0
SR = 1 1
SR = 00, 01 SR = 00, 10
SR = 0 0
SR = 11
SR = 0 0
Very difficult to observe R-S Latch in the 1-1 state
Ambiguously returns to state 0-1 or 1-0
A so-called "race condition"
ECE C03 Lecture 8 9
Input
Clock
T su T h
Definition of Terms in Clocking
Setup Time (Tsu)
Clock: Periodic Event, causes state of memory element to change
rising edge, falling edge, high level, low level
There is a timing "window" around the
clocking event during which the input
must remain stable and unchanged
in order to be recognized
There is a timing "window" around the
clocking event during which the input
must remain stable and unchanged
in order to be recognized
Minimum time before the clocking event by which the input must be stable
Hold Time (Th)Minimum time after the clocking event during which the input must remain stable
ECE C03 Lecture 8 10
Level Sensitive RS LatchLevel-Sensitive Latch
\ S
\ R
\ Q
Q
\enb
Schematic:
Timing Diagram:
aka Gated R-S Latch
\S
\R
\enb
Q\Q
Level-Sensitive D-Latch
• Make level-sensitive D-latch from level-sensitive RS-latch by connecting S = D and R = not D
• Compared to transistor version
D
Q
Q
CLK
CLK
CLK
D QCLK
CLK 8 Transistors
18 Transistors
ECE C03 Lecture 8 12
Latches vs Flip-flops
Input/Output Behavior of Latches and Flipflops
Type When Inputs are Sampled When Outputs are Validunclocked always propagation delay from latch input change
level clock high propagation delay fromsensitive (Tsu, Th around input changelatch falling clock edge)
positive edge clock lo-to-hi transition propagation delay fromflipflop (Tsu, Th around rising edge of clock rising clock edge)
negative edge clock hi-to-lo transition propagation delay fromflipflop (Tsu, Th around falling edge of clock falling clock edge)
master/slave clock hi-to-lo transition propagation delay fromflipflop (Tsu, Th around falling edge of clock falling clock edge)
ECE C03 Lecture 8 13
Latches vs Flipflops7474
7476
Bubble herefor negative
edge triggereddevice
Timing Diagram:
Behavior the same unless input changes while the clock is high
Edge triggered device sample inputs on the event edge
Transparent latches sample inputs as long as the clock is assertedPositive edge-triggered
flip-flop
Level-sensitive latch
D Q
D Q
C
Clk
Clk
D
Clk
Q
Q
7474
7476
ECE C03 Lecture 8 14
Timing Specifications of FFs74LS74 PositiveEdge Triggered
D Flipflop
• Setup time• Hold time• Minimum clock width• Propagation delays (low to high, high to low, max and typical)
All measurements are made from the clocking eventthat is, the rising edge of the clock
D
Clk
Q
T su 20 ns
T h 5
ns
T w 25 ns
T plh 25 ns 13 ns
T su 20 ns
T h 5
ns
T phl 40 ns 25 ns
ECE C03 Lecture 8 15
Timing Specifications of Latches
74LS76TransparentLatch
• Setup time• Hold time• Minimum Clock Width• Propagation Delays: high to low, low to high, maximum, typical data to output clock to output
Measurements from falling clock edgeor rising or falling data edge
T su 20 ns
T h 5
ns
T su 20 ns
T h 5
ns
T w 20 ns
T plh C » Q 27 ns 15 ns
T phl C » Q 25 ns 14 ns
T plh D » Q 27 ns 15 ns
T phl D » Q 16 ns 7 ns
D
Clk
Q
ECE C03 Lecture 8 16
RS Latch Revisited
Truth Table:Next State = F(S, R, Current State)
S
R
Q
R-SLatch Q+
Derived K-Map:
Characteristic Equation:
Q+ = S + R Q t
R
SR 00 01 11 10
0 0 X 1
1 0 X 1
0
1
Q ( t )
S
S(t) R(t) Q(t) Q(t+d)
0 0 0 0 HOLD 0 0 1 1------------------------- 0 1 0 0 RESET 0 1 1 0------------------------- 1 0 0 1 SET 1 0 1 1------------------------- 1 1 0 X NOT ALLOWED 1 1 1 X
ECE C03 Lecture 8 17
JK Latch DesignHow to eliminate the forbidden state?
Idea: use output feedback to guarantee that R and S are never both one
J, K both one yields toggle
Characteristic Equation:
Q+ = Q K + Q J
R-S latch
K
J S
R
Q
\ Q \ Q
Q J(t) K(t) Q(t) Q(t+d)
0 0 0 0 HOLD 0 0 1 1------------------------- 0 1 0 0 RESET 0 1 1 0------------------------- 1 0 0 1 SET 1 0 1 1------------------------- 1 1 0 1 TOGGLE 1 1 1 0
ECE C03 Lecture 8 18
J
K
Q
\ Q
100
JK Latch Race Condition
Set Reset Toggle
Race Condition
Toggle Correctness: Single State change per clocking event
Solution: Master/Slave Flipflop
ECE C03 Lecture 8 19
Solution: Master Slave JK Flip FlopMaster Stage Slave Stage
Sample inputs while clock high Sample inputs while clock low
Uses time to break feedback path from outputs to inputs!Uses time to break feedback path from outputs to inputs!
Correct ToggleOperation
J
R-S Latch
R-S Latch
K R
S
Clk
\Q
Q
\P
P
R
S
\Q
Q
\Q
Q
Master outputs
Slave outputs
Set Reset T oggle 1's
Catch 100
J
K
Clk
P
\ P
Q
\ Q
by B. G. Kim 집적회로설계 (Digital Integrated Circuits) 20
Master-Slave-Based D Flip-Flop
• Master-Slave configuration
Master-Slave Edge-Triggered Flip-Flop
8 Transistors
36 Transistors
GND GND
QDCLK
CLK
VDD
CLK
CLK
VDD
Q
D
CLK
CLK
MASTER SLAVE
ECE C03 Lecture 8 22
Positive vs Negative Edge Triggered Devices
Positive Edge Triggered
Inputs sampled on rising edgeOutputs change after rising edge
Negative Edge Triggered
Inputs sampled on falling edgeOutputs change after falling edge
Toggle FlipflopFormed from J-K with both inputs wired together
Positive edge- t riggered FF
Negative edge- t riggered FF
D
Clk
Q pos
\ Q pos
Q neg
\ Q neg
100
ECE C03 Lecture 8 23
Realizing Circuits with Different Kinds of FFsR-S Clocked Latch:
used as storage element in narrow width clocked systems its use is not recommended! however, fundamental building block of other flipflop types
J-K Flipflop: versatile building block can be used to implement D and T FFs usually requires least amount of logic to implement ƒ(In,Q,Q+) but has two inputs with increased wiring complexity
because of 1's catching, never use master/slave J-K FFs edge-triggered varieties exist
D Flipflop: minimizes wires, much preferred in VLSI technologies simplest design technique best choice for storage registers
T Flipflops: don't really exist, constructed from J-K FFs usually best choice for implementing counters
Preset and Clear inputs highly desirable!!
ECE C03 Lecture 8 24
Timing Methodology• Set of rules for interconnecting components and clocks
• When followed, guarantee proper operation of system
• Approach depends on building blocks used for memory elements
For systems with latches:
Narrow Width Clocking
Multiphase Clocking (e.g., Two Phase Non-Overlapping)
For systems with edge-triggered flipflops:
Single Phase Clocking
• Correct Timing:
(1) correct inputs, with respect to time, are provided to the FFs
(2) no FF changes more than once per clocking event
ECE C03 Lecture 8 25
In
Q 0
Q 1
Clk
100
Cascaded Flipflops and Setup/Hold/Propagation Delays
Shift RegisterS,R are preset, preclear
New value to first stagewhile second stageobtains current valueof first stage
Correct Operation,assuming positiveedge triggered FF
IN
CLK
Q0 Q1D
C
Q
Q
D
C
Q
Q
ECE C03 Lecture 8 26
Why Cascaded Flip-Flops Work
• Propagation delays far exceed hold times; Clock width constraint exceeds setup time
• This guarantees following stage will latch current value before it is replaced by new value
• Assumes infinitely fast distribution of the clock
Timing constraintsguarantee proper
operation ofcascaded components
Timing constraintsguarantee proper
operation ofcascaded components
T su 20 ns
T plh 13 ns
T h 5 ns
T su 20 ns
T plh 13 ns
T h 5 ns
In
Clk
Q 0
Q 1
ECE C03 Lecture 8 27
Timing Methodologies
Design Strategies for Minimizing Clock Skew
Typical propagation delays for LS FFs: 13 ns
Need substantial clock delay (on the order of 13 ns) for skew to be a problem in this relatively slow technology
Nevertheless, the following are good design practices:
• distribute clock signals in general direction of data flows
• wire carrying the clock between two communicating components should be as short as possible
• for multiphase clocked systems, distribute all clocks in similar wire paths; this minimizes the possibility of overlap
• for the non-overlap clock generate, use the phase feedback signals from the furthest point in the circuit to which the clock is distributed; this guarantees that the phase is seen as low everywhere before it allows the next phase to go high
ECE C03 Lecture 8 28
Summary
• Sequential logic networks• Latches (RS Latch)• Flip-flops (D and JK)• Timing issues (setup and hold times)• NEXT LECTURE: Registers and Counters• READING: Katz 7.1, 7.2, 7.4, 7.5, Dewey 10.2,
10.3, 10.4