Post on 11-Feb-2022
Digital Circuit Design
Combinational Logic
Lan-Da Van (范倫達), Ph. D.
Department of Computer Science
National Chiao Tung University
Taiwan, R.O.C.
Fall, 2012
ldvan@cs.nctu.edu.tw
http://www.cs.nctu.edu.tw/~ldvan/
Lecture 4
Digital Circuit Design
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Outlines
Combinational Circuits
Analysis Procedure
Design Procedure
Binary Adder-Subtractor
Decimal Adder
Binary Multiplier
Decoders
Encoders
Multiplexers
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Introduction
Logic circuits for digital systems may be either
combinational or sequential.
A combinational circuit consists of logic gates whose
outputs at any time are determined from only the
present combination of inputs.
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Combinational Circuits
A combinational circuits
2n possible combinations of input values
Specific functions
Adders, subtractors, comparators, decoders, encoders, and
multiplexers
MSI circuits or standard cells
Combinational
Logic Circuit
n input
variables
m output
variables
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Step 1: Label all gate outputs that are a function of
input variables with arbitrary symbols – but with
meaningful names. Determine the Boolean functions
for each gate output.
Step 2: Label the gates that are a function of input
variables and previously labeled gates with other
arbitrary symbols. Find the Boolean functions for
these gates.
Step 3: Repeat the process outlined in step 2 until the
outputs of the circuit are obtained.
Step 4: By repeated substitution of previously defined
functions, obtain the output Boolean functions in
terms of input variables.
Analysis Procedure
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A straight-forward procedure
Analysis Procedure Example
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Step 1:
F2 = AB+AC+BC
T1 = A+B+C
T2 = ABC
Step 2:
T3 = F2'T1
Step 3:
F1 = T3+T2
Step 4:
F1 = T3+T2 = F2'T1+ABC
= (AB+AC+BC)'(A+B+C)+ABC
= (A'+B')(A'+C')(B'+C')(A+B+C)+ABC
= (A'+B'C')(AB'+AC'+BC'+B'C)+ABC
= A'BC'+A'B'C+AB'C'+ABC
Analysis Procedure Example
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Truth Table
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Design Procedure
The design procedure of combinational circuits
Step 1: State the problem (system spec.)
Step 2: From the specifications of the circuits,
determine the required number of inputs and outputs
and assign a symbol to each.
Step 3: Derive the truth table that defined the
required relationship between inputs and outputs
Step 4: Obtain the simplified Boolean functions for
each output as a function of the input variables.
Step 5: Draw the logic diagram and verify the
correctness of the design (manually or by simulation).
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Design Method and Constraint
Functional description Boolean function
HDL (Hardware description language)
Verilog HDL
VHDL
Schematic entry
Logic constraint number of gates
number of inputs to a gate
propagation delay
number of interconnections
limitations of the driving capabilities
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BCD to Excess-3 Code Conversion
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BCD to Excess-3 Code Conversion
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Simplified functions
z = D'
y = CD +C'D'
x = B'C + B'D+BC'D'
w = A+BC+BD
Efficient implementation
z = D'
y = CD +C'D'= CD + (C+D)‘
x = B'C + B'D+BC'D‘ = B'(C+D) +B(C+D)'
w = A+BC+BD= A+ B(C+D)
BCD to Excess-3 Code Conversion
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Logic Diagram for BCD to Excess-3 Code Converter
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1-Bit Half Adder
Half adder
0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 = (10)2
two input variables: x, y
two output variables: C (carry), S (sum)
truth table
S = x'y+xy'=xy= (x+y)(x'+y')
C = xy= (x'+y')'
S' = xy+x'y'
S = (C+x'y')'
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Logic Diagram of 1-Bit Half Adder
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Full-Adder
The arithmetic sum of three
input bits
three input bits
x, y: two significant bits
z: the carry bit from the
previous lower significant bit
Two output bits: C, S
1-Bit Full Adder
Sum Carry
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Logic Diagram of 1-Bit Full Adder
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S = x'y'z+x'yz'+ xy'z'+xyz
= x’(yz) +x(yz)’ = xyz
C = xy + xz + yz
= xy + xyz + xy’z + xyz + x’yz
= xy + z (xy + xy)
= xy + z (xy)
Logic Diagram of 1-Bit Full Adder
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Binary adder
4-Bit Full Adder
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Carry Lookahead Adder (1/7)
Given Stage i from a Full Adder, we know that there will be a carry generated when Ai = Bi = "1", whether or not there is a carry-in.
Alternately, there will be a carry propagated if the “half-sum” is "1" and a carry-in, Ci occurs.
These two signal conditions are called generate, denoted as Gi, and propagate, denoted as Pi respectively and are identified in the circuit.
Ai Bi
Ci
Ci+1
Gi
Pi
Si
Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals.
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Carry Lookahead Adder (2/7)
In the ripple carry adder:
Gi, Pi, and Si are local function to each cell of the
adder
Ci is also local function for each cell
In the carry lookahead adder, in order to reduce the
length of the carry chain, Ci is changed to a more
global function spanning multiple cells
Defining the equations for the Full Adder in term of
the Pi and Gi:
i i i i i i B A G B A P = =
i i i 1 i i i i C P G C C P S + = = +
Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals.
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Carry Lookahead Adder (3/7)
Ci+1 can be removed from the cells and used to
derive a set of carry equations spanning multiple cells.
Beginning at the cell 0 with carry in C0:
C1 = G0 + P0 C0
C4 = G3 + P3 C3 = G3 + P3G2 + P3P2G1+ P3P2P1G0
+ P3P2P1P0 C0
C2 = G1 + P1 C1 = G1 + P1(G0 + P0 C0)
= G1 + P1G0 + P1P0 C0
C3 = G2 + P2 C2 = G2 + P2(G1 + P1G0 + P1P0 C0)
= G2 + P2G1 + P2P1G0 + P2P1P0 C0
Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals.
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Carry Lookahead Adder (4/7)
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Carry Lookahead Adder (5/7)
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Carry Lookahead Adder (6/7)
CLA GEN
Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals.
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Carry Lookahead Adder (7/7)
This lookahead scheme could be extended to more than four bits; in practice, due to limited gate fan-in, such extension is not feasible.
Instead, the concept is extended another level by considering group generate (G0-3) and group propagate (P0-3) functions:
Using these two equations:
Thus, it is possible to have five 4-bit carry lookahead generator circuit to speed up 16-bit addition (see next slide).
0 1 2 3 3 0
0 1 2 3 1 2 3 2 3 3 3 0
P P P P P
G P P P G P P G P G G
=
+ + + =
-
-
0 3 0 3 0 4 C P G C - - + =
C4 = G3 + P3 C3 = G3 + P3G2 + P3P2G1+ P3P2P1G0
+ P3P2P1P0 C0
Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals.
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28
16-bit 2-level Carry Lookahead Adder
CLA GEN
c3
G0-3 P0-3
G0P0 G1P1
G2P2
G3P3
c0 CLA GEN
G4-7 P4-7
G4P4 G5P5
G6P6 G7P7
c4
CLA GEN
c9 c11
G8-11 P8-11
G8P8 G9P9
G10P10 G11P11
c8 CLA GEN
G12-15 P12-15
G12P12 G13P13
G14P14
G15P15
c12
CLA GEN
G0-15 P0-15
c8
c4
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4-Bit Adder/Subtractor
A-B = A+(2’s complement of B)
4-bit adder-subtractor M=0, A+B; M=1, A+B’+1
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Overflow
The storage is limited.
Add two positive numbers and obtain a negative number
Add two negative numbers and obtain a positive number
V = 0, no overflow; V = 1, overflow
Example:
Overflow Discussion
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BCD Adder
Add two decimal digits in BCD together with an input carry from
a previous stage
9 inputs: two BCD's and one carry-in
5 outputs: one BCD and one carry-out
Design approaches
Since each input digit does not exceed 9, the output sum cannot be
grater than 9+9+1 =19, where 1 denotes an input carry.
A truth table with 19 entries
Use two 4-bit binary full adders
Modifications are needed if the binary sum > 9
C = 1
K = 1
Z8Z4 = 1
Z8Z2 = 1
modification: +6
C = K +Z8Z4 + Z8Z2
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Truth Table of BCD Adder
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Logic Diagram of BCD Adder BCD
BCD Output
BCD
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Binary Multiplier
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4-Bit by 3-Bit Binary Multiplier
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Magnitude Comparator
The comparison of two numbers
outputs: A>B, A=B, A<B
Design Approaches
the truth table
22n
entries - too cumbersome for large n
use inherent regularity of the problem
reduce design efforts
reduce human errors
Algorithm -> logic
A = A3A2A1A0 ; B = B3B2B1B0
A=B if A3=B3, A2=B2, A1=B1and A0=B0
equality: xi= AiBi+Ai'Bi'
(A=B) = x3x2x1x0
(A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'
(A<B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0
Implementation
xi = (AiBi'+Ai'Bi)'
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Four-Bit Magnitude Comparator
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Decoder
An n-to-m decoder
a binary code of n bits = 2n
distinct information
n input variables; up to 2n
output lines
only one output can be active (high) at any time
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Three-to-Eight Line Decoder
x’y’z’
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Demultiplexers
a decoder with an enable input
receive information on a single line and transmits it on one of
2n
possible output lines
Two-to-four-line decoder with enable input
Decoder with Enable /Demultiplexer
0
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Decoder with Enable /Demultiplexer
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Expansion
two 3-to-8 decoder: a 4-to-16 decoder
4 16 decoder constructed with two 3 8 decoders
4x16 Decoder
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Combinational Logic Implementation
Each output = a minterm
Use a decoder and an external OR gate to implement any
Boolean function of n input variables
A full-adder
S(x,y,x)=S(1,2,4,7)
C(x,y,z)= S(3,5,6,7)
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Encoder
1 3 5 7
2 3 6 7
4 5 6 7
z D D D D
y D D D D
x D D D D
= + + +
= + + +
= + + +
The encoder can be implemented with three OR gates.
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An implementation
limitations
illegal input: e.g. D3=D6=1
the output = 111 (¹3 and ¹6)
Encoder
x=D4+D5+D6+D7
y=D2+D3+D6+D7
z=D1+D3+D5+D7
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Priority Encoder Resolve the ambiguity of illegal inputs Only one of the input is encoded
D3 has the highest priority D0 has the lowest priority X: don't-care conditions V: valid output indicator
LSB MSB
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Priority Encoder
1
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2 3
3 1 2
0 1 2 3
x D D
y D D D
V D D D D
= +
= +
= + + +
Priority Encoder
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Multiplexer
Select binary information from one of many input
lines and direct it to a single output line
2n
input lines, n selection lines and one output line
E.g.: 2-to-1-line multiplexer
Two-to-one-line multiplexer
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4-to-1-Line Multiplexer
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MUX: a decoder + an OR gate
2n
-to-1 MUX can implement any Boolean function of n
input variable.
Procedure:
assign an ordering sequence of the input variable
the rightmost variable (D) will be used for the input lines
assign the remaining n-1 variables to the selection lines w.r.t.
their corresponding sequence
construct the truth table
consider a pair of consecutive minterms starting from m0
determine the input lines
Boolean Function Implementation Using MUX
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Example: Given F(x,y,z) = S(1,2,6,7)
Boolean Function Implementation Using MUX
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Boolean Function Implementation Using MUX
Example: Given F(A, B, C, D) = S(1, 3, 4, 11, 12, 13, 14, 15)
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Three-State Gate
A multiplexer can be constructed with three-state
gates.
Output state: 0, 1, and high-impedance (open ckts)
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Four-to-One-Line Multiplexer
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Conclusion
From this lecture, you have learned the follows:
Adder/Subtractor
Multiplier
Decoder
Encoder
Multiplexer