Post on 28-Sep-2020
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Lecture 4: CMOS review & Dynamic Logic
Reading: ch5, ch6
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Overview
CMOS basics
Power and energy in CMOS
Dynamic logic
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CMOS Properties
Full rail-to-rail swing high noise margins
Logic levels not dependent upon the relative device sizes
ratioless
Always a path to VDD or GND in steady state low output
impedance ~ kΩ
Extremely high input resistance nearly zero steady-state
input current
No direct path steady state between power and ground no
static power dissipation (but leakage)
Propagation delay: function of load capacitance and resistance
of transistors D ~ f(C,R)
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CMOS
CMOS is the dominant circuit family due to:
No static power consumption
Ease of design
Robust to variations and noise
Etc…
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The CMOS Inverter: A First Glance
V in V out
C L
V DD
First DC analysis, then transient analysis
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CMOS Inverter
Polysilicon
In Out
V DD
GND
PMOS 2l
Metal 1
NMOS
OutIn
VDD
PMOS
NMOS
Contacts
N Well
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Two Inverters
Connect in Metal
Share power and ground
Abut cells
VDD
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CMOS Inverter First-Order DC Analysis
VOL = 0
VOH = VDD
VM = f(Rn, Rp)
V DD V DD
V in = V DD V in = 0
V out
V out
R n
R p
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CMOS Inverter VTC
Vout
Vin0.5 1 1.5 2 2.5
0.5
11.5
22
.5
NMOS resPMOS off
NMOS satPMOS sat
NMOS offPMOS res
NMOS satPMOS res
NMOS resPMOS sat
Noise Margins?
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CMOS Inverter: Transient Response
t pHL = f(R on .C L )
= 0.69 R on C L
V out V out
R n
R p
V DD V DD
V in = V DD V in = 0
(a) Low-to-high (b) High-to-low
C L C L
-ln(0.5)
How do is Ron calculated?
CL: Cdiff, Cwire, Cg
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Fast gate
Transient response
tp= f(Ron, CL)
CL: : Cdiff, Cwire, Cg
Fast gate
Lower CL: small size, short wire, smaller gate input cap (area)
Smaller Ron (bigger size or width): increase W/L ratio
It is nonlinear depend on gate operation (lin, sat, etc…)
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CMOS Performance Analysis
Propagation delay: 0.69 0.69pHL eqn L pLH eqp Lt R C t R C
Average the large signal resistance at endpoints of
voltage transition of concern (0-50%)
At 0% V/I is Vdd/Idsat
At 50% V/I is (Vdd/2)/(a*Idsat) where a<1
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Switching Threshold as a function of Transistor Ratio
10 0
10 1
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
M
V
(V
)
W p
/W n
1
DDM
rVV
r
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Determining VIH and VIL
V OH
V OL
V in
V out
V M
V IL V IH
A simplified approach
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Impact of Process Variations
0 0.5 1 1.5 2 2.5 0
0.5
1
1.5
2
2.5
V in (V)
V ou
t (V)
Good PMOS Bad NMOS
Good NMOS Bad PMOS
Nominal
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5
Vin
(V)
Vout(V
)
What is “good” device
- Smaller oxide thickness, smaller length
- Higher width, smaller threshold, etc…
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Gain as a function of VDD (Vdd scaling)
0 0.05 0.1 0.15 0.20
0.05
0.1
0.15
0.2
Vin
(V)
Vout (V
)
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5
Vin
(V)
Vout(V
)
Gain=-1
Lowering VDD
- Slower
- Sensitive to variations
- Sensitive to external noise
Subthreshold
( 25 )T
kTmV
q
Thermal noise
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CMOS Inverter Propagation Delay Approach 1
VDD
Vout
Vin = VDD
CLIav
tpHL = CL Vswing/2
Iav
CL
kn VDD
~
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CMOS Inverter Propagation Delay Approach 2
VDD
Vout
Vin = VDD
Ron
CL
tpHL = f(Ron.CL)
= 0.69 RonCL
t
Vout
VDD
RonCL
1
0.5
ln(0.5)
0.36
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CMOS Inverters
Polysilicon
In Out
Metal1
V DD
GND
PMOS
NMOS
1.2 m m =2l
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Capacitance (CL)
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Miller Effect
“A capacitor experiencing identical but opposite
voltage swings at both its terminals can be
replaced by a capacitor to ground, whose value
is two times the original value.”
02gd GDC C W
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MOS Capacitances
Gate to channel cap
Drain to bulk and source to bulk
(junction) cap
Overlap cap, Cgd0 and Cgs0
Capacitance parameters for book’s 0.25μm process
W, L, AD, PD, AS, PS
Bottom
Side wall
Side wall Channel
Source N D
Channel-stop implant N A 1
Substrate N A
W
x j
L S
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A first-order RC network
v out
v in C
R
tp = ln (2) t = 0.69 RC = 0.69 ReqCL
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0 0.5 1 1.5 2 2.5
x 10-10
-0.5
0
0.5
1
1.5
2
2.5
3
t (sec)
Vout(V
)
Transient Response
tp = 0.69 CL (Reqn+Reqp)/2
?
tpLH tpHL
If a≈0.9, then Req=0.8*Vdd/Idsat
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Delay as a function of VDD
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VDD
(V)
t p(n
orm
aliz
ed)
0.69* *
0.69*(0.8* / )*
pHL eq L
dd dsat L
t R C
V I C
'0.52
( / )
LpHL
n n DSATn
Ct
W L k V
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Design for Performance (Speed)
Keep capacitances small (reduce CL)
Compact layout, good placement (short wires)
Keep drain diffusion areas as small as possible
Increase transistor sizes to match load
Increase W/L ratio Watch out for self-loading!
Increase CL and Cgate
Increase VDD (????)
Not usually possible due to reliability and power penalties
~ L
P
n DD
Ct
k V
~ L DDP
C Vt
I
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1 1.5 2 2.5 3 3.5 4 4.5 53
3.5
4
4.5
5x 10
-11
b
t p(s
ec)
NMOS/PMOS ratio
tpLH tpHL
tp
b = Wp/Wn
PMOS size up
Improve tpLH
Larger cap
Degrade tpHL
( )
2
pLH pHL
P
t tt
1 2
(1 ) 1.9wopt
dn gn
Cr
C Cb
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2 4 6 8 10 12 142
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8x 10
-11
S
t p(s
ec)
Device Sizing
(for fixed load)
Self-loading effect: Intrinsic capacitances dominate
intL extC C C
Cint: self-loading
Cdiff, Cgd
Cext: fanout + Cw
int
int 0
int int
0.69 ( )
0.69 (1 ) (1 )
p eq ext
ext exteq p
t R C C
C CR C t
C C
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Inverter Chain
CL
If CL is given:
- How many stages (N) are needed to minimize the delay?
- How to size (f) the inverters?
May need some additional constraints.
In Out
One INV Sizing ↑ delay ↓ but, input cap. ↑
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Inverter Delay
• Minimum length devices, L=0.25mm
• Assume that for WP = 2WN =2W • same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
• Analyze as an RC network
WNunit
Nunit
unit
PunitP RR
W
WR
W
WRR
11
tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL Delay (D):
2W
W
unit
unit
gin CW
WC 3Load for the next stage:
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Inverter with Load
Load (CL)
Delay
Assumptions: no load zero delay
CL
tp = k RWCL
RW
RW
Wunit = 1
k is a constant, equal to 0.69
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Inverter with Load
Load
Delay
Cint CL
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)
= Delay (Internal) + Delay (Load)
CN = Cunit
CP = 2Cunit
2W
W
Dint
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Delay Formula
/1/1
~
0int ftCCCkRt
CCRDelay
pintLWp
LintW
Cint = Cgin with 1 ; intrinsic output capacitance
CL=Cext (=fanout + CW)
f = CL/Cgin : effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit intrinsic or unloaded delay
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Apply to Inverter Chain
CL
In Out
1 2 N
tp = tp1 + tp2 + …+ tpN
jgin
jgin
unitunitpjC
CCRt
,
1,1~
LNgin
N
i jgin
jgin
p
N
j
jpp CC C
Cttt
1,
1 ,
1,
0
1
, ,1
tP
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Optimal Tapering for Given N
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N
Minimize the delay, find N - 1 partial derivatives
Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1 fj=fj+1
Size of each stage is the geometric mean of two neighbors
- each stage has the same effective fanout (f=Cout/Cin)
- each stage has the same delay (tpi = tpi+1)
1,1,, jginjginjgin CCC
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Optimum Delay and Number of Stages
,1
N L
gin
Cf F
C
When each stage is sized by f and has same eff. fanout f:
N Ff
/10N
pp FNtt
Minimum path delay, where N is # of stages
Effective fanout of each stage:
F is the overall eff. fanout
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Example
CL= 8 C1
In Out
C1 1 f f2
283 f
CL/C1 has to be evenly distributed across N = 3 stages:
1
8LCF
C
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Optimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ff
fFtFNtt
pN
pplnln
ln1/
0/1
0
0ln
1lnln2
0
f
ffFt
f
t pp
For = 0, f = e, N = lnF
f
FNCfCFC in
N
inLln
ln with
ff 1exp
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Optimum Effective Fanout ( f )
Optimum f for given process defined by
ff 1exp
fopt = 3.6 for =1
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Impact of Self-Loading on tp
1.0 3.0 5.0 7.0u
0.0
20.0
40.0
60.0
u/l
n(u
)
x=10
x=100
x=1000
x=10,000
No Self-Loading, =0
CL=fan-out
With Self-Loading =1
f
Norm
aliz
ed d
ela
y
fopt=4
N=ln(F)
f=e=2.71828
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Normalized delay: function of F
/10N
pp FNtt
fopt
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Buffer Design (γ = 1)
1
1
1
1
8
64
64
64
64
4
2.8 8
16
22.6
N f tp
1 64 65
2 8 18
3 4 15
4 2.8 15.3
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Fast Complex Gates: Design Techniques
Isolating fan-in from fan-out using buffer insertion
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Logic Effort – more detail in later time
Straightforward (back of envelope) technique to
estimate delay of CMOS circuit
Ivan E. Sutherland, Robert F. Sproull, and David F.
Harris (1999). Logical Effort: Designing Fast CMOS
Circuits. Morgan Kaufmann. ISBN 1558605576.
http://books.google.com/books?id=hGVWzQmQYP0C&pg=P
P1&ots=OA5TMYJeFS&dq=logical+effort+cmos&sig=rxgvRW
0PaIe8oMLSGr5gQ8B0des#v=onepage&q=&
http://en.wikipedia.org/wiki/Logical_effort
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Input Pattern Effects on Delay
Delay is dependent on the
pattern of inputs
Low to high transition
Both inputs go low
Delay is 0.69*Rp/2CL
One input goes low
Delya is 0.69*RpCL
High to low transition
Both inputs go high
Delay is 0.69*2RnCL
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Transistor Sizing
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Sizing a Complex CMOS gate
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Fast Complex Gates: Design Techniques
Transistor ordering
Delay determined by time
to discharge CL, C1, and
C2
Delay determined by time
to discharge CL,
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Power and Energy in CMOS
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Power and Energy Figures of Merit (FOM)
Power consumption in Watts
Determines battery life in hours
Ex) Laptop battery rated at 65W-hr
Peak power
Determines power and ground wiring requirements
Sets packaging limits (plastic vs. ceramic)
Energy in units of Joules
Energy = power * time (E=Pt)
Joules = Watts * seconds
Lower energy means less power to perform a computation at the same
frequency
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Dynamic power consumption
Charging and discharging of capacitors
Short-circuit currents
During switching transients, currents flows between Vdd and GND
Not dominants (@low Vdd)– typically assumed to be ~10% of dynamic power
Static power consumption (leakage)
Due to non-ideal switches
Leaking diodes and transistors
Becoming important @ short L and lower Vt
Where Does Power Go in CMOS?
Almost zero static power consumption !!!
(except leakage)
Dynamic
Static
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Dynamic Power Dissipation
Energy/transition = EN + EP= C L * V dd 2
Power = E/t = Energy/transition * f = C L * V dd 2 * f
Vin Vout
C L
Vdd
Need to reduce C L , V dd , and f to reduce power.
Not a function of transistor sizes! NO! CL is function of device size
L H
H L
L H
2
2
L DDC V
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Switching Activity, αsw
Let fsw = αsw*fclock, since we usually know clock frequency
of a design (e.g., 3 GHz core 2 Duo)
0 < αsw <1
For αsw = 0, the circuit never switches so no dynamic power is
consumed
For αsw = 1, the node switches as often as the clock (the circuit
cannot switch more often than this) so fsw = fclock
More cases somewhere in between
Lower αsw lower power
αsw = 0.25 (25%)
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Low Energy-Power Design Techniques
2
dyn DDP CV f
Switching activity:
Design, architecture
Capacitance:
Wire, gate size, Fan-out
Supply Voltage:
Voltage scaling
Frequency
Clock speed
• Does not dependent(directly) on size
• Does not dependent on switching delay
• No switching no Pdyn consumption
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Fundamental Tradeoff: Power vs. Delay
~ LP
n DD
Ct
k V
2
dyn DDP CV f
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Short Circuit Currents
Vin Vout
CL
Vdd
I VD
D (m
A)
0.15
0.10
0.05
Vin (V)5.04.03.02.01.00.0
• Non-ideal Trise, Tfall
• When both tr. on
• Imax depends on
saturation current
ISC
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Dynamic Short Circuit Power
During input switching, both NMOS and PMOS are ON for a small amount of a time
Some current is “lost” meaning it’s not use to charge/discharge the capacitor, but flows to the other
supply rail
tsc : Duration of input signal
Ipeak : size, ratio between input and output slopes (CL)
2
2 2
peak sc peak sc
dp DD DD sc DD peak
dp sc DD peak sc DD
I t I tE V V t V I
P t V I f C V f
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Impact of CL on short-circuit current
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How to keep Short-Circuit Currents Low?
Short circuit current goes to zero if tfall >> trise,
but can’t do this for cascade logic, so ...
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Minimizing Short-Circuit Power
0 1 2 3 4 50
1
2
3
4
5
6
7
8
tsin
/tsout
Pnorm
Vdd =1.5
Vdd =2.5
Vdd =3.3
Less important in deep submicron tech. VDD≤1
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Leakage (Static Power Consumption)
Vout
Vdd
Sub-ThresholdCurrent
Drain JunctionLeakage
Sub-Threshold Current Dominant Factor
• Leakage becomes important in modern CMOS • Wasted energy should be avoided as much as possible • More complicated • Sub-threshold current one of most compelling issues in
low-energy circuit design!
0
No switching
= Vdd
Ideally, no static current
But, not completely OFF
static DD offP V I
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Reverse-Biased Diode (Junction)Leakage
Np+ p+
Reverse Leakage Current
+
-Vdd
GATE
IDL = JS A
JS = 1-5pA/mm2 for a 1.2mm CMOS technology
Js double with every 9oC increase in temperature
JS = 10-100 pA/mm2 at 25 ℃ for 0.25mm CMOS
JS doubles for every 9 ℃!
60x at 85℃ 0.6-6nA/um2 ~6mW (1mil.
Gates)
Temperature !!!
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Subthreshold Leakage Component
Isub
=Ioff
• Note log scale on y-axis • Off-current (Ioff) defined as how much current a device conducts
when Vgs = 0V [and Vds=Vdd] • Leakage control is critical for low-voltage operation (low VDD low
Vt)
Subthreshold Swing
(Ss): mV/decade
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Example Calculation
Subthreshold swing (Ss) is around 80-100mV/decade
Let Vth be 0.3V and Ss = 100mV/decade
Ioff = 10nA/um
Assume 107 inverters in a design (not a good design…)
with Wn = 1um
Total Ioff= 107*10nA = 100mA = 0.1A
Pstatic = 2V*100mA = 0.2W
/10 / *10 th sV S
offI A mm m
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Power in CMOS
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Principles for Power Reduction
Prime choice: Reduce voltage! (V)
Recent years have seen an acceleration in supply voltage reduction
Design at very low voltages still open question (0.6 … 0.9 V by 2010!) 45nm tech. still use 1.0V or 1.2V
Reduce switching activity (α)
Reduce physical capacitance (CL)
Device Sizing: for F=20 fopt(energy)=3.53, fopt(performance)=4.47
Reduce leakage current (Ileak)
2
tot dyn dp stat L DD DD leakP P P P C V f V I
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Delay, Energy, and Power Metrics
Power-Delay Product (PDP)
Average energy consumed per power switching event
Energy-Delay Product (EDP)
22
max2
L DDav p L DD p
C VPDP P t C V f t
22
2
L DDp av p p
C VEDP PDP t P t t
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Summary of Power in CMOS
Power reduction is as important as increasing speed in IC
design today
Three major components of power in CMOS
Dynamic: charging capacitors dominant
Short-circuit: small, typically ignore
Static: subthreshold leakage, growing fast
2
tot dyn dp stat L DD DD leakP P P P C V f V I
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Summary and Next time
CMOS is the dominant circuit family due to:
No static power consumption
Ease of design
Robust to variations and noise
Inverter propagation delay
Dynamic power consumption
Leakage is becoming important
Short channel length (L=45nm, 32nm, 22nm …)
Low Vt
Next time: Combinational Logic design in CMOS
Static vs. Dynamic
Logical effort
~ LP
n DD
Ct
k V
2
dyn DDP CV f