Lecture 20

OUTLINE

The MOSFET (cont’d) • Qualitative theory• Field-effect mobility• Long-channel I-V characteristics

Reading: Pierret 17.2, 18.3.4; Hu 6.3-6.6

Qualitative Theory of the NMOSFETdepletion layer

The potential barrier to electron flow from the source into the channel region is lowered by applying VGS> VT

Electrons flow from the source to the drain by drift, when VDS>0. (IDS > 0)

The channel potential varies from VS at the source end to VD at the drain end.

VGS < VT :

VGS > VT :

VDS 0

VDS > 0

EE130/230M Spring 2013 Lecture 20, Slide 2

Inversion-layer “channel” is formed

MOSFET Linear Region of OperationFor small values of VDS (i.e. for VDS << VGVT),

where eff is the effective carrier mobility

Hence the NMOSFET can be modeled as a resistor:

L

VWQWQvWQI DS

effinveffinvinvDS

)( TGoxeeffDS

DSDS VVCW

L

I

VR

EE130/230M Spring 2013 Lecture 20, Slide 3

Field-Effect Mobility, eff

Scattering mechanisms:

• Coulombic scattering

• phonon scattering

• surface roughness scattering

EE130/230M Spring 2013 Lecture 20, Slide 4

• When VD is increased to be equal to VG-VT, the inversion-layer charge density at the drain end of the channel equals 0, i.e. the channel becomes “pinched off”

• As VD is increased above VG-VT, the length L of the “pinch-off” region increases. The voltage applied across the inversion layer is always VDsat=VGS-VT, and so the current saturates.

• If L is significant compared to L, then IDS will increase slightly with increasing VDS>VDsat, due to “channel-length modulation”

DsatDS VVDSDsat II

VDS = VGS-VT

VDS > VGS-VT

EE130/230M Spring 2013 Lecture 20, Slide 5

ID

VDS

MOSFET Saturation Region of Operation

Ideal MOSFET I-V Characteristics

Linearregion

Enhancement-Mode N-channel MOSFET

EE130/230M Spring 2013 Lecture 20, Slide 6

Impact of Inversion-Layer Bias• When a MOS device is biased into inversion, a pn junction

exists between the surface and the bulk.• If the inversion layer contacts a heavily doped region of the

same type, it is possible to apply a bias to this pn junction.

N+ poly-Si

p-type Si

-- - - --

+ + + + + +

N+

+ +

-- -SiO2

• VG is biased so that surface is inverted• n-type inversion layer is contacted by N+

region• If a bias VC is applied to the channel, a

reverse bias (VB-VC) is applied between the channel and body

EE130/230M Spring 2013 Lecture 20, Slide 7

Effect of VCB on S, W and VT

• Application of a reverse body bias non-equilibrium 2 Fermi levels (one in n-type region, one in p-type region)

are separated by qVBC S is increased by VCB

• Reverse body bias widens W, increases Qdep and hence VT

ox

CBFSiAFCBFBT C

yVqNyVVyV

))(2(22)()(

EE130/230M Spring 2013 Lecture 20, Slide 8

Derivation of NMOSFET I-V• VD > VS

• Current in the channel flows by drift• Channel voltage VC(y) varies continuously between the source

and the drain

• Channel inversion charge density

oxe

depSCBFBGoxeinv C

yQyVVVCyQ

)(2)()(

ox

CBFSiAFCBFBT C

yVqNyVVyV

))(2(22)()(

W

EE130/230M Spring 2013 Lecture 20, Slide 9

1st-Order Approximation• If we neglect the variation of Qdep with y, then

where VT is defined to be the threshold voltage at the source end:

The inversion charge density is then

)2(2 SBFSiAdep VqNQ

)()(

)2(22)()(

yVVVyV

VVC

VqNyVVyV

CBSBTT

SBSBox

SBFSiAFCBFBT

EE130/230M Spring 2013 Lecture 20, Slide 10

)()( yVVVVCyVVVVCQ CSTGoxeCBSBTGoxeinv

ox

SBFSiAFSBFBT C

VqNVVV

)2(22

NMOSFET Current (1st-order approx.)• Consider an incremental length dy of the channel. The voltage

drop across this region is

DSDS

TGoxeeffDS

V

V CCSTGoxeeff

V

V CCinveffDS

V

V CCinveff

L

DS

effinv

DS

inveffDS

invDSDSC

VV

VVCL

WI

dVVVVVCL

W

dVVQL

WI

dVVWQdyI

WQ

dyI

nWTq

dyI

WT

dyIdRIdV

D

S

D

S

D

S

2

)(

)(0

in the linear region

EE130/230M Spring 2013 Lecture 20, Slide 11

2)(2 TGeffoxeDsat VVCL

WI

IDS saturates when VD reaches VG-VT

Saturation Current, IDsat (1st-order approximation)

TGDsatD VVVV for

ox

SBFSiAFSBFBT C

VqNVVV

)2(22

EE130/230M Spring 2013 Lecture 20, Slide 12

Set VD = VG-VT in the equation for ID

Problem with “Square Law Theory”• Ignores variation in depletion width with distance y:

where

CSTGoxeinv VVVVCQ

EE130/230M Spring 2013 Lecture 20, Slide 13

ox

SBFSiAFSBFBT C

VqNVVV

)2(22

Modified (Bulk-Charge) I-V Model

T

oxe

oxe

dep

W

T

C

Cm

311 min, where

23 since OSiSi

DSDSTGeffoxeDlin VVm

VVCL

WI )

2(

2)(2 TGeffoxeDsat VVCmL

WI

In saturation region:m

VVVV TG

DsatD

In linear region:m

VVVV TG

DsatD

EE130/230M Spring 2013 Lecture 20, Slide 14

MOSFET Threshold Voltage, VT

The expression that was previously derived for VT is the gate voltage referenced to the body voltage that is required reach the threshold condition:

ox

SBFSiAFSBFBT C

VqNVVV

)2(22

Usually, the terminal voltages for a MOSFET are all referenced to the source voltage. In this case,

and the equations for IDS areox

SBFSiAFFBT C

VqNVV

)2(22

DSDSTGSeffoxeDlin VVm

VVCL

WI )

2( 2)(

2 TGSeffoxeDsat VVCmL

WI

mVVVV TGSDsatDS / mVVVV TGSDsatDS /EE130/230M Spring 2013 Lecture 20, Slide 15

The Body EffectNote that VT is a function of VSB:

where is the body effect parameter

When the source-body pn junction is reverse-biased, |VT| is increased. Usually, we want to minimize so that IDsat will be the same for all transistors in a circuit.

FSBFTFSBFox

SiAT

ox

SBFSiA

ox

FSiA

ox

FSiAFFB

ox

SBFSiAFFBT

VVVC

qNV

C

VqN

C

qN

C

qNV

C

VqNVV

22222

)2(2)2(2)2(22

)2(22

00

EE130/230M Spring 2013 Lecture 20, Slide 16

MOSFET VT Measurement

• VT can be determined by plotting IDS vs. VGS, using a low value of VDS

IDS

VGS

EE130/230M Spring 2013 Lecture 20, Slide 17

Channel Length Modulation• Recall that as VDS is increased above VDsat, the width L of the

depletion region between the pinch-off point and the drain increases, i.e. the inversion layer length decreases.

L

L

LLLIDsat 1

11

DsatDS VVL

DsatDS VVL

L

DsatDSTGSeffoxeDsat VVVVCmL

WI 1)(

22

EE130/230M Spring 2013 Lecture 20, Slide 18

IDS

VDS

Long-Channel MOSFET I-V Summary• In the ON state (VGS>VT for NMOS; VGS<VT for PMOS), the

inversion layer at the semiconductor surface forms a “channel” for current to flow by carrier drift from source to drain

In the linear region of operation (VDS < (VGSVT)/m):

In the saturation region of operation (VDS > (VGSVT)/m):

L

VWQWQvWQII DS

effinveffinvinvDlinDS

DSsatDSTGSeffoxeDsatDS VVVVCmL

WII 1)(

22

2DS

TGSoxeinv

mVVVCQ

oxe

dep

C

Cm min,1 GSeff Vf

EE130/230M Spring 2013 Lecture 20, Slide 19