Post on 15-Sep-2020
Lect 15Lect 15
Programmable Logic
CS221: Digital Design
Dr. A. SahuDept of Comp. Sc. & Engg.
Indian Institute of Technology GuwahatiIndian Institute of Technology Guwahati1
Outline• Programmable Logic• PAL PLA• PAL, PLA, • Memory
–ROM, PROM, EPROM, EEPROM–SRAM : Memory CellSRAM : Memory Cell
• CPLD, CLB, FPGA• FPGA/ASIC Design Flow • HDL Programming : Verilog HDL• HDL Programming : Verilog HDL
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ProgrammableProgrammable Logic DevicesLogic Devices
Programmable Via Control : /Adder/Substractor
• C= B‐A=B+(‐A)=B+ (Ab+1), Ab is complement of A• D is control bit: D=0/1 operation is add/sub
A
Result
ALUB
Operation
4
Operation
Programmable Via Select: ALUProgrammable Via Select: ALU• Arithmetic and Logic Unit • Add/Sub/OR/AND/Shift…
if Control=0 R =A +BR=0
AR
if Control=0 R =A +B if Control=1 R =A ‐ B if Control=2 R =NOT A
R>0Co
R if Control=3 R =A AND B if Control=4 R =A OR B
B if Control=5 R =A XOR Bif Control=6 R = (A<B)?0:A if Control=7 R =A SHFT B
5Control: What to do ?
if Control=7 R =A SHFT B
ProgrammableProgrammable Logic DevicesLogic Devices
Programmable Logic Organization• Pre‐fabricated building block of many AND/OR gates (or NOR, NAND)
• "Personalized" by making or breaking connections among the gates
Inputs
Dense Array of AND gates
Dense Array of OR GatesProduct termsterms
Outputs
Programmable Array Block Diagram for Sum of Products Form
Basic Programmable Logic Organizations
• Depending on which of the AND/OR logicDepending on which of the AND/OR logic arrays is programmable, we have three basic organizations
AND ARRAY OR ARRAYORGANIZATION
PROG. FIXEDPAL
FIXED
PROG.
PROG.
PROG.
PROM
PLA PROG. PROG.PLA
PLA Logic ImplementationKey to Success: Shared Product TermsExample: Equations
Key to Success: Shared Product Terms
F0 A + B’ C’
Personality MatrixOutputsInputsProductF0 = A + B’ C’
F1 = A C ‘ + A BF2 = B ‘C’ + A B Reuse
F 1 1 0
Outputs Inputs Product t erm A
1 B 1 0
C ‐1
F 0 0 0
F 2 1 0
F 3 0 1
A B B’ CF3 = B ‘C + A Reuse
of t erms
0 1 0
‐1 ‐
0 ‐0
1 0 0
0 0 1
0 0 1
1 0 0
B’ C A C’ B’ C’
1 = asserted in termInput Side:
0 1 ‐ ‐ 1 0 1 A
1 asserted in term0 = negated in term‐ = does not participate
Output Side:1 = term connected to output0 = no connection to output
Output Side:
PLA Logic Implementationl i d d d iExample Continued ‐ Unprogrammed device
All possible connections are availableb f i
A B Cbefore programming
F0 F1 F2 F3
PLA Logic ImplementationExample Continued ‐ Programmed part
A B C
Unwanted connections are "blown"ABAB
B’C
’AC’
B’C’
A
Note: some array structureswork by making connectionsrather than breaking them F0 F1 F2 F3
PLA Logic ImplementationAlternative representation
Un‐programmed device
Sh t h d t ti d 't h tShort‐hand notation so we don't have todraw all the wires!
X at junction indicates a connection
PLA Logic ImplementationNotation for implementing
F0 = A B + A’ B’F1 = CD’ + C’D Programmed deviceF1 = CD + C D
A B C D
AB
Programmed device
AB
CD’
A’B’
CD’
C’D
AB+A’B’ CD’+C’D
PLA Logic ImplementationMultiple functions of A, B, C : List of all product terms
Design Example
Multiple functions of A, B, C : List of all product terms
ABC
A B C Programmed device
F1 = A B CF2 = A + B + CF3 = (A B C)’
ABCABCF3 = (A B C)
F4 = (A + B + C)’F5 = A ⊕ B ⊕ C
CA’B’C’
F6 = (A ⊕ B ⊕ C)’ A’B’C’A’B’CA’BC’AB’C’ABC’A’BCAB’CAB’C
F1 F2 F3 F4 F5 F6
PLA Logic ImplementationAnother Example: Magnitude Comparator
A AB CD 00 01 11 10
AB CD 00 01 11 10
A
1 0 0 0
0 1 0 0
CD 00 01 11 10 00
01 D
0 1 1 1
1 0 1 1
CD 00 01 11 10 00
01 D
0 0 1 0
0 0 0 1
11
10
B
C 1 1 0 1
1 1 1 0
11
10
B
C
K‐map for EQ
AB CD 00 01 11 10
A AB CD 00 01 11 10
A
K‐map for NE
00
01
11 D
0 1 1 1
0 0 1 1
0 0 0 0
00
01
11 D
0 0 0 0
1 0 0 0
1 1 0 1
10
B
C 0 0 1 0
K‐map for GT
10
B
C 1 1 0 0
K‐map for L T
A B C D
PLA Logic Imp: Magnitude Comparator
A’B’C’D’A’BC’D
A B C D
A BC DABCDAB’CD’AC’AC’A’CB’DBDBDA’B’DB’CDABCABCB’C’D’
EQ NE LT GT
PALs and PLAsWhat is difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA)?PAL concept — implemented by Monolithic MemoriesPAL concept implemented by Monolithic MemoriesAND array is programmable, OR array is fixed at fabrication
A given column of the OR array has access to only a subset of the
possible product terms
PLA concept — Both AND and OR arrays are programmable
PALs and PLAs• Of the two organizations the PLA is the most flexibleflexible– One PLA can implement a huge range of logic functions
– BUT many pins; large package, higher cost
• PALs are more restricted / you trade number• PALs are more restricted / you trade number of OR terms vs number of outputs
Many device variations needed– Many device variations needed– Each device is cheaper than a PLA
Read‐Only MemoryRead‐Only Memory
ROM
ROM• Decoder : Produces minterms
• Ors : Produce SOP’s
A ‘B’C’D’ A ‘B’C’D A‘B’CD’ F1
0 1 2 A B CD
A ‘B’CD A ‘BC’D’ A ‘BC’D A‘BCD’
A B S2
S3
2 3 4 5 64 16 A BCD
A ‘ BCD A B’C’D’ A B’C’D AB’CD’
F2C D
2
S1
S0
6 7 8 9
10
4:16 dec
A B CD A B’CD A B C’D’A B C’D AB C D’ F3
D S0 10 1 1 12 13 14 A B C D’
A B C D F314
15 Enb
ROM• A decoder• A decoder• A set of programmable OR’s
D7D6D5
X XX
X XD5D4D3D2D1
A2A1
AB
XX
X XD1D0
A1A0
BC
XX
X
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F0F1F2F3
ROM vs. PLA/PAL
InputsFixed
AND array(d d )
ProgrammableOR array
OutputsProgrammableConnections
(a) Programmable read-only memory (PROM)
(decoder) OR arrayConnections
Inputs ProgrammableAND array
FixedOR array
OutputsProgrammableConnections
(b) Programmable array logic (PAL) device
Inputs ProgrammableOR array
OutputsProgrammableConnections
ProgrammableConnections
ProgrammableAND array
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(c) Programmable logic array (PLA) device
General Logic Implementation
• Given a 2kxn ROM, we can implement ANY bi ti l i it ith t t kANY combinational circuit with at most k inputs and at most n outputs.
• Why?k to 2k decoder will generate all 2k possible– k‐to‐2 decoder will generate all 2 possible minterms
h f h l– Each of the OR gates must implement a ∑m()
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– Each ∑m() can be programmed
Example• Find a ROM‐based circuit implementation for:implementation for:– f(a,b,c) = a’b’ + abc
( b ) ’b’ ’ b b– g(a,b,c) = a’b’c’ + ab + bc–h(a,b,c) = a’b’ + c
• Solution:– Express f(), g(), and h() in ∑m() format (useExpress f(), g(), and h() in ∑m() format (use truth tables)
–Program the ROM based on the 3 ∑m()’s
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Program the ROM based on the 3 ∑m() s
Example• There are 3 inputs and 3 outputs, thus we need a 8x3 ROM block.8x3 ROM block.f = ∑m(0, 1, 7), g = ∑m(0, 3, 6, 7), h = ∑m(0, 1, 3, 5, 7)
3-to-8
0123
a
b decoder 4567
b
c
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f g h
ROM as a Memory• Read Only Memories (ROM) or Programmable Read Only Memories (PROM) have:Read Only Memories (PROM) have:– N input lines, – M output lines and– M output lines, and
– 2N decoded minterms.
• Can be viewed as a memory with the inputs as addresses of data (output values), – hence ROM or PROM names!
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Memories• Volatile: Random Access Memory (RAM)
– SRAM "static" –DRAM "dynamic"
• Non‐Volatile: Read Only Memory (ROM):Non Volatile: Read Only Memory (ROM): –Mask ROM "mask programmable" – EPROM "electrically programmable"EPROM electrically programmable – EEPROM “electrically erasable electrically programmable" p g
– FLASH memory ‐ similar to EEPROM with programmer integrated on chip
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ROM as Memory•Read Example: For input (A2,A1,A0) = 011, output is (F0,F1,F2,F3 ) = 0010.What are functions F F F and F in terms of (A A A )?
0 1 1 0 1Address 8x4 ROM
•What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)?
0 1 1 0 1
1 0 0 0 0
2 1 0 0 1
D0D1D2D3
X XX
XX
X
3 0 0 1 0
4 0 0 0 03 4
D4D5D6D7
A2A1A0
AB
C
XX
XX
A[2:0] F[3:0]
5 1 0 0 0
6 0 0 1 1
7 0 1 0 0
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7 0 1 0 0F3F2F1F0
A[2:0] =A2A1A0 F[3:0]=F3F2F1F0
Design by ROM: Examplel ll• BCD to 7 Segment Display Controller
A B C D a b c d e f g
0 0 0 00 0 0 10 0 1 0
1 1 1 1 1 1 00 1 1 0 0 0 01 1 0 1 1 0 1 a0 0 1 1
0 1 0 00 1 0 10 1 1 0
1 1 1 1 0 0 10 1 1 0 0 1 11 0 1 1 0 1 11 0 1 1 1 1 1
a
f b0 1 1 00 1 1 11 0 0 01 0 0 1
1 0 1 1 1 1 11 1 1 0 0 0 01 1 1 1 1 1 11 1 1 0 0 1 1 e c
b
1 0 1 01 0 1 11 1 0 01 1 0 1
X X X X X X XX X X X X X XX X X X X X XX X X X X X X
d
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1 1 0 11 1 1 00 1 1 1
X X X X X X XX X X X X X XX X X X X X X
g
Memory UnitMemory UnitRead/Write
D
Address MA
eco
Data
Data to
AR
odeData to
Read/Writeer
Memory UnitMemory UnitMemory celln bits
ster
bit 0
bit 1012
dress regis
decod
er234
emory ad
d
Address
Me
bit n ‐ 1 2n‐10 1 2 m ‐ 1
Memory data register m bits
Memory Cell
Select
R
S DOutputInput
R/W’ S RW’ D O/p
0 X X 00 X X 0
1 1 X D
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1 0 In 0
Memory Data Inputs
BC BC BC BC
W0
2x4 Dec
BC BC BC BC
BC BC BC BC
W1
Decoder
BC BC BC BCAddrW2
BC BC BC BC
Enable
W3
BC BC BC BCEnable
R/W’
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R/W
Data Outputs