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Charles Kime & Thomas Kaminski
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Chapter 4 – Combinational Functions and Circuits
Logic and Computer Design Fundamentals
Chapter 4 2
OverviewFunctions and functional blocksRudimentary logic functionsDecodingEncodingSelectingImplementing Combinational Functions Using:
• Decoders and OR gates• Multiplexers (and inverter)• ROMs• PLAs• PALs• Lookup Tables
2
Chapter 4 3
Functions and Functional Blocks
The functions considered are those found to be very useful in design Corresponding to each of the functions is a combinational circuit implementation called a functional block.In the past, many functional blocks were implemented as SSI, MSI, and LSI circuits. Today, they are often simply parts within a VLSI circuits.
Chapter 4 4
Rudimentary Logic Functions
Functions of a single variable XCan be used on theinputs to functionalblocks to implementother than the block’sintended function
0
1
F � 0
F � 1
(a)
F � 0
F � 1
VCC or VDD
(b)
X F � X
(c)
X F � X
(d)
TABLE 4-1Functions of One Variable
X F = 0 F = X F = F = 1
01
00
01
10
11
X
3
Chapter 4 5
Multiple-bit Rudimentary Functions
Multi-bit Examples:
A wide line is used to representa bus which is a vector signalIn (b) of the example, F = (F3, F2, F1, F0) is a bus.
The bus can be split into individual bits as shown in (b)Sets of bits can be split from the bus as shown in (c)for bits 2 and 1 of F. The sets of bits need not be continuous as shown in (d) for bits 3, 1, and 0 of F.
F(d)
0
F31 F2
F1A F0
(a)
01
A1
2 34
F0
(b)
4 2:1 F(2:1)2
F(c)
4 3,1:0 F(3), F(1:0)3
A A
Chapter 4 6
Enabling Function
Enabling permits an input signal to pass through to an outputDisabling blocks an input signal from passing through to an output, replacing it with a fixed valueThe value on the output when it is disable can be Hi-Z (as for three-state buffers and transmission gates), 0 , or 1When disabled, 0 outputWhen disabled, 1 outputSee Enabling App in text
XF
EN
(a)
ENX
F
(b)
4
Chapter 4 7
Decoding - the conversion of an n-bit input code to an m-bit output code withn ≤ m ≤ 2n such that each valid code word produces a unique output codeCircuits that perform decoding are called decodersHere, functional blocks for decoding are• called n-to-m line decoders, where m ≤ 2n, and• generate 2n (or fewer) minterms for the n input
variables
Decoding
Chapter 4 8
1-to-2-Line Decoder
2-to-4-Line Decoder
Note that the 2-4-linemade up of 2 1-to-2-line decoders and 4 AND gates.
Decoder ExamplesA D0 D1
0 1 0
1 0 1
(a) (b)
D1 � AA
D0 � A
A1
0011
A0
0101
D0
1000
D1
0100
D2
0010
D3
0001
(a)
D0 � A1 A0
D1 � A1 A0
D2 � A1 A0
D3 � A1 A0
(b)
A1
A0
5
Chapter 4 9
Decoder Expansion
General procedure given in book for any decoder with n inputs and 2n outputs.This procedure builds a decoder backward from the outputs.The output AND gates are driven by two decoders with their numbers of inputs either equal or differing by 1.These decoders are then designed using the same procedure until 2-to-1-line decoders are reached. The procedure can be modified to apply to decoders with the number of outputs ≠ 2n
Chapter 4 10
Decoder Expansion - Example 1
3-to-8-line decoder • Number of output ANDs = 8• Number of inputs to decoders driving output ANDs = 3• Closest possible split to equal
2-to-4-line decoder1-to-2-line decoder
• 2-to-4-line decoderNumber of output ANDs = 4Number of inputs to decoders driving output ANDs = 2Closest possible split to equal
• Two 1-to-2-line decoders
See next slide for result
6
Chapter 4 11
Decoder Expansion - Example 1
Result
3-to-8 Line decoder
1-to-2-Line decoders
4 2-input ANDs 8 2-input ANDs
2-to-4-Linedecoder
D0A0
A1
A2
D1
D2
D3
D4
D5
D6
D7
Chapter 4 12
Decoder Expansion - Example 27-to-128-line decoder
• Number of output ANDs = 128• Number of inputs to decoders driving output ANDs
= 7• Closest possible split to equal
4-to-16-line decoder3-to-8-line decoder
• 4-to-16-line decoderNumber of output ANDs = 16Number of inputs to decoders driving output ANDs = 2Closest possible split to equal
• 2 2-to-4-line decoders
• Complete using known 3-8 and 2-to-4 line decoders
7
Chapter 4 13
In general, attach m-enabling circuits to the outputsSee truth table below for function
• Note use of X’s to denote both 0 and 1• Combination containing two X’s represent four binary combinations
Alternatively, can be viewed as distributing value of signal EN to 1 of 4 outputsIn this case, called ademultiplexer
EN
A1
A0D0
D1
D2
D3
(b)
EN A1 A0 D0 D1 D2 D3
01111
X0011
X0101
01000
00100
00010
00001
(a)
Decoder with Enable
Chapter 4 14
EncodingEncoding - the opposite of decoding - the conversion of an m-bit input code to a n-bit output code with n ≤ m ≤ 2n such that each valid code word produces a unique output codeCircuits that perform encoding are called encodersAn encoder has 2n (or fewer) input lines and n output lines which generate the binary code corresponding to the input valuesTypically, an encoder converts a code containing exactly one bit that is 1 to a binary code corres-ponding to the position in which the 1 appears.
8
Chapter 4 15
Encoder Example
A decimal-to-BCD encoder• Inputs: 10 bits corresponding to decimal
digits 0 through 9, (D0, …, D9)• Outputs: 4 bits with BCD codes• Function: If input bit Di is a 1, then the
output (A3, A2, A1, A0) is the BCD code for i,The truth table could be formed, but alternatively, the equations for each of the four outputs can be obtained directly.
Chapter 4 16
Encoder Example (continued)
Input Di is a term in equation Aj if bit Aj is 1 in the binary value for i.Equations:A3 = D8 + D9
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7 + D9
F1 = D6 + D7 can be extracted from A2 and A1Is there any cost saving?
9
Chapter 4 17
Priority Encoder
If more than one input value is 1, then the encoder just designed does not work. One encoder that can accept all possible combinations of input values and produce a meaningful result is a priority encoder.Among the 1s that appear, it selects the most significant input position (or the least significant input position) containing a 1 and responds with the corresponding binary code for that position.
Chapter 4 18
Priority Encoder ExamplePriority encoder with 5 inputs (D4, D3, D2, D1, D0) - highest priority to most significant 1 present - Code outputs A2, A1, A0 and V where V indicates at least one 1 present.
Xs in input part of table represent 0 or 1; thus table entries correspond to product terms instead of minterms. The column on the left shows that all 32 minterms are present in the product terms in the table
1684211
No. of Min-terms/Row
0XXX00000
1001XXXX11110XXX101010XX1001100X1000100010000
VA0A1A2D0D1D2D3D4
OutputsInputs
10
Chapter 4 19
Priority Encoder Example (continued)
Could use a K-map to get equations, but can be read directly from table and manually optimized if careful:A2 = D4
A1 = D3 + D2 = F1, F1 = (D3 + D2)A0 = D3 + D1 = (D3 + D1)V = D4 + F1 + D1 + D0
D4 D3D4 D4
D4 D3D4 D2 D4 D2
Chapter 4 20
Selecting of data or information is a critical function in digital systems and computersCircuits that perform selecting have:
• A set of information inputs from which the selection is made
• A single output• A set of control lines for making the selection
Logic circuits that perform selecting are called multiplexersSelecting can also be done by three-state logic or transmission gates
Selecting
11
Chapter 4 21
Multiplexers
A multiplexer selects information from an input line and directs the information to an output lineA typical multiplexer has n control inputs (Sn − 1, … S0) called selection inputs, 2n
information inputs (I2n
− 1, … I0), and one output YA multiplexer can be designed to have minformation inputs with m < 2n as well as n selection inputs
Chapter 4 22
2-to-1-Line Multiplexer
Since 2 = 21, n = 1The single selection variable S has two values:
• S = 0 selects input I0
• S = 1 selects input I1
The equation:Y = I0 + SI1
The circuit:S
S
I0
I1
DecoderEnablingCircuits
Y
12
Chapter 4 23
2-to-1-Line Multiplexer (continued)
Note the regions of the multiplexer circuit shown:• 1-to-2-line Decoder• 2 Enabling circuits• 2-input OR gate
To obtain a basis for multiplexer expansion, we combine the Enabling circuits and OR gate into a 2 × 2 AND-OR circuit:
• 1-to-2-line decoder• 2 × 2 AND-OR
In general, for an 2n-to-1-line multiplexer:• n-to-2n-line decoder• 2n × 2 AND-OR
Chapter 4 24
Example: 4-to-1-line Multiplexer
2-to-22-line decoder22 × 2 AND-OR
S1Decoder
S0
Y
S1Decoder
S0
Y
S1Decoder
4 � 2 AND-ORS0
Y
I2
I3
I1
I0
13
Chapter 4 25
Multiplexer Width ExpansionSelect “vectors of bits” instead of “bits”Use multiple copies of 2n × 2 AND-OR in parallelExample:4-to-1-linequad multi-plexer
4 � 2 AND-OR
2-to-4-Line decoder
4 � 2 AND-OR
4 � 2 AND-OR
4 � 2 AND-OR
I0,0
I3,0
I0,1
I3,1
I0,2
I3,2I0,3
I3,3
Y0
D0
D3
A0
A1
Y1
Y2
Y3
.
.
.
.
.
....
.
.
.
.
.
.
Chapter 4 26
Other Selection Implementations
Three-state logic in place of AND-OR
Gate input cost = 14 compared to 22 (or 18) for gate implementation
I0
I1
I2
I3
S1
S0
(b)
Y
14
Chapter 4 27
Other Selection Implementations
Transmission Gate MultiplexerGate inputcost = 8comparedto 14 for3-state logicand 18 or 22for gate logic
S0
S1
I0
I1
I2
I3
Y
TG(S0 � 0)
TG(S1 � 0)
TG(S1 � 1)
TG(S0 � 1)
TG(S0 � 0)
TG(S0 � 1)
Chapter 4 28
Combinational Function Implementation
Alternative implementation techniques:• Decoders and OR gates
• Multiplexers (and inverter)
• ROMs
• PLAs
• PALs
• Lookup TablesCan be referred to as structured implementation methods since a specific underlying structure is assumed in each case
15
Chapter 4 29
Decoder and OR Gates
Implement m functions of n variables with:• Sum-of-minterms expressions• One n-to-2n-line decoder• m OR gates, one for each output
Approach 1:• Find the truth table for the functions• Make a connection to the corresponding OR from
the corresponding decoder output wherever a 1 appears in the truth table
Approach 2• Find the minterms for each output function• OR the minterms together
Chapter 4 30
Decoder and OR Gates ExampleImplement the following set of odd parity functions of (A7, A6, A5, A3)P1 = A7 A5 A3P2 = A7 A6 A3P4 = A7 A6 A5
Finding sum ofminterms expressionsP1 = Σm(1,2,5,6,8,11,12,15)P2 = Σm(1,3,4,6,8,10,13,15)P4 = Σm(2,3,4,5,8,9,14,15)Find circuitIs this a good idea?
+++
+++
0123456789101112131415
A7A6A5A4
P1
P4
P2
16
Chapter 4 31
Multiplexer Approach 1 Implement m functions of n variables with:
• Sum-of-minterms expressions• An m-wide 2n-to-1-line multiplexer
Design: • Find the truth table for the functions.• In the order they appear in the truth table:
Apply the function input variables to the multiplexer inputs Sn − 1, … , S0
Label the outputs of the multiplexer with the output variables
• Value-fix the information inputs to the multiplexer using the values from the truth table (for don’t cares, apply either 0 or 1)
Chapter 4 32
Example: Gray to Binary Code
Design a circuit to convert a 3-bit Gray code to a binary codeThe formulation givesthe truth table on therightIt is obvious from thistable that X = C and theY and Z are more complex
GrayA B C
Binaryx y z
0 0 0 0 0 01 0 0 0 0 11 1 0 0 1 00 1 0 0 1 10 1 1 1 0 01 1 1 1 0 11 0 1 1 1 00 0 1 1 1 1
17
Chapter 4 33
Gray to Binary (continued)
Rearrange the table sothat the input combinationsare in counting order
Functions y and z can be implemented usinga dual 8-to-1-line multiplexer by:
• connecting A, B, and C to the multiplexer select inputs• placing y and z on the two multiplexer outputs• connecting their respective truth table values to the inputs
GrayA B C
Binaryx y z
0 0 0 0 0 00 0 1 1 1 10 1 0 0 1 10 1 1 1 0 01 0 0 0 0 11 0 1 1 1 01 1 0 0 1 01 1 1 1 0 1
Chapter 4 34
Note that the multiplexer with fixed inputs is identical to a ROM with 3-bit addresses and 2-bit data!
Gray to Binary (continued)
D04D05D06D07
S1S0
AB
S2
D03D02D01D00
Out
C
D14D15D16D17
S1S0
AB
S2
D13D12D11D10
Out
C
11
1
1
11
11
00
0
0
0
0
0
0
Y Z
8-to-1MUX
8-to-1MUX
18
Chapter 4 35
Multiplexer Approach 2
Implement any m functions of n + 1 variables by using:• An m-wide 2n-to-1-line multiplexer• A single inverter
Design:• Find the truth table for the functions.• Based on the values of the first n variables, separate the truth
table rows into pairs• For each pair and output, define a rudimentary function of the
final variable (0, 1, X, )• Using the first n variables as the index, value-fix the
information inputs to the multiplexer with the corresponding rudimentary functions
• Use the inverter to generate the rudimentary function
X
X
Chapter 4 36
Example: Gray to Binary Code
Design a circuit to convert a 3-bit Gray code to a binary codeThe formulation givesthe truth table on therightIt is obvious from thistable that X = C and theY and Z are more complex
GrayA B C
Binaryx y z
0 0 0 0 0 01 0 0 0 0 11 1 0 0 1 00 1 0 0 1 10 1 1 1 0 01 1 1 1 0 11 0 1 1 1 00 0 1 1 1 1
19
Chapter 4 37
Gray to Binary (continued)Rearrange the table so that the input combinations are in counting order, pair rows, and find rudimentary functions
1 0 11 1 10 1 01 1 01 1 01 0 10 0 11 0 01 0 00 1 10 1 10 1 01 1 10 0 10 0 00 0 0
Rudimentary Functions of
C for z
RudimentaryFunctions of
C for y
Binaryx y z
GrayA B C
F = C
F = C
F = C
F = C
F = C
F = CF = C
F = C
Chapter 4 38
Assign the variables and functions to the multiplexer inputs:
Note that this approach (Approach 2) reduces the cost by almost half compared to Approach 1.This result is no longer ROM-likeExtending, a function of more than n variables is decomposed into several sub-functions defined on a subset of the variables. The multiplexer then selects among these sub-functions.
Gray to Binary (continued)
S1S0
AB
D03D02D01D00
Out Y
8-to-1MUX
CC
C
C D13D12D11D10
Out Z
8-to-1MUX
S1S0
AB
C
C
CCC C
20
Chapter 4 39
Read Only MemoryFunctions are implemented by storing the truth tableOther representations such as equations more convenientGeneration of programming information from equations usually done by softwareText Example 4-10 Issue
• Two outputs are generated outside of the ROM• In the implementation of the system, these two
functions are “hardwired” and even if the ROM is reprogrammable or removable, cannot be corrected or updated
Chapter 4 40
Programmable Array LogicThere is no sharing of AND gates as in the ROM and PLADesign requires fitting functions within the limited number of ANDs per OR gateSingle function optimization is the first step to fittingOtherwise, if the number of terms in a function is greater than the number of ANDs per OR gate, then factoring is necessary
21
Chapter 4 41
Productterm
AND Inputs
OutputsA B C D W
123
W = C
456
F1 = X = A + B + W
789
101112
———
———
———
———
———
AB
C
+ ABC
F2 = Y = AB + BC +AC
B CA
10—
01—
00—
———
——1
— —
01
01
11—
—
—
———
—
1—1
11—
—11
—
—
———
—
Equations: F1 = A + B + C + ABCF2 = AB + BC + AC
F1 must befactoredsince fourtermsFactor outlast twoterms as W
A BB C C A
Programmable Array Logic Example
Chapter 4 42
Programmable Array Logic Example
X
XX
XX
XX
X XX
X X X
XX X
X X X
AND gates inputs
A C WProductterm
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
W
F1
F2
All fuses intact(always � 0)
X Fuse intact
X
A B B C D D W
A C WA B B C D D W
� Fuse blown
22
Chapter 4 43
Programmable Logic Array
The set of functions to be implemented must fit the available number of product termsThe number of literals per term is less important in fittingThe best approach to fitting is multiple-output, two-level optimization (which has not been discussed)Since output inversion is available, terms can implement either a function or its complementFor small circuits, K-maps can be used to visualize product term sharing and use of complementsFor larger circuits, software is used to do the optimization including use of complemented functions
Chapter 4 44
Programmable Logic Array Example
K-mapspecificationHow can thisbe implementedwith four terms?Complete the programming table
Outputs
123
4
F2
11
–1
ABACBC
Inputs
–11
C
11–
A
1–1
B
PLA programming table
(T)F1
( )Productterm
F1 � ABC + A B C + A B CF1 � AB + AC + BC + A B C
0
C
0
1
0 1
0 0
00 01 11 10BC
A
0
B
1
1A
0
C
0
1 0
1 1
00 01 11 10BC
A
1
B
0
1A
F2 � AB + AC+ BCF2 � AC + AB + BC
0
23
Chapter 4 45
Programmable Logic Array Example
X Fuse intact
� Fuse blown
0
1
F1
F2
A
B
C
C B AC B A
1
2
4
3
X X
X X
X X
X XX
X
X
X X
X
X
X
X
X
Chapter 4 46
Lookup TablesLookup tables are used for implementing logic in Field-Programmable Gate Arrays (FPGAs) and Complex Logic Devices (CPLDs)Lookup tables are typically small, often with four inputs, one output, and 16 entriesSince lookup tables store truth tables, it is possible to implement any 4-input functionThus, the design problem is how to optimally decompose a set of given functions into a set of 4-input two- level functions.We will illustrate this by a manual attempt
24
Chapter 4 47
Lookup Table Example
Equations to be implemented:F1(A,B,C,D,E) = A D E + B D E + C D E F2(A,B,D,E,F) = A E D + B D E + F D EExtract 4-input function:F3(A,B,D,E) = A D E + B D EF1(C,D,E,F3) = F3 + C D EF2(D,E,F,F3) = F3 + F D EThe cost of the solution is 3 lookup tables
Chapter 4 48
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