Post on 10-Nov-2018
Introduction to CMOS VLSI
Design
Layout, Fabrication, and Elementary Logic Design
Adapted from Weste & Harris CMOS VLSI Design
CMOS VLSI Design Fabrication and Layout Slide 2
Overview Implementing switches with CMOS transistors
How to compute logic functions with switches
Fabricating transistors on a silicon wafer and connecting them together
CMOS VLSI Design Fabrication and Layout Slide 3
Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors
CMOS VLSI Design Fabrication and Layout Slide 4
Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type)
CMOS VLSI Design Fabrication and Layout Slide 5
p-n Junctions A junction between p-type and n-type semiconductor
forms a diode. Current flows only in one direction
CMOS VLSI Design Fabrication and Layout Slide 6
nMOS Transistor Four terminals: gate, source, drain, body Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors – SiO2 (oxide) is a very good insulator
CMOS VLSI Design Fabrication and Layout Slide 7
nMOS Operation Body is commonly tied to ground (0 V) When the gate is at a low voltage:
– Source-body and drain-body diodes are OFF – No current flows, transistor is OFF
CMOS VLSI Design Fabrication and Layout Slide 8
nMOS Operation When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor – Negative charge attracted to body – Inverts a channel under gate to n-type – Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
CMOS VLSI Design Fabrication and Layout Slide 9
pMOS Transistor Similar, but doping and voltages reversed
– Body tied to high voltage (VDD) – Gate low: transistor ON – Gate high: transistor OFF – Bubble indicates inverted behavior
CMOS VLSI Design Fabrication and Layout Slide 10
Power Supply Voltage GND = 0 V In 1980’s, VDD = 5V VDD has decreased in modern processes
– High VDD would damage modern tiny transistors – Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
CMOS VLSI Design Slide 11
Transistor Abstraction 3D structure formed by fabrication 2D planar “layout” view Schematic symbol Switch
CMOS VLSI Design Fabrication and Layout Slide 12
Transistors as Switches We can view MOS transistors as electrically
controlled switches Voltage at gate controls path from source to drain
CMOS VLSI Design Slide 13
a b
s d
a
b
s d
a
b
s d
a b
s d
conducts iff a•b
(0 only)
conducts iff a'•b' or (a+b)'
(1 only)
conducts iff a'+b' or (a•b)'
(1 only)
conducts iff a+b
(0 only)
Switching Logic
CMOS VLSI Design Slide 14
a
b
1 f(a,b)
a b a + b
0 0 0
0 1 1
1 0 1
1 1 1
Implementation of Logic Gates
OR gate
Two problems – 1) when a=b=0, f(a,b) is undefined (floating) – 2) n- type switches do not conduct 1 well
Two solutions – when f=0, connect output to 0v using n-type switches – when f=1, connect output to 1v using p-type switches
CMOS VLSI Design Slide 15
inputs output
P
N
1v (logic 1)
0v (logic 0)
pull-up
pull-down
a a'
a a'
0 1
1 0
↑: a'
↓: a
Complementary CMOS Gates Pull-up network consisting of p-type devices Pull-down network consisting of n-type devices
Example: an inverter
CMOS VLSI Design Fabrication and Layout Slide 16
CMOS Inverter
A Y
0
1
CMOS VLSI Design Fabrication and Layout Slide 17
CMOS Inverter
A Y
0
1 0
CMOS VLSI Design Fabrication and Layout Slide 18
CMOS Inverter
A Y
0 1
1 0
CMOS VLSI Design Fabrication and Layout Slide 19
CMOS NAND Gate A B Y
0 0
0 1
1 0
1 1
CMOS VLSI Design Fabrication and Layout Slide 20
CMOS NAND Gate A B Y
0 0 1
0 1
1 0
1 1
CMOS VLSI Design Fabrication and Layout Slide 21
CMOS NAND Gate A B Y
0 0 1
0 1 1
1 0
1 1
CMOS VLSI Design Fabrication and Layout Slide 22
CMOS NAND Gate A B Y
0 0 1
0 1 1
1 0 1
1 1
CMOS VLSI Design Fabrication and Layout Slide 23
CMOS NAND Gate A B Y
0 0 1
0 1 1
1 0 1
1 1 0
CMOS VLSI Design Fabrication and Layout Slide 24
CMOS NOR Gate A B Y
0 0 1
0 1 0
1 0 0
1 1 0
CMOS VLSI Design Fabrication and Layout Slide 25
3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0
CMOS VLSI Design Fabrication and Layout Slide 26
3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0
CMOS VLSI Design Slide 27
2:1
a
b
f
s
f=a, when s=0
f=b, when s=1
f=s'a+sb
Switch Logic vs. Gate Logic
Example: two-input multiplexer
CMOS VLSI Design Slide 28
complementary pass transistor
Switch Logic vs. Gate Logic
Two-input mux with gate logic (14 transistors)
Two-input mux with switch logic (6 transistors)
CMOS VLSI Design Slide 29
F
A
A'
B
B'
C
C'
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Implementing LUTs Multiplexor logic – simple switch network (a tree)
– inputs: programming bits – controls: inputs to CLB – output: function value
However, series transistors are slow – O(n2)
CMOS VLSI Design Slide 30
Programmable Interconnect Switches connect wires at intersections Can also be used to segment wire Repeaters needed every so often
– simple non-inverting buffers (2 inverters) – otherwise, too many switches in series slow down signal
CMOS VLSI Design Slide 31
Master-Slave Register
CMOS VLSI Design Slide 32
Dynamic Register
CMOS VLSI Design Slide 33
CL
CL CL
this circuit can use the entire clock cycle – no wasted time - a form of retiming
straightforward implementation
φ1
φ1
φ2
φ2
Latch-Based Design Switches and/or gates compute new values to store
on next clock cycle
CMOS VLSI Design Slide 34
bit bit'
rd or wr
(rd or wr)'
Static Memory Cell 8-transistor cell N-transistor only: 6T cell
CMOS VLSI Design Slide 35
storage capacitor is one end of transistor
charge sharing with
bus capacitance
(Ccell << Cbus)
extra demands on sense amplifier to detect small changes in bus charge
precharge to intermediate voltage level
destructive read (must immediately write back)
Dynamic Memory Cell 1-transistor cell
CMOS VLSI Design Slide 36
Dynamic storage Capacitor implemented by gate capacitance of
transistor No capacitor is perfect
– charge leaks away through imperfect switches Must be replenished or refreshed
– 'memory' lasts about 1ms Solution: periodically read the value and write it back
CMOS VLSI Design Slide 37
bit1 bit2 bit3
read1
read2
programmable logic array structure
(exploits distributed NOR gate structure)
Read-only Memory Cells To store constants or other invariant data Popular for control implementation
CMOS VLSI Design Slide 38
row-bus1
row-bus2
bus1
bus2 bus1'
bus2'
Multi-ported Register Cells Augment 6T cell for more I/O
CMOS VLSI Design Fabrication and Layout Slide 39
CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or
etched Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing process
CMOS VLSI Design
The wafer Czochralski process
– Melt silicon at 1425 °C – Add impurities (dopants) – Spin and pull crystal
Slice into wafers – 0.25mm to 1.0mm thick
Polish one side
CMOS VLSI Design
CMOS VLSI Design
Crystal and wafer
Wand (a finished 250lb crystal)
A polished wafer
CMOS VLSI Design
4X reticle
Wafer
The mask Illuminate reticle on wafer
– Typically 4× reduction Typical image is 25×25mm
– Limited by focus Step-and repeat across wafer
– Limited by mechanical alignment
CMOS VLSI Design Reference: FULLMAN KINETICS
Lithography Patterning is done by exposing photoresist with light Requires many steps per “layer”
Example: Implant layer
CMOS VLSI Design
Grow Oxide Layer
Reference: FULLMAN KINETICS
CMOS VLSI Design Reference: FULLMAN KINETICS
Add Photoresist
CMOS VLSI Design Reference: FULLMAN KINETICS
Mask
CMOS VLSI Design Reference: FULLMAN KINETICS
Expose using UV Light
CMOS VLSI Design Reference: FULLMAN KINETICS
Develop and Remove Resist
CMOS VLSI Design Reference: FULLMAN KINETICS
Etch Silicon Dioxide
CMOS VLSI Design Reference: FULLMAN KINETICS
Remove Resist
CMOS VLSI Design Reference: FULLMAN KINETICS
Implant Dopant
CMOS VLSI Design Fabrication and Layout Slide 53
Inverter Cross-section Typically use p-type substrate for nMOS transistor
– Requires n-well for body of pMOS transistors – Several alternatives: SOI, twin-tub, etc.
CMOS VLSI Design Fabrication and Layout Slide 54
Inverter Layout Transistors and wires are defined by masks Cross-section taken along dashed line
CMOS VLSI Design
Advanced Metallization - Copper
Copper versus Aluminum ~ 40% lower resistivity ~ 10× less electromigration
CMOS VLSI Design Slide 56
A View of Interconnect Layers
CMOS VLSI Design
Package-to-Board Interconnect
© Digital Integrated Circuits2nd
CMOS VLSI Design
Flip-Chip Bonding
© Digital Integrated Circuits2nd
CMOS VLSI Design
Package Types
© Digital Integrated Circuits2nd
CMOS VLSI Design
Multi-Chip Modules
© Digital Integrated Circuits2nd