Post on 05-Feb-2016
description
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
A 0.13um CMOS Rad-hard proven technology with associated mixed mode circuit design
approaches for space applications
Laurent Dugoujon (1), Constantin Papadas (2) and Bill Sinnis (2)1) ST Microelectronics, 12 rue Jules Horowitz, B.P. 217, 38019 Grenoble Cedex, France2) Integrated Systems Development S.A., Atrina Center, Building B, 32 Kifisias Avenue, 15125 Marousi, Greece.
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
INTRODUCTION
New Telecommunications Satellites must offer:
• High data throughput
• Uninterrupted Service
• High Reliability
• Competitive costs
- The usage of Deep-Sub-Micron technology is now mandatory to keep-up with US manufacturers -
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
KEY FUNCTIONS
Some functions are « key » to succes:
• Broadband Analog-Digital Converters: ADC & DAC
• High Speed Serial Links
• Digital Processing ASICs
- For these key components, only modern technology nodes (<=0.25um) can fulfill the specifications -
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
TECHNOLOGY / FUNCTIONS
0.25um 0.13um 0.09um
DC-1GHz
Analog functions
1-2GHz Mixed
Analog & Digital
1-4GHz
HSSL
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
RH at PROCESS LEVEL
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
HCMOS9 Core Process
4 or 6 Cu Dual Damascene Metal levels0.41µm pitch metallization, Low k dielectric
0.13µm Technology Platforms
Digital/Analog/RF convergence
HCMOS9 SOIBICMOS9
HCMOS9 SiGeHCMOS9 SiGe
HCMOS9 A
HCMOS9DRAM0. 39/ 0.53µm²
HCMOS9i
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
HCMOS9 : Device list MOSFETs 1.2V HS 0.13µm CMOS (GO1 : 20A) 1.2V LL 0.13µm CMOS (GO1 : 20A) 2.5V CMOS (GO2 : 50A) 2.5V HS CMOS (GO2 : 50A) (option) DRIFT N & P MOS transistors (GO2:50A) NMOS SRAM (option)
RESISTORS Silicided N+ Poly; 10 Ohm/sq Unsilicided p+ Active; 135 Ohm/sq Unsilicided P+ Poly; 320 Ohm/sq Hipo; 1KOhm/sq (option) Unsilicided N+ Poly; 110 Ohm/sq
CAPACITORS 2 fF/µm² MIM capacitor (option) N+Poly/NWell capacitor (GO2:50A) P+Poly/PWell capacitor (GO2:50A) Interdigited Metal fringe capacitor (MOM) Intermetal capacitor (MEM)
JUNCTION DIODES N+/Pwell P+ /Nwell
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
ST 130 & 90nm SRAMs are invulnerable to thermals
Thermal neutrons highly interact with Boron10
Highest concentration of Bo10 in today’s IC :
borophosphosilicate glass (BPSG) film : not used in ST technologies
Test on 130nm ST SRAMs at ILB, Paris : no SEU with a fluence >1011n/cm2
Test on a 90nm SRAMs at TRIUMF, Vancouver : no SEU variations with & without Cadnium shielding
Oxy
gen
10-3
10-2
10-1
100
101
102
103
104
Neu
tron
Cro
ss-s
ectio
n (b
arns
)
Tun
gste
nT
itani
umA
rsen
icC
oppe
rN
itro
gen
Alu
min
um
Bor
on-
11
Pho
sph
orus
Sili
con
BO
RO
N 1
0
7Li Recoil
- particle1.47 MeV
Low Energy Neutron
10B Fissio
n
0.84 MeV
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
TID characterizations for 130nm MOSFETs & (r)SRAMs
Linear transistors 130nm (thin oxide) @ 30 MradSi - Tests performed by CERN
Threshold voltage shift < 10 mV : negligible Subthreshold swing variations : negligible Transconductance degradation of less than 10%
Linear transistors 130nm (thick oxide) @ 30 MradSi - Tests performed by CERN
Threshold voltage shift < 35 mV : negligible Transconductance degradation of less than 10%
Two 130nm 1Mb SRAMs, standard and rSRAM tested at BNL @ 1 MradSi :
No bit error detected for each memory cut at initial and after each exposure step (0, 100, 500 and 1000Krads(Si))
Full functionality verified for the 2 cuts after being exposed to 1Mrad(Si).
These experimental results confirm the strong robustness of ST 130nm MOSFETS, SRAM and robust SRAMs
CERN test report : “specifications should be met in terms of radiation requirements WITHOUT using enclosed transistors (with obvious benefits)”
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
1.E-09
1.E-08
1.E-07
1.E-06
0 5 10 15 20 25 30 35 40 45 50 55 60LET [MeV/cm2.mg]
Cro
ss
-se
cti
on
pe
r b
it [
cm
2]
Standard SRAM
rSRAM (Cap.1)
rSRAM (Cap.2 > Cap.1)
Responses to HI of 130nm regular & robust rSRAMsExperiments performed at the BNL, NY, 01/2004
Std SRAM
rSRAM ref.
The rSRAM has both a lower LETth (x10) & X-section at sat. (/3) than the regular SRAM
No SEL recorded up to 80 MeV/cm2.mg for all tested SRAMs
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
RH at LIBRARY LEVEL
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
RHBD: Library Level
StandardGuardbands
NAND Gate
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
RHBD: Library Level
Or … • Trench capacitors• Drain degeneration by drain contact distance• Silicide protect• Salicide protect
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
RHBD: Library Level
Standard (6 xtors)
Redundant (14 xtors)
Redundant Latch
Layout
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
RHBD: Library Level
D
Vote
Q1
Q2
Q3
QN1
QN2
QN3CK
>
>
>
Reset
Reset
Reset
Q
QN
Latch1
Latch2
Latch3
Triple Voting Scheme
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
RH at DESIGN LEVEL
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
Memory Core
Addl. Cols.
EDAC
Flag
Error Code Correction
(eg Hamming)
ECC
RHBD: Architecture Level
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
rSRAM validation Testchip in 130 nm
Chip micrograph
Content :•SRAM Standard 1Mb
memcell 2.5 µm2
•SRAM Standard 1Mb memcell 2.5 µm2 with Triple Well
•rSRAM 1Mb robust memcell 2.5 µm2
•rSRAM 1Mb robust memcell 2.5 µm2 - ver. 2 (lower capacitor value)
•50x164Kbrobust memcell 2.5 µm2
Package : •PBGA 27x27 276+16
1Mb
SRAM
1Mb
SRAM1Mb
rSRAM
1Mb
rSRAM
PLL, BIST, Laser Fusesscribes
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
SRAM
Specifications
rSRAM
in %
SRAM ECC1,2
in %
tcycle (ns) 4.2 1.50 +5 % +1% 0 %
taa (ns) 3.7 0.95 +5 % +1% one cycle later
area (mm2) 3.6 0.4 0 0 +25%
power (µW/MHz) 160 50 +20 % +5% +40 %
leakage (uA, WC) 1016 400 0 0 +20-25%
Process Standard eDRAM option Standard
Wafer cost 1 1.10 1
Die cost
(10Mb/ 32-bit word) 1 1.10 >1.25
Note1 : pipeline architecture, Note2 : penalty induced by the additional parity bits (= +7 bits for a 32 bit-word ) and combinatonial logic (XOR stage)
Relative perf between a standard, robust and ECC SRAM130nm Single-Port SRAM - 32kx32 HCMOS9GP-LL, typical corner, 1V2, room temp.
90nm Single-Port SRAM - 8kx32 CMOS90-GP, typical corner, 1V, room temp.
rSRAM offers lower die cost than ECC with a similar robustness
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
Neutron accelerated results @ 1.2V Alpha accelerated results @ 1.2V
Alpha & neutron responses of the 130nm rSRAM
Experiments performed at Los Alamos and Crolles, 2003
Nominal Conditions
(1.2 V, room temp)
SRAM standard
cell area=2.5 µm2
rSRAM
cell area=2.5 µm2
Alpha fail rate 37,000 fails/min 0 after 23h, Th232
Neutron fail rate 1,195 fails after 6 h 8 fails after 6 h
Total SER FIT/Mb 1475 ± 6 6 ± 4
ST rSRAM provides a robustness enhancement by ×250 :
SER < 10 FIT/Mb @ 1.2 V + full immunity @ 1.32 V
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
RHBD: Library Mapping (synthesis)
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
Robust Designs: PLL and Sense Amplifier
LOGO
UWBTBA
TA
P0
PLL
Sense amplifier
PLLTechnology: 0.13umLocking Frequency: 620MHzCtoC Jitter: 17psPower Consumption: 340mW
Sense AmplifierTechnology: 0.13umBandwidth: 4GHzGain: 12dbPower Consumption: 15mW
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
Robust Designs: 64x1bit ADC
64x1bit-ADCTechnology: 0.13umSampling Frequency: 3GHzPower Consumption: 500mW
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
Robust Designs: 10bit DAC
10bit-DACTechnology: 0.13umTopology: Current SteeringSampling Frequency: 15MHzSignal bandwidth~2.5MHzENOB: 8.73bitsImax=1.4mANoise: +/- 2LSB
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
Robust Designs: 10bit ADC
10bit-ADCTechnology: 0.13umTopology: Interleaved SARSampling Frequency: 1.3GHzConsumption: 400mWENOB: in testNoise: in test
AMICSA’2006 II DDSSIntegrated Systems Development S.A.
CONCLUSION
It is the CONJUNCTION of 3 main levels of efforts which can maximize the Radiations performances:
• Intrinsic good choices at Si process level (materials,...)• usage of validated mitigation techniques (libraries, options,...)• design for Rad-hard (architecture, registers,...)
We are able to manage all these levels with additional know-how from space industry trough contractual projects