Post on 30-Dec-2015
Interrupt Controller for DSP-based Control of Multi-Rail DC-DC Converters with Non-Integer Switching Frequency Ratio
James Mooney, Simon Effler, Mark Halton, Hussain MahdiUniversity of Limerick
james.mooney@ul.ie
15/12/2010
Overview Introduction to DSP-based Control of Multi-Rail DC-DC
Converter Systems
Interrupt Management for Multiple Control Loops
Modified Interrupt Controller
Multi-rail DC-DC Converter Application
Conclusions
DSP-based Control of Multi-Rail DC-DC Converter Systems
Multiple DC-DC converters are compensated by a single DSP-based digital controller
An interrupt signal triggers execution of a control algorithm when a new ADC sample is available
Interrupt-Triggered Control With Integer Multiple Frequency Ratios
For multiple converters interrupt signals are interleaved so that each control loop’s interrupt service routine has a fixed time slot
Constraining switching frequencies to integer multiples of each other can impact efficiency or performance of converters
Interrupt-Triggered Control With Non-Integer Multiple Frequency Ratios A delay in the calculation and updating of the duty cycle for at least one
converter will occur if:
An interrupt is triggered when a control algorithm is already being executed
Multiple interrupt signals are triggered simultaneously
The delay can vary each time an interrupt is triggered
Interrupt-Triggered Control With Non-Integer Multiple Frequency Ratios If duty cycle has not been calculated by beginning of next
switching cycle, DPWM will apply duty cycle from previous cycle
If load transient occurs:
Duty cycle update delay will result in slower response in output voltage
Instability could occur if delay occurs for a number of consecutive cycles
Maximum ADC Sample to Duty Cycle Update Delay To avoid problems with variable delay, fix delay at maximum for
each iteration of each algorithm
For a particular algorithm
Maximum fixed delay is excessive and degrades performance of voltage regulator due to slower response to load transients
DC
HP
iPCDCADCDMAX TTTTT
ii
0
Modified Interrupt Controller Modified interrupt controller reduces TDMAX to acceptable value to obtain improved
performance:
All interrupts are automatically re-enabled after control algorithm has passed a certain stage of execution
Allows interruption of one algorithm by another during pre-calculation stage, after duty cycle calculation and DPWM updating has been completed
DC
HP
iDCADCDMAX TTTT
i
0
*
Modified Interrupt Controller Improved interrupt scheme can be achieved by augmenting a conventional
DSP’s interrupt controller with minimal additional hardware:
Counter that determines when to re-enable interrupts
Registers to store interrupt return addresses and duty-cycle calculation times for each algorithm in terms of number of instructions required
Multi-Rail DC-DC Converter Application
FPGA Implementation Dual Datapath DSP core with
modified interrupt controller
Multi-rail switching mode power supply system 3 buck converters 12V – to – 1.5 V 500 & 495 kHz switching
frequencies
3rd order linear compensator applied to each converter 6 duty-cycle operations 6 pre-calculation operations
Interrupt Controller Operation - Comparison
Standard Modified
Interrupt Controller Operation - Standard
1) Int0 triggered
2) Int1 triggered
3) ISR0 executed
4) ISR1 executed
Interrupt Controller Operation - Comparison
Standard Modified
Interrupt Controller Operation - Modified
1) Int0 triggered2) Int1 triggered3) ISR0 started4) ISR0 duty cycle calculation completed5) ISR1 executed6) Remainder of ISR0 executed
Performance Comparison
Modified interrupt method has shorter TDMAX delay
This facilitates the use of a wider bandwidth compensator
Result: Improved performance in response to load step
Standard Modified
Conclusions Drawback of a standard DSP controlling multiple power converters
is its limitation in dealing with switching frequencies with non-integer ratios
ADC-sample to duty-cycle-update delay
Existing DSPs have excessive delay
Proposed method has a constant, reduced and hence more desirable delay
Proposed interrupt controller performs significantly better in non-integer switching frequency applications Demonstrated using a three-rail power converter prototype
Thank you for your attention!
Questions?
james.mooney@ul.ie
Thank you for your attention!
Questions?
james.mooney@ul.ie
Backup Slides
Comparison with Standard Interrupt Method
Manually enabling and disabling interrupts
Comparison with Standard Interrupt Method Separate interrupts for duty cycle calculation and pre-
calculation code sections
Duty cycle updated early in switching cycle
Duty cycle updated just in time to be applied