HPEC 09 -1HN 9/23/2009

MIT Lincoln Laboratory

RAPID:A Rapid Prototyping Methodology for

Embedded Systems

Huy Nguyen, Thomas Anderson, Stuart Chen, Ford Ennis, Michael Eskowitz, Andy Heckerling, Tanya Kortz, George Lambert , Larry Retherford, Michael Vai

HPEC 2009

23 September 2009

This work is sponsored by the Department of the Air Force under Air Force contract FA8721-05-C-0002. Opinions, interpretations, conclusions and recommendations are those of the author and are not necessarily endorsed by the United States Government.

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RAPID - Rapid Advanced Processor In Development

CustomVME / VPX

MicroTCA

COTS Boards

ControlSig. Proc.

Capture

Composable Processor

Board

Form Factor Selection

Des

ign

FPGA Container

Infrastructure

IOKnown Good Designs

RAPID Tiles and IP Library

Main features of RAPID:• Composable board design process

– Custom processor composed of tiles extracted from known-good boards Form factor highly flexible

– Tiles accompanied with verified firmware / software for host computer interface• Container framework allowing co-design of boards and IPs

– Portable FPGA Container Infrastructure with on-chip control infrastructure, off-chip memory access, and host computer interface

– Surrogate board can be used while target board(s) are being designed or purchased

Ports

Bus

RegsFPGA

FunctionCore

MemoryInterface

Container

Control

Ports

Bus

RegsFPGA

FunctionCore

MemoryInterface

Container

Control

System Architecture

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Composable Board Design Flow

Known Good Boards

Extract circuit block of interest(Known Good Circuit)

Tile Re-use Library

Hierarchical Composite

“Known Good Tile”

Physical Design Reuse

tool

RAPID Design Board

Verify

Reduces time 50% to 66% as well as increases probability of first-spin success

DurationApproach

Sche-matic

Layout Manu-facture

Test & Debug

Total(mos.)

Start from scratch 3-6 2-4 1-2 1-2 7-14Known Good Board 1-3 1-3 1-2 1-2 4-10Known Good Tiles 0.5-1 0.5-1 1-1.5 1-1.5 3-5

Board design time

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RAPID System Development

• 6 months head start on surrogate system– Overlapping of FPGA and board design– Standardized control interface allows smooth porting to objective system

• 2 months saved in system debug and integration– Incremental integration with local storage for data path source / sink

Full capabilityRAPID board

design

ADCDIQ FIR ABF

PacketForming

Sample Timing Control

PacketForming

ADC data

Processed dataAnalog data

Timing signals

Control* Control*

Data path

RAPID Processor

Initial capability

Development Timeline

*A. Heckerling, T. Anderson, H. Nguyen, et.al., An Ethernet-Accessible Control Infrastructure For Rapid FPGA Development, HPEC 2008.

~12 months

~13-14 months