High-Speed CMOS Circuit Techniques

for Broadband Communications

Jri Lee

Electrical Engineering DepartmentNational Taiwan University

Outline

Broadband Amplifiers

VCOs

Frequency Dividers

Introduction

Conclusion

• Design Considerations

• Cross-Coupled• Colpitts• mm-Wave Associated

• Static• Regenerative• Injection-Locked

• High-Speed Techniques

The Past and The Future

CMOS Device in 5-10 Years

Minimum device length ~ 10 nm!

• Gate oxide > 1nm (otherwise tunneling)• Channel length > 10x gate oxide (otherwise no gate control)

Forecast the future• “640k ought to be enough for anybody”- Bill Gates, 1981• “No exponential is forever... but we can delay 「forever」”

- Gordon Moore, 2003

1950 2000 Year

CMOS Boundaries

Voltage Limitation• In sub-threshold, • For inverter with reasonable gain, VDD,min = 100 mV.

Energy Limitation• Moving 3 electrons (1 for NMOS, 2 for PMOS) across

0.1 V requires 0.3 eV.• In 90nm CMOS, one operation of minimum-size inverter

needs = 0.8 fJ = 0.3 eV × 50,000.• For 10nm inverters Ctot = 20 aF.

Switching energy = 1.25 eV.12 electrons in one node!

)1)(e1(e DSSD

DSGS

VII qkTV

qnkTV

λ+−=−

//

Supply Limitations on High-Speed Circuits

1 Overdrive for current source (~250 mV)

1 Overdrive to switch current (~250 mV)

BER=10

SNR=14

250 mV

－12

)2

(2

exp21

n

PP2

tote,n0 σ

=−

π= ∫

∞

σ

VQdxxPV

Supply reduction will stop at 0.7~0.8V if we have nothing better than CML.

Applications at Ultra High Frequencies

O2

O2

H2O

60 GHz Indoor Comm.77 GHz Automotive94 GHz Cloud Radars140 GHz P-to-P Comm.

20 Gb/s Backplane40 Gb/s Optical Links

100 Gb/s Ethernet

Evolution of PLL Circuits

Extending the Bandwidth by CascadingCascading identical gain stages

For a given technology, gain bandwidth constant

totopt1/n

1/ntot

tot ln2 12GBWBW AnA

=−=

12BW 1/n0tot −ω=

Gain increases faster than bandwidth decreases.

≅

dB 40tot =A

dB 50tot =A

dB 60tot =A

(but usually we have n≦5 )

×

Offset-Cancellation Technique

outos,1mFoutos,inos, ][ VARGVV =−

1mF

inos,

inos,1mF

outos, 1

RGV

VRAG

AV

≈

+=

FF1mF

FF1m

in

out1

)(1RsCRAG

RsCRAGV

V++

+=

Offset cancellation introduces one zero and one pole.Lower corner defined by standards.

Scrambler or encoder removes the near-dc power

(Offset reduced by A)

Inductive Peaking

Powerful technique.No extra power dissipation.Area consuming.

ζω

ωζωζω

222 n

2nn

2n

Dmin

out

+++

−=ss

sRgVV

LD3dB 2

1.79CR

fπ

=−

21/=ζfor

Extend the bandwidth by 79% (considering parasitics: around 40%). Widely used all over the place.

Dual-Resonance Peaking

14

3

12

11

6

2

1

ω=ω

ω=ω

=ωCL

CR1dB3

32=ω−

Triple-Resonance Architecture [Galal, ’04]

Response Analysis:

Dual-Resonance Peaking

14

3

12

11

6

2

1

ω=ω

ω=ω

=ωCL

CR1dB3

32=ω−

Triple-Resonance Architecture [Galal, ’04]

Response Analysis:

Dual-Resonance Peaking

14

3

12

11

6

2

1

ω=ω

ω=ω

=ωCL

CR1dB3

32=ω−

Triple-Resonance Architecture [Galal, ’04]

Response Analysis:

Dual-Resonance Peaking

14

3

12

11

6

2

1

ω=ω

ω=ω

=ωCL

CR1dB3

32=ω−

Triple-Resonance Architecture [Galal, ’04]

Response Analysis:

Alternative Dual-Resonance Peaking Reversed TRA [Liao, ’08] Double Series [Kim, ’05]

π-Peaking Network [Jin, ’08]

CR

CR

CL

1dB3

1

4

3

12

11

93

62

2

1

.=ω

=ω

ω=ω

=ω

−

Application of Inductive PeakingHigh-Speed Selector [Lee, ’05]

Pushing internal bandwidth to speed up switching.Applicable to other CML switching circuits.

Cherry-Hooper AmplifiersCoupling trans-impedance and trans-admittance amplifiers.

Increase the bandwidth at a cost of modulate gain.

m2

m1Fm1

in

outggRg

VV

−=X

m2Xp, C

g≈ω

Voltage headroom issue.Output CM level issue.

Popular architecture in BJT

Y

m2Yp, C

g≈ω

Ex: 43 Gb/s TIA-LA, [Tran, ’04]

Challenges of CMOS Cherry-Hooper AmplifiersHigh supply

Incompetent current source/source follower (also need CMFB)

Resistive load becomes the only possibility

Uncertain output swing and dc level

Gain degrades. (still IR drop)

Finite current goes through RF unless ISS1RD1 = ISS2RD2

Other Broadband Techniques

Din2in1mout )( RVVgV −=

fT Doubler

Multi-Stage

Active Feedback

GD1L1m1

L1m1M7 1

1CRgRgC

−+

≅

Feedback pair M5-M6

Miller Cap. Cancellation M7-M8

Broadband Technique Comparison

Two-Stage Amplifiers simulated in 65-nm CMOS

Resistive Loadw/i Inductive Peaking

w/i Dual PeakingCherry-Hopper

Cherry-Hopper w/I Active Feedback

Capacitive Degeneration

Two poles and one zero.Usually used as equalizing filters.Severe tradeoff between gain and boosting.

Capacitive Degeneration

Three poles, two zeros.The second zero extends the gain boosting by canceling the first pole.

Distributed AmplifierCascode with peaking

Ideally infinite gain and infinite bandwidthVoltage gain proportional to length l (i.e., number of stages)

Cascaded Segments

vlfnZgA T

0Lmv 2

π≈=

[Shigematsu, ’02]

Difficulties of Distributed AmplifierTransmission Line Loss

Loss-Compensation

Insufficient Gain / Complex Routing

Stage-Reuse Architecture

[Moez,’07][Arbabian, ’08]

• Top metal thickness < 1μm in nano-scale CMOS tech.

• For Q = 7, wave amplitude halves after λ/2 propagation

• Most DAs provide gain < 15dB

• Not efficient in area using

Fundamental Oscillation TheoryBarkhausen Criteria

20

signal

noise10 )(1)(log10

ωΔω

⋅∝=ωΔQP

P)L(

)1

(log10)(log10FOMmW10

2

010

P+

ωωΔ

+ωΔ= )L(

1)( osc =ωjAo180)( osc =ω∠ jA

Cross-Coupled Oscillators

Estimation ωosc :

m1,2OSCP

1g

LQR =ω⋅=

T

GSoscm

GS

11

1

ω⋅=

ω

=

≈

Q

CQg

LCOSCω

Unbounded oscillation frequency!However, physical Limitations:

• fSR of on-chip inductors• Varactor loss

• Inductor loss• Significant CP

Modifications of Cross-Coupled VCOsTop Biasing

Noise Blocking

Dual Pairs

Differential Control

Resonating ElementsInductor StructuresDifferential Stacked Differentially-Stacked

Rsub,eq↑ Q ↑

)(4121

21eq CCC +=

• fSR ↑, compact layout

• Q degrades

Combination of the two

Suitable for high frequencies

Transmission Lines

Microstrip

• Accuracy• Compatible to mm-wave

devices

• Lower Q• Larger area• Difficult routing

Semi-Circular

Coplaner

Q EnhancementSources of loss: Ohm loss, skin effect, and Eddy current

Geometric Improvements

Physical Improvements• Use high conductivity metals• Ground shields• High-resistance substrate

• Operate differentially• Shunt parallel layers• MEMS

However, for most on-chip inductors, Q < 20.[ Werker, ’04]

Enlarging the Tuning RangeCapacitor Array

Switching Inductors Auxiliary Inductors

(Most popular approach)

Design PitfallsCapacitive Degeneration

Negative resistance gets weakened, making oscillation more difficult!

Em1,2eq

12sCg

R −−=

OscillationCriteria: P

2d

m1,21

RQg +

≥For Qd = 3, we need 10x larger gm!

)12(

1

2d

2d

EP

osc

QQCCL +⋅−

=ω

ω=

E

m1,2d 2C

gQ

Colpitts Oscillators

421

221

Pm ≥+

≥CCCCRg )(

Simplest structure with only 1 active device.

)11(121

osc CCL+≈ω

Potential for high frequency.Challenging for CMOS due to lower gm.May need design assistance from mm-wave technique.

Slightly higher threshold for oscillation. Edwin H. Colpitts(1872-1949)

Realization of Colpitts OscillatorsCommon-Drain

High speed operation

Common-Source Common-Gate

Common-drain is the most popular topology.

Intrinsic C1 (CGS)Varactor M2 as C2

x L floating at both ends

x CGS degrades oscillation freq. or tuning range

x Tail-current parasitics

Actual Implementation of a Colpitts Oscillator

RL converts the current into voltage (Peaking or inductive load is applicable)Regular MOS varactor could be usedλ/4-line converts impedance (Not necessarily λ/4; it depends on CP)

Differential operation suppresses supply coupling.

Overall, Colpitts oscillator is mature and suitable for high speed, e.g., [Heydari, ’07]

Applications of Colpitts TopologyClapp Oscillator

• More stable• Less tuning range

• Extensively used as a reference clock

• Piezoelectric crystal replaces the inductor

Pierce Oscillator

)111(1210

OSC CCCL++=ω

SOSC

1LC

≈ω

Push-Push OscillatorsPrinciple: generating 2nd-order harmonic

Advantages• Double frequency• Low power

• Any point along the central line contains 2nd-order harmonic.

• Need mm-wave technique to extract it .

Disadvantages

• Higher phase noise• Single-ended output

Central Line

Practical Push-Push OscillatorsCross-Coupled Colpitts

[Huang, ’07]

Impedance matching is difficult to maintain over frequency tuning.

mm-Wave OscillatorsMatching networks with highly unstable device

Choosing ΓT:

mm-Wave OscillatorsMatching networks with highly unstable device

• Difficult to tune the frequency • Single-ended operation

Realization Example:

Black Box

Distributed Oscillators

Difficulties:00

osc 21

CLf

l=

• Group velocity deviation• Large area, high power

• Frequency tuning• Non-uniform swings

• Hard to make it differential • Terrible routing

Wave propagates and circulates along the loop.

Barkhausen Criteria still hold.

Traveling time determines the oscillation frequency.

Frequency Tuning of Distributed Oscillators

Degrade fosc and Q

Possible Approaches:Adding Varactors Varying Bias Point Placing “Short-Cut”

Imbalance swingsAggravate mismatchesDeteriorate oscillation Damage the wave

propagation

Distributed oscillators bear intrinsic difficulties.

Modifications of Distributed Oscillators

[Rogers, ’02][Savoj, ’01]

CK0

CK45

CK90

CK135

Resistors dissipate energy in each cycle. from tank resonance.

o45Oscillating at away

Modifications of Distributed Oscillators

[Lee, ’03]

3λ/4 Resonator

M1 M2 M3 M4

⎟⎠⎞

⎜⎝⎛

LW

0.18

102. 10

6. 30

40..

Simulated VCO Waveforms

B'V

BV

AV

A'V

Impedance Transformation of 3λ/4 Line

Equivalent Circuit:

[JSSC ’08]

Supply-Rejection Biasing

DDDD VI

VI

∂∂

=∂∂ CSS

Same Slope

Complete VCO Design

Probing Higher Frequencies

410-GHz Osc. in 45nm 324-GHz Osc. in 90nm

• Typical push-push structure • XORed and rectified (x4)• Low output power• Low output power

[Huang, ’08]

[Seok, ’08]

Frequency Dividers and Arrangement

Usually we apply injection-locked, Miller, and static dividers in descendent order of frequency.

Static Dividers

Flipflop Topologies

CML Divider

TSPC Divider

CML

TSPC

Regenerative (Miller) Dividers

Estimation of lock range:

Self-resonance frequency may not exist.

cminin,

cmaxin,

23

and2

ω≥ω

ω≤ω

cinc 2

32

ω≤ω≤ω

Minimum Required

Input

Insights of Regenerative Dividers

y(t) decays!

tyAydtdyCR in11 cosωβ=+

1st-order RC model

⎟⎟⎠

⎞⎜⎜⎝

⎛+−= ω

ωβ tCR

ACRtyty in

in1111

sin exp (0))(

RC + delay model

• Proper delay is required (e.g., emitter follower)

• Difficult for CMOS ΔT

Regenerative Divider with Bandpass Filter

Absorb parasitic cap. Require no delay element!

β≥

ωω

ξ

⎟⎟⎠

⎞⎜⎜⎝

⎛ωω

−+

β≥

241

12

2

2n

2in2

2n

2in

A2

n

12⎟⎟⎠

⎞⎜⎜⎝

⎛ωωΔ

+β

≥QA

Need to suppress the 3rd-order harmonic by at least 10.8 dB ([Lee, ’04]).

For regular case,

1)2

(2

in ≥ωβ jHA

Configurations of Miller Dividers with BPFType I Type II

Injection-Locked Dividers

Reversed operation of push-push oscillators.

osc

inj

0

21II

Q⋅

π⋅=

ωωΔ

Quite narrow lock range at high frequencies.

[Adler ’1973][Razavi ’2004]

[Kurokawa ’1968]

Enhanced Locking TechniquesShunt Peaking Direct Injection

[Wu, ’01]

[Tiebout, ’04]• Resonating out CP

• Pseudo differential operation• Extendable to differential

operation (e.g., [Lee, ’03])

Higher-Order Injection Lockings

Divide-by-3• Injected into common-

source point

• Nonlinearity of M3

Divide-by-4

• Even narrower lock range

• Vulnerable to PVT

Relationships among the Three TopologiesRedrawn of Type-II Miller Divider

Static Divider with Inductive Loads

De-Qed inj. lockeddiv. (fSR may exist)

Merging 2 latches

creating quadrature signalsTwo coupled inj. locked divs.

Ultimate Version of Degeneration!

Injection-LockedDividers

If We Keep Increasing the Frequency…

Conclusion

CMOS Device proves competent for broadband circuits operation at 20+ Gb/s.

Amplifiers utilizing various high-speed techniques increase the gain-bandwidth product substantially.

Oscillators explore the speed boundaries; some topologies even achieve frequencies beyond fT.

Frequency dividers gradually get matured, covering almost all the bands of interest.

System-level designs with higher integration are expectable in the near future.