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Ver. 1.0 November 2010 www.ntlab.com
GUIDELINES FOR USE
SMIC 0.18 micron, 1.8 V high-density synchronous single port SRAM IP blocks compiler
Guidelines for use IP blocks compiler
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CONTENT
1. DESCRIPTION OF THE COMPILER .......................................................... 3
1.1 GENERAL CHARACTERISTICS OF IP COMPILER ............................... 3
1.2 DESCRIPTION OF OPERATION CONDITIONS...................................... 3
1.3 FEATURES OF SRAM ............................................................................. 4
1.4 DESCRIPTION OF INPUT/OUTPUT SIGNALS ....................................... 4
1.5 DESCRIPTION OF INPUT PARAMETERS .............................................. 5
1.6 DESCRIPTION OF OUTPUT FILES ......................................................... 6
1.7 MEMORY ARCHITECTURE ................................................................... 7
2. TIMING AND POWER SPECIFICATIONS ................................................. 8
2.1 DATA WRITE MODE .............................................................................. 8
2.2 SINGLE BIT WRITE MODE .................................................................... 9
2.3 DATA READ MODE .............................................................................. 10
2.4 CHIP SELECT MODE ........................................................................... 10
2.5 SPECIFICATION OF TIMING AND POWER......................................... 11
3. USING OF IP COMPILER ......................................................................... 13
3.1 DESCRIPTION AND SYSTEM REQUIREMENTS................................. 13
3.2 USAGE OF CONSOLE INTERFACE...................................................... 13
3.3 USING GRAPHICAL USER INTERFACE .............................................. 15
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1. DESCRIPTION OF THE COMPILER
1.1 GENERAL CHARACTERISTICS OF IP COMPILER
The compiler sram_sp_smic018 generates high-density IP modules of single-port
synchronous random access memory (SRAM), implemented in the 0.18 micron SMIC 1.8V technology. The compiler is able to work in a graphic and a console mode and has the following
characteristics: The minimum size of compiled memory SRAM is equal to 8x2 bits, the maximum –
131072x64 bits (8 Mb). Possible word width: 2 to 64 bits with a step increment of 1 bit. The
word depth is from 8 to 131,072 bits, depending on the width of the multiplexer. Flexibility of architecture is achieved by using multiplexing that allows to change the
aspect ratio of IP modules in a wide range. It supports five levels of multiplexing: mux4, mux8, mux16, mux32, mux64.
SRAM has four control signals: user-defined an non inverting or inverting clock
CE/CEB, active at low level signals: an output enable (OEB), a chip select (CSB), a write enable (WEB). In addition, optional control signal select bit write (WENB [n]). Input and output data
have separate data inputs (I [n]) and outputs (O [n]). Memory is synchronous, has possibility of synchronization by rise/fall edge of clock
CE/CEB at a low level signal CSB.
The output buffer is implemented in two versions: 3-states outputs and a stable zero (hard “0”) output circuit, a buffer is activated by low level of signal OEB.
Memory use 6-transistor cell with static control. Cell area is 4.9728 um2. Topology of the SRAM memory is made using four levels of metallization.
1.2 DESCRIPTION OF OPERATION CONDITIONS
The table 1.1 presents information which describes the operating conditions of SRAM.
Table 1.1: Operating conditions of SRAM
Mode Voltage (V) Temperature (С) Process
The best (BC)
1.95 -40 ff
Nominal (NOM)
1.8 25 tt
The worst (WC)
1.65 125 ss
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1.3 FEATURES OF SRAM
Sizes:
words depth: 8…131072; words width: 2/4…64 (increment – 1 bit).
Control signals: rise/edge of clock CE/CEB; output enable (OEB), active – low level;
chip select (CSB), active – low level; write enable (WEB), active – low level;
write enable bit (WENB[n]), active – low level. Writing data: whole word (WEB) or by individual bits (WENB [n]). Data buses: two separate buses (I [n], O [n]) for the input and output data.
Output buffer: a choice of power of output buffer for the different load (2х, 4х, 8х);
a choice of buffer design - a circuit with three states, a circuit with a stable zero.
Four levels of metallization.
Optimizing of area and perimeter of memory modules by using multiplexing. Low power consumption in a static mode.
Low power consumption in a dynamic mode. High-density of memory modules.
1.4 DESCRIPTION OF INPUT/OUTPUT SIGNALS
The table 1.2 describes the input/output signals of the SRAM.
Table 1.2: Description of SRAM signals
The compiler can change the names of the signals with user’s preferences.
Signal Description
vdd! Power bus
gnd! Ground bus
I[n] n-th input
O[n] n-th output
A[n] n-th address line
CSB Chip select, active low level
CE/CEB Clock, active rising/falling edge
OEB Output enable, active low level
WEB Write enable, active low level
WENB[n] n-th local write enable, low level
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1.5 DESCRIPTION OF INPUT PARAMETERS
Information about the input parameters of IP compiler and their detailed description given in
table 1.3.
Table 1.3: Input parameters of compiler
Parameter Range
Number of Words
mux4 8 – 8192, increment = mux×2
mux8 16 – 16384, increment = mux×2
mux16 32 – 32768, increment = mux×2
mux32 64 – 65536, increment = mux×2
mux64 128 – 131072, increment = mux×2
Number of Bits
mux4 2 – 64, increment = 1 bit
mux8 4 – 64, increment = 1 bit
mux16 4 – 64, increment = 1 bit
mux32 4 – 64, increment = 1 bit
mux64 4 – 64, increment = 1 bit
Frequency
from 1 to 1/tcyc, increment = 1 MHz
Clock Polarity
Rise/Fall
Mux Width
4, 8, 16, 32, 64
Select Bit Write
True/False
Output Drive
2х/4х/8х for Tristate out
2х/4х for Hard Zero and mux4, mux8
2х/4х/8х for Hard Zero and mux16, mux32, mux64
Output Circuit Tristate/Hard Zero
Number of Words
Sets the number of words per single output of the SRAM. The range of possible values and its increment depends on the choice of multiplexing and can take values mux×2 words.
Number of Bits Sets the number of bits in a word. The range of possible values ranging from 4 (2 for
mux4) to 64 bits with an increment of 1 bit.
Frequency This parameter sets the clock frequency to calculate the parameters of power
consumption in the generation of specifications for the IP module of SRAM. The frequency can range from 1 to 1/tcyc MHz with increments of 1 MHz. (tcyc - the minimum of period of the clock for the compiled block).
Clock Polarity Determines the active edge of the clock of SRAM. Synchronization can be done on the
rising or falling edge of clock CE/CEB respectively. The parameter is able to possess the value rise/fall.
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Mux Width Parameter sets the capacity of bit multiplexer to select the optimum ratio of size, power
and time responses of the compiled modules. There are possible five versions of multiplexing: mux4, mux8, mux16, mux32, mux64.
Select Bit Write
This parameter allows to recording a specific number of bits in a word. If this parameter is true, then each bit is complemented by the write enable signal WENB [n]. In combination with
the global WEB signal it enables writing of the particular bit. If the value is false, data is written to the entire length of the word.
Output Drive
Used to select the output drive buffer of the SRAM. There are three possible values: 2X, 4X, 8X.
Output Circuit The choice of the output buffer circuit that is implemented in two versions: a scheme with
three states at the output (Tristate) and the scheme with a stable zero (Hard Zero).
1.6 DESCRIPTION OF OUTPUT FILES
The list of synthesized by IP compiler back-end and front-end views (files) for using at
various stages of the design is shown in table 1.4.
Table 1.4: Description of output files of IP compiler
File description Format
Electrical circuit (CDL netlist) *.net
Layout information (GDSII) *.gds
RTL models (Verilog, VHDL) *.v, *.vhdl
Models for Synopsys *.lib
File for the automation placement and routing *.lef
Specification of IP Module *.html
Script for creation symbol, abstract views in Cadence *.il
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1.7 MEMORY ARCHITECTURE
Block diagram of SRAM memory with random address access and architecture of 2D-M
(2 Dimensional Modified), generated by the IP compiler, is shown in figure 1.1. It presupposes the usage of two coordinate buses to select the cell from the memory array and one output data
bus.
Figure 1.1 – SRAM architecture
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2. TIMING AND POWER SPECIFICATIONS
2.1 DATA WRITE MODE
Figure 2.1 shows the timing diagrams explaining the mode of writing information in the SRAM.
Figure 2.1 – Data write cycle
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2.2 SINGLE BIT WRITE MODE
Figure 2.2 shows the timing diagram for writing information in SRAM with option of
writing a separate n-th bit by the WENB signal.
Figure 2.2 – Single bit writing cycle
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2.3 DATA READ MODE
In a data reading mode outputs are activated at the end of the access time (tACC) after the
active edge of CE/CEB (rise/fall) and latched until the next read cycle (figure 2.3).
Figure 2.3 – Data reading mode
2.4 CHIP SELECT MODE
Memory has the ability to go into standby mode with low-power which is controlled by a
signal CSB. Low level signal CSB is active (figure 2.4).
Figure 2.4 – Chip select mode
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2.5 SPECIFICATION OF TIMING AND POWER
Timing data of compiled IP-blocks of SRAM are presented in table 2.1, the parameters of
energy consumption are presented in table 2.2.
Table 2.1: Timing data of SRAM Parameter Designation Note
Clock cycle time
tCYC Min
Access time
tACC Maxa
Minimum clock high time
tHCEB Min
Minimum clock low time
tLCEB Min
Address setup time
tAS Min
Address hold time
tAH Min
Write Enable setup time
tWS Min
Write Enable hold time
tWH Max
Data input setup time
tIS Min
Data input hold time
tIH Min
Chip select setup time
tCS Min
Chip select hold time
tCH Max
Select bit write setup time
tWENBS Min
Select bit write hold time
tWENBH Max
Output Disable time: OEB rising
tLOE Min
Output Enable time: OEB falling
tHOE Maxa
а. Parameter depends on the output load and the duration of the front clock.
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Table 2.2: Parameters of power SRAM Parameter Symbol Unit Note
Consumption in the write mode
PWRITE uW/MHz Nominal parameters
Consumption in the read mode
PREAD uW/MHz Nominal parameters
Consumption in the standby mode
PSTAND uW/MHz Nominal parameters
Leakage current ILEAK uА Nominal parameters Peak current IPEAK mА In the read mode, without external
load
Modes of measurement of parameters (without external load, the rise time of clock is 0.1 ns):
PWRITE (worst case) - power consumption in the write mode. One full clock cycle, all
addresses are switched (one front); all inputs are switched (one front); WEB is switched (two front); the worst value while recording of the values of "1" and "0"; CSB = 0; WEB = 0;
OEB = 0. PREAD (worst case) - power consumption in read mode. One full clock cycle; all addresses
are switched (one front); all inputs are unchanged; the worst value in reading the values of "1"
and "0"; CSB = 0; WEB = 1; OEB = 0. PSTAND – power consumption in standby mode when the crystal is not selected. One full
clock cycle; all addresses are switched (one front); all inputs are switched (one front); WEB switches (2 front); the average consumption during read/write for inactive values of "1" and "0"; CSB = 1; WEB = 1/0; OEB = 0.
ILEAK – leakage current. All signals are unchanged; CEB = 0; CSB = 1; WEB = 0; OEB = 0).
IPEAK – peak current in read mode without an external load.
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3. USING OF IP COMPILER
3.1 DESCRIPTION AND SYSTEM REQUIREMENTS
This version of the IP compiler steadily working on the following operating systems: - Linux SuSE 10.0/RedHat 3/Centos 4.7 and above.
- Windows Xp/Vista The compiler is able to work in a graphic and a console mode. In a graphic mode it is
possible to import/export parameters of compilation from/to a specification file. Console mode does not support additional options of graphical interface but they can be imported from a specification file.
3.2 USAGE OF CONSOLE INTERFACE
The user has the ability to run SRAM compiler in the console mode from the command
line. To do this, it is necessary to create an input file *.spec (format is shown below) in any text editor and specify the file path. There is also a possibility to set the input parameters as run
parameters of the compiler. Enter the following commands to run compiler directly from the console: [user@hostname]$ sram_sp_smic18 [- file <file_path>] [run options]
The following options for the command line are available:
-version
-help
-file <string>
-outdir <string>
-block <string>
-words [8…131072]
-bits [2…64]
-freq [1…1/tCYC]
-clock [rise/fall]
-mux [4/8/16/32/64]
-sbw [true/false]
-drive [2x/4x/8x]
-output [tristate/zero]
-overpoise [left/right]
A detailed description of the options is shown in table 2.3.
Example:
[user@hostname]$ sram_sp_smic18 -outdir /home/user/ram -block
sram64x4 -words 64 -bits 4 –mux 4 -outdir 2x
This command will compile SRAM memory with the name sram64x4 and parameters: 64
words, 4 bits, 4-bit multiplexer, buffer 2x, synchronization by rising edge. If any parameter is not specified, it uses its default value (table 2.3).
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Structure of input file *.spec interface sp
outdir /home/user/work/
ip_name rars64x8m16sbw_x2_tri
words 64
bits 8
frequency 1
clock rise
mux 16
sbw true
drive 2x
output tristate
corner_proc best
corner_volt 1.95
corner_temp 0.00
corner_name ff_1.95_0
cust_comment
left_delim [
right_delim ]
pwr_rename vdd!
gnd_rename gnd!
adr_rename A
in_rename I
out_rename O
wenb_rename WENB
clock_rename CE
oeb_rename OEB
web_rename WEB
csb_rename CSB
name_case upper
odd_bus left
netlist yes
gds yes
verilog yes
vhdl yes
synopsys yes
lef yes
skill yes
html yes
log yes
An example of a console run with the specification file: [user@hostname]$ sram_sp_smic18 -file /home/user/sram.spec
This command will compile SRAM memory to the directory /home/user/work.
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3.3 USING GRAPHICAL USER INTERFACE
Developers offer a user- friendly graphical interface (GUI - Graphical User Interface), to
work with sram_sp_smic18 compiler (figure 3.1).
Figure 3.1 – Graphical interface of compiler sram_sp_smic18
GUI is separated into three blocks: 1. Block of parameters of IP memory module (GENERATION PARAMETERS) - allows
the user to easily and conveniently set the necessary parameters of SRAM for subsequent
compilation. 2. The database with the parameters (DATABASE PARAMETERS) - displays the
physical characteristics (height, width, area, aspect ratio of IP-block), the timing parameters and power consumption for the boundary conditions and user preferences.
3. Panel to display the current operations.
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Table 3.1: Description of parameters of sram_sp_smic18 compiler Parameter in
the console
Parameter in
the graphics
mode
Description Default value
-version - Displays information about version of product and developer
-
-help - Displays information about the possible options and compiler’s options
-
-outdir Run Directory Specifies the working directory which compiler is used
-
-block Instance Name
Name of the memory block can contain any alphanumeric characters. It is recommended to use a unique name for memory block to avoid conflict of the same name within a directory
rars256x8m8_x2
-words Number of Words
Determines the number of words 256
-bits Number of Bits Determines the number of bits 8
-freq Frequency This parameter sets the clock frequency to calculate the parameters of energy consumption
1 МHz
-clock Clock Polarity Determines the active edge of the input clock rise
-mux Mux Width Sets capacity of bit multiplexer to select the optimum ratio of the size, power and timing characteristics
8
-sbw Select Bit Write Parameter allows to write a single bit in a word false
-drive Output Drive Used to select the intended load capacity of output buffers
2x
-output Output Circuit hard0
-overpoise Odd Bus Location
left
-file - Generates the SRAM with the parameters from pre-defined file *.spec
-
- Views Calling the file generation menu - - Corners Calling the operating conditions menu (process,
voltage, temperature) to generate a custom library -
- Advanced Calling the advanced compile options menu - - Import Imports values of the input parameters from the
specification file *.spec -
- Export Exports values of input parameters to the specification file *.spec
-
- Default Sets the values of input parameters by default - - Generate Begins to generate output files - - Close Exit from program -