GATE-ALL-AROUND MOSFETS BASED ON …...GATE-ALL-AROUND MOSFETS BASED ON VERTICALLY STACKED...

GATE-ALL-AROUND MOSFETS BASED ON

VERTICALLY STACKED HORIZONTAL NANOWIRES

HANS MERTENS,

IMEC, LEUVEN, BELGIUM

Semicon Europa, TechArena, Advanced Materials Session, 15/11/2017

THIS PRESENTATION: SILICON GATE-ALL-AROUND

SiGe 40 nm

8-nm Si

nanowires

WF metalMetal

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.510

ent (A

NMOSPMOS

LG = 28 nm

ILINILIN

Processing: Device demonstration:

OUTLINE

Introduction: Motivation and scope

Process flow animation by Coventor SEMulator3D

GAA device fabrication: SiGe/Si processing, nanowire

release, ...

GAA CMOS based on dual work function metal gates

Summary

OUTLINE

release, ...

Summary

MOTIVATION

FinFET

Gate-all-

aroundPlanar

Gate-all-around (GAA):

– Optimal electrostatic

control, ultimate CMOS

scaling

Lateral:

– Natural evolution of

FinFETs

Stacking:

– More active volume,

higher drive current Fin

Stack of

lateral

nanowires

Wrapped

by gate

from all sides

Scaling scenario

Illustration of

50% area scaling

per generation*

* Actual pitch scaling per

generation is slowing

MOTIVATION

90; 64

64; 45

45; 32

30; 24

20; 18

10 20 30 40 50 60 70 80 90 100

Contacted Gate Pitch, CGP (nm)

N14/N16

MOTIVATION

Mx = Metal

LE3 = litho/etch times 3

SADP=Self-aligned dual

patterning

SAQP=Self-aligned quadruple

SE=single exposure

90; 64

64; 45

45; 32

30; 24

20; 18

193i Mx LE3 cliff

193i Mx SADP cliff

193i Mx SAQP cliff

EUV SE cliff

10 20 30 40 50 60 70 80 90 100

N14/N16 1st challenge:

Patterning cliffs

must be overcome

New patterning

techniques required

MOTIVATION

90; 64

64; 45

45; 32

30; 24

20; 18

193i Mx LE3 cliff

193i Mx SADP cliff

193i Mx SAQP cliff

EUV SE cliff

10 20 30 40 50 60 70 80 90 100

FinFET electrostatic limit (~40 nm*)

N14/N16

C C C C C C C

CGP LG

*Liebmann et al., VLSI

(2016)

2nd challenge:

Contacted Gate Pitch:

- Gate length

- Spacer width

- Contact width

Sufficiently long to

switch off device

MOTIVATION

90; 64

64; 45

45; 32

30; 24

20; 18

193i Mx LE3 cliff

193i Mx SADP cliff

193i Mx SAQP cliff

EUV SE cliff

10 20 30 40 50 60 70 80 90 100

FinFET electrostatic limit (~40 nm*)GAA

N14/N16

C C C C C C C

CGP LG< ~16nm

2nd challenge:

Contacted Gate Pitch:

- Gate length

- Spacer width

- Contact width

GAA: LG scaling

beyond FinFET

*Liebmann et al., VLSI

(2016)

ITRS 2.0 ROADMAP

Lateral GAA in ITRS roadmap:

Confirmation of industrial relevance

Production forecast: 2019-2021

Assumed target dimensions:

Diameter of 6 nm

Vertical pitch of 18 nm

Source (2016):

http://www.itrs2.net/itrs-reports.html

SCOPE OF THIS WORK

Key features:

Scaled dimensions:

8-nm diameter wires

Stacking of nanowires

CMOS device integration

Restriction:

Stacking limited to 2 nanowires

to limit topography for

downstream processing

OUTLINE

release, ...

Summary

GAA PROCESS FLOW

Starting material: Si wafer

Ground plane formation

SiGe/Si epitaxy

SADP fin patterning

STI fill + fin reveal

Dummy gate patterning

Spacer formation

Embedded S/D epitaxy

ILD0 fill

Dummy gate removal

Nanowire release

Dual WF metal integration

Metal gate fill and CMP

LI1 + LI2 + V0 + BEOL

pMetal

nMetal

W fill

Si S/D

GAA PROCESS FLOW

NMOSPMOS

Alignment to zero

markers (not shown)

B I/IP I/I

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

Si Si0.7Ge0.3

Typical layer

thicknesses: 10nm

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

fin core

resist

SiO2 HM

SiN HM

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

fin core

SiO2 HM

SiN HM

90 nm pitch

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

45 nm pitch

SiN spacers

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

NMOSPMOS

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

SiO2 fill after STI CMP

SiN HM

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

SiGe/Si fins

SiGeSi

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

1.5 gate pitch

0.5 LG 1 LG

Nanowire

during RMG

processing

S/D epi view

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

Nanowire

during RMG

processing

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

S/D epi view

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

SiN spacer

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

SiN spacer

Recessed

SiGe/Si fins

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

SiN spacer

Undoped

Si epi

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

NMOSPMOS

B I/IP I/I

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

S/D Si epi

w/ HDD I/I

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

ILD0 oxide

Dummy gate

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

Dummy gate removed

ILD0 oxide

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

SiGe/Si fins

in gate trenches

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

Lateral

SiGe etch

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

Si nanowires

SiN spacer

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

pMetal:GAA PROCESS FLOW

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

PMOS NMOS

pMetal

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

PMOS NMOS

pMetal

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

PMOS NMOS

pMetal (with nMetal on top)

nMetalW fill

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

nMetal:GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

Nanowires Embedded

S/D epi

Simulated epi volume

is suboptimal

GAA PROCESS FLOW

SiGe/Si epitaxy

SADP fin patterning

Spacer formation

ILD0 fill

Dummy gate removal

Nanowire release

pMetal

nMetal

W fill

Si S/D

OUTLINE

release, ...

Summary

SHALLOW TRENCH ISOLATION (STI) FOR SILICON GAA

SiGe/Si epi: Fin etch: STI:

Restriction on STI densification

~1 nm sharp

SiGe/Si

interfaces

Risk: High thermal budget can lead to

smoothening of the SiGe/Si transitions

Nitride SiGe

SIGE/SI INTERMIXING: DIFFUSION MODEL*

-15 -10 -5 0 5 10 150.0

Depth (nm)

750 °C900 °C

1050 °C

500 600 700 800 900 1000

<~ 1 nm SiGe-Si

interface broadening

for 30-min anneal

Ge% = 20%

Temperature (°C)

STI densification

temperature for

Si FinFET

Low degree of intermixing for 750 °C for Ge% =

Selected for STI densification

Temperature and

Ge% dependence:

SiGe/Si profile simulations

for 30-min anneal:

Ge% = 27%

* D. B. Aubertine and P. C. McIntyre,

J. Appl. Phys. 97, 013531 (2005)

SIGE/SI INTERMIXING: EXPERIMENT

30 min, 900 °C, N2

Annealed

0 20 40 60 80 100 12010

As grown

750 °C

1050 °C

sity (

Depth (nm)

900°CSiGe

HAADF-STEM:

As-grown

Ge% = 27%

SIMS data:

Ge% = 27%

Trends from diffusion model

confirmed by experimental

Thermal budget

restriction

Image contrast Z2

Si0.73Ge0.27

Is this representative for fins ? See next slides

0 20 40 60 80 100 1200.0

Depth (nm)

SIGE/SI INTERMIXING: EXPERIMENT

30 min, 900 °C, N2

Annealed

HAADF-STEM:

As-grown

Ge% = 27%

STEM vs. SIMS:

Ge% = 27%

Line: SIMS

Dots: STEM

intensity

(dots)

Good SIMS-STEM

correspondence

STEM suitable for SiGe/Si intermixing

analysis

Applicable to nanostructures, see next

SIGE/SI INTERMIXING IN FINS

SiGe/Si intermixing by STI thermal

budget comparable for narrow fins

and blanket layers (blue vs. green)

STEM methodology applied to narrow fins:

STEM intensity

(arb. units)

-6 -4 -2 0 2 4 60.0

Depth (nm)

Black: Post epi - Blanket

Green: Post STI - Blanket

Blue: Post STI - Fin

thermal

budget

Post-STI STEM

10 nmSTI dens. at 750 °C Sharp SiGe/Si

NANOWIRE RELEASE

HCl vapor etch in epi reactor*:

Slow Fast

Application to SADP-defined fins:

Si0.7Ge0.340 nm

8-nm Si nanowires

W gate

HCl +rounding

NANOWIRE SIZE TUNING

• Starting material: Si wafer

• Well implantations

• SiGe/Si epitaxy

• SADP fin patterning

• STI fill and recess

• Dummy gate

• Spacer

• Embedded S/D epitaxy

• ILD0 (incl. poly removal)

• Dummy oxide removal

• Si nanowire release

• HK + WF metal deposition

• Metal gate fill and CMP

• LI1 + LI2 + V0 + BEOL

Challenge:

Size and

shape control

top and bottom

nanowires

nanometer

accuracy

Oxidation (top/side)

Fin width and profile

Si layer thicknesses

Oxide etch / clean

Clean / oxidation

SiGe/Si selectivity

Process flow: Influence on nanowire size:

NANOWIRE SIZE TUNING

GAA module

optimization Epi tuning

Fin profile

optimization

Minimization of

SiGe/Si intermixing

SiGe/Si etch

improvement

Si nanowire corner

rounding optimization

GAA module

set-up

GAA DEVICE STRUCTURE

NMOS, LG = 70 nm

metal 8 nm

W gate

Stacked Si nanowires

Narrow size distribution

Conformal HK/MG fill

TEM ALONG NANOWIRES

Thick TEM specimen

Along nanowires:

W fill

W gate covers the nanowires:

W fill

WF metalHfO2

10 nm LG = 70 nm

Metal gate shields the nanowires

TEM ALONG NANOWIRES

Thick TEM specimen

Along nanowires:

LG = 70 nm

W fill

W gate covers the nanowires:

W fill

WF metalHfO2

TEM sample thinning to make W gate transparent See next slide

TEM ALONG NANOWIRES

Thick TEM specimen

Along nanowires:

LG = 70 nm

W fill

Si nanowires visible:

Ultrathin specimen

Well-defined NWs over full gate lengthWF metal

Si NWs

Ultrathin W

9.4 8.7 nm

8.9 nm 9.6 9.4

TEM ALONG NANOWIRES

Top Si NW

SiN spacer

Bottom

Facet attributed to anisotropy of

vapor HCl etch process

Si0.7Ge0.3

W fill Top

Si NW WF

Top Si

LG = 30 nm

WF metal

Bottom Si

Well-defined GAA device structure for LG = 30 nm

KEY DIFFERENCES COMPARED TO FINFET

1. SiGe/Si epitaxy 2. Low-T STI module

3. Embedded Si S/D epitaxy 4. Si nanowire release in RMG

SiGe/Si stack

with ~1 nm

sharp transitions

Si Si0.7Ge0.3

S/D epi

Temperature

reduction of

1050 °C to 750

°C to minimize

SiGe/Si

intermixing

SiGe/Si layer

stack confined

below dummy

SiGe sacrificial

layer removal by

HCl vapor etch

process +

HK/MG dep.

SiGeSi

ID-VGS CHARACTERISTICS

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.510

ent (A

NMOSPMOS

LG = 28 nm

Excellent short-

channel characteristics

GP doping

condition: >1E19

N- and PMOS on separate

wafers

0.01 0.1 10

Gate length, LG (m)

-1.0 -0.5 0.0 0.510

SUBTHRESHOLD SLOPE

0.01 0.1 10

Gate length, LG (m)

-0.5 0.0 0.5 1.010

VDD = 0.9V

LG = 24nm

GAA High GP

VDD = 0.9V

LG = 24nm

GAA High GP

PMOS: NMOS:

Subthreshold slope reduction by high GP

doping

DIBL AND ION – VT,SAT

-0.2 0.0 0.2 0.40

I ON (

VT,SAT

20 25 30 35 400

Gate length, LG (nm)

VDD = 0.9V

LG=24-30nm

GAA, High GP

FF, WFIN =

WFIN=10nmVDD = 50mV, 0.9V

High GP

FF NMOS

High GP

Excellent DIBL for GAA ION – VT,SAT at similar

trend line as FinFET

NMOS:PMOS and NMOS:

* Normalized by

channel perimeter

OUTLINE

release, ...

Summary

DUAL WORK FUNCTION METAL GATES

NMOS PMOS

nMetalpMetal

Previous slides:

NMOS and PMOS devices on

separate wafers

Next slides:

NMOS and PMOS devices on the

same wafer

Dual work function metal gates

for threshold voltage tuning

DUAL WORK FUNCTION METAL INTEGRATION

Dry strip + APM

TiN removed

(stop in TaN)

pMetal + TaN

barrier + sacrificial

TiN dep. + litho

Dry removal of

pMetal from

W-Fill

TiAl 4

mTiN 3

4 TiAl

nMetal

deposition by

resist

O2+ APM

PMOS-first patterning scheme developed for FinFET:

DUAL WORK FUNCTION METAL INTEGRATION

Dry strip + APM

TiN removed

(stop in TaN)

pMetal + TaN

barrier + sacrificial

TiN dep. + litho

Dry removal of

pMetal from

W-Fill

TiAl 4

mTiN 3

4 TiAl

nMetal

deposition by

resist

O2+ APM

PMOS-first patterning scheme developed for FinFET:

Is this patterning

scheme compatible

with 3D GAA

structures ?

FABRICATED DEVICES

Post-WFM-etch

Top-view SEM:

PMOS NMOS

TEM cut

LG = 30nm

LG = 30 nm

PMOS NMOS

PWFM NWFMN/P

boundary

HfO2HfO2

TiAlTiNTa

removed from

NMOS 20 nm

Conformal WFM

deposition

Removal of pMetal

from NMOS

Well-defined N/P

boundary

NMOS VTH SHIFT BY DWFM INTEGRATION

0.0 0.2 0.4 0.6 0.8 1.00

Gate-source voltage, VGS

LG = 28 nm, VDD = 0.9 V

NMOS w/

nMetal

Control:

NMOS w/ pMetal

200-mV shift

nMetal

on NMOS:

Control*:

pMetal

on NMOS

TiNTaN

* TEM for illustrative purposes (pMetal on PMOS)

MATCHING VTH BY DWFM INTEGRATION

-1.0 -0.5 0.0 0.5 1.010

ent, I

ID,LIN

6x2 NWs

LG = 30 nm

50 mV, 0.9 V

|VT,SAT| =

~0.35ID,LIN

ID,SAT

IS,SAT

PMOS NMOSN- and PMOS devices on

the same wafer

MATCHING VTH BY DWFM INTEGRATION

-1.0 -0.5 0.0 0.5 1.010

ent, I

ID,LIN

6x2 NWs

LG = 30 nm

50 mV, 0.9 V

|VT,SAT| =

~0.35ID,LIN

ID,SAT

IS,SAT

PMOS NMOSMinority carriers

generated in nanowires:

BGIDL in ID and IS

Signature of nanowire

conduction

THRESHOLD VOLTAGE VS. GATE LENGTH

0 50 100 150 200 250

Gate length, LG (nm)

Similar VTH as

uni-gate control

devices

Validation of

work function

metal integration

scheme

Uni-gate (control)

Dual-gate (CMOS)

Uni-gate (control)

Dual-gate (CMOS)

OUTLINE

release, ...

Summary

SUMMARY: SCOPE

Natural evolution of

FinFETs:

Improved electrostatics

SUMMARY: SCOPE

FinFETs:

Industry-relevant:

Illustrated by ITRS 2.0

roadmap

SUMMARY: SCOPE

FinFETs:

Industry-relevant:

Illustrated by ITRS 2.0

roadmap

GAA device variants:

Trade-offs:

- Drive current

- Electrostatics

- Parasitics

- Layout

flexibility

SUMMARY: SI GAA DEVICE DEMONSTRATION

GAA Si NWFETs with excellent short-

channel characteristics demonstrated:

1. Stacked NWs

2. Scaled dimensions

3. RMG processing

4. Bulk Si substrates

Major differences with bulk FinFET flow:

STI densification at 750 °C Sharp SiGe/Si transitions

Low-complexity GP doping scheme prior to SiGe/Si epitaxy bottom

parasitic channel suppression

SUMMARY: SI GAA CMOS DEMONSTRATION

767676

LG = 30 nm

PMOS NMOS

pmetal nmetal

boundary

NMOSPMOS

HfO2HfO2

TiAlTiN TaN

Vertically stacked Si nanowire transistors

with dual work function metal gates

demonstrated

-1.0 -0.5 0.0 0.5 1.010

ID,LIN

6x2 NWs

LG = 30 nm

50 mV, 0.9 V

|VT,SAT| =

~0.35 ID,LIN

ID,SAT

IS,SAT

ACKNOWLEDGEMENTS

The GAA team of Imec’s LOGIC DEVICES program

Imec’s (sub-)10nm CMOS partners including, Samsung,

TSMC, GlobalFoundries, Intel, SK-Hynix, Micron,

Qualcomm, Sony, Altera, and Huawei

The European Commission and Regional authorities

for their support of European collaborative projects

Coventor for process simulation software support

GATE-ALL-AROUND MOSFETS BASED ON …...GATE-ALL-AROUND MOSFETS BASED ON VERTICALLY STACKED...

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