Post on 08-Aug-2015
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FreeRTOS Multicore Port for Validation Infrastructure
Raghav Nayak raghav.nayak@freescale.com
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14th IDC Technical Symposium
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Agenda
Problem Analysis
Proposed Solution
Results
Uniqueness
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PROBLEM:
SoC’s becoming increasingly complex
Limitations with Bare-Metal Framework
Better validation strategy to find/reproduce critical silicon issues
Bridge the gap between Bare-Metal and Software Environment
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SOLUTION:
RTOS Based Validation
Which RTOS to choose????
We have decided to go with “FREERTOS”
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WHY FREERTOS?
Very Scalable
Simple and easy to use
Low Memory Footprint
Popular Open-Source embedded real-time operating system
Ported over different hardware architectures and compiler tool-chains
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FREERTOS:
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FREERTOS:
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FREERTOS-MULTICORE:
Extending the support to Multicore Implementing MP Scheduler
Hardware design
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FREERTOS-MULTICORE:
Memory model
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FREERTOS-IMPLEMENTATION:
Core-Ignition:
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FREERTOS-IMPLEMENTATION:
Task Creation:
Single-Core:
Multi-Core:
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FREERTOS-IMPLEMENTATION:
Scheduler -> Task Control Block (TCB) :
Single-Core--->
Multi-Core---->
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FREERTOS-IMPLEMENTATION:
Port-Layer (Context Save/Restore)
Synchronization
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FREERTOS-RUN:
LS1 Platform with debug from ARM DS-5
LS2 Fast Model with debug from GDB
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FREERTOS-SUPPORT:
Preemptive and Co-operative Scheduling
Core-Subsystem (ARM Cortex A7, A57, A53)
Memory Management (Short descriptor and LPAE)
Interrupt Management (GIC400, GIC500)
Drivers ( I2C, UART, DMA )
Logging ( Console, Trace )
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FREERTOS-PLATFORM:
Python (Host-Interface) FreeRTOS (Target-Interface)
Multi-Processing and Multi-Tasking
Provide path to run directed and complex system synario’s
Multiple-Masters/Cores getting services to validate/stress-out better
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UNIQUENESS:
“Memory footprint” <400KB and “Boot-time” is <1min with full-system on emulator
Scalable enough to find “early” critical silicon bugs in Pre-Silicon phase
Easy to “reproduce” issues reported by software team in Post-Silicon phase
Helps to “bridge the gap” between Bare-Metal and Software
Platform is “generic” across different hardware architectures and applications
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Thinking Ahead
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UNIQUENESS:
Scalable enough to find “early” critical silicon bugs in Pre-Silicon phase
Easy to “reproduce” issues reported by software team in Post-Silicon phase
Helps to “bridge the gap” between Bare-Metal and Software
Platform is “generic” across different hardware architectures and applications
Questions and Answers
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