Post on 30-Dec-2015
FPGA Implementation of Linear Model Predictive Controller for Closed Loop
Control of Intravenous Anesthesia
Guide:-Prof. D. N. Sonawane
By:-Prashant Basargi(121117003)
Objectives• Understanding Linear MPC and QP problem• Active-set method• Hardware/Software Co-Simulation• Testing of developed MPC architecture for closed loop
control of intravenous anesthesia • Simulation of various clinical trials
Model Predictive Control:
Block Diagram MPC strategy
Types of Model Predictive Control:
Tuning parameters of MPC:
1. Sample time2. Prediction horizon3. Control horizon
Methods to solve QP problems :
1.Active set method
2.Interior point method
3.Gradient Projection method
Why Active Set ?
• Best suitable for less numbers of variables• Gives more exact solutions and sensitivity
information for less number of variables
• Active set methods are more stable than interior-point methods for less numbers of variables
Hildreth Algorithm:
1. Find initial values of X– Find H-1 matrix– Cholesky decomposition [L and LT] – Inverting triangular matrix [L-1 and (LT)-1] – Multiplication of L-1 and (LT)-1 – Multiplication of H-1, C and -1
2. Find optimum values of λ
P=M x H-1 x MT
– Multiplication of M and H-1 – Multiplication of above calculated matrix and MT
Continued…3. d = (M x H-1 x C) + K
– multiplication of M, H-1 and C – Addition of above calculated matrix and K matrix
4. Using lower triangular matrix of P calculate the values of λ 11, λ 2
1, λ 31.
5. Using matrix P and above calculated values of λ find values of λ 12, λ 2
2, λ 32.
6. Using this optimum value of λ calculate optimum value of X* by,
X* = X - H-1 x MT x λ* – Multiplication of H-1, MT and λ*– Subtract above calculated value from initial value of X.
Cholesky decompositionA = L * L
Algorithm:1. Determine l11 and L21
2. Compute L22 from
Synthesis report:Device Utilization Summary (estimated values) [-]
Logic Utilization Used Available UtilizationNumber of Slice Registers 2023 54576 3%Number of Slice LUTs 7493 27288 27%Number of fully used LUT-FF pairs 1449 8067 17%
Number of bonded IOBs 833 296 281%Number of BUFG/BUFGCTRLs 1 16 6%Number of DSP48A1s 8 58 13%
MATLABExecution time=0.001152sec=1152000 nsec
FPGAClock cycle required=24 Execution time=120 nsec
Hildreth Algorithm: synthesis report
MATLABExecution time=0.826691 sec = 826691 microsec
FPGAClock cycle required=224 Execution time=1.12 microsec
Device Utilization Summary (estimated values) [-]Logic Utilization Used Available UtilizationNumber of Slice Registers 5278 54576 9%Number of Slice LUTs 13425 27288 49%
Number of fully used LUT-FF pairs 4127 14576 28%
Number of bonded IOBs 1217 296 411%Number of BUFG/BUFGCTRLs 1 16 6%Number of DSP48A1s 8 58 13%
Fix to float synthesis report:
Results:Input number Expected output Proposed IP core output
5.34 32’h40AAE148 32’h40AAE148
-11.57 32’hC1391EB8 32’hC1391EB8
0.023 32’h3CBC6A7F 32’h3CBC6A40
Device Utilization Summary (estimated values)Logic Utilization Used Available UtilizationNumber of Slice Registers 11 54576 0%Number of Slice LUTs 480 27288 1%Number of fully used LUT-FF pairs 11 480 2%
Number of bonded IOBs 65 296 21%Number of BUFG/BUFGCTRLs 1 16 6%
Addition/Subtraction Synthesis report:
Results:Input number1 Input number2 Expected output
Addition/subtractionProposed IP core output
Addition/subtraction32’h41280000 32’h40AAE148 32’h417D70A4/
32’h40A51EB832’h417D70A0/32’h40A51EB8
32’h405AE148 32’hC1391EB8 32’hC1026666/32’h416FD70A
32’hC1026666/32’h416FD70A
Device Utilization Summary (estimated values) [-]
Logic Utilization Used Available Utilization
Number of Slice Registers 31 54576 0%
Number of Slice LUTs 573 27288 2%
Number of fully used LUT-FF pairs 31 573 5%
Number of bonded IOBs 97 296 32%
Number of BUFG/BUFGCTRLs 1 16 6%
Multiplication Synthesis report:
Results:
Device Utilization Summary (estimated values)
Logic Utilization Used Available Utilization
Number of Slice LUTs 54 27288 0%
Number of fully used LUT-FF pairs 0 54 0%
Number of bonded IOBs 97 296 32%
Number of BUFG/BUFGCTRLs 1 16 6%
Number of DSP48A1s 4 58 6%
Input number1 Input number2 Expected outputMultiplication
Proposed IP core outputMultiplication
32’h41280000 32’h40AAE148 32’h426047AE 32’h
32’h405AE148 32’hC1391EB8 32’hCC21E4711 32’h
Division Synthesis report:
Results:
Device Utilization Summary (estimated values)Logic Utilization Used Available UtilizationNumber of Slice LUTs 1757 27288 6%
Number of fully used LUT-FF pairs 0 1757 0%
Number of bonded IOBs 97 296 32%
Number of BUFG/BUFGCTRLs 1 16 6%
Input number1
Input number2 Expected outputDivision
Proposed IP core outputDivision
32’h41280000 32’h40AAE148 32’h3FFBAF76 32’h
32’h405AE148 32’hC1391EB8 32’h3E9757D7 32’h
Square root synthesis report:
Results:Input number Expected output
Square rootProposed IP core output
Square root5.34 32’h4013E4DE 32’h4013E4DE
11.57 32’h4059B1B0 32’h4059B1B0
0.023 32’h3E1B4C1B 32’h3E1B4C1B
Device Utilization Summary (estimated values) [-]Logic Utilization Used Available UtilizationNumber of Slice LUTs 900 27288 3%
Number of fully used LUT-FF pairs 0 900 0%
Number of bonded IOBs 64 296 21%Number of BUFG/BUFGCTRLs 1 16 6%
Objective completed:
• Different IP cores :o IEEE 754 Floating Point Number
Converter and Arithmetic unitso Matrix algebrao Cholesky Decompositiono Active set method
Objective to be completed:
• Hardware/Software Co-Simulation• Testing of developed MPC architecture for
closed loop control of intravenous anesthesia.• Simulation of various clinical trials
Literature Survey
• E. Furutani and Y. Sawaguchi, “A hypnosis control system using a model predictive controller with online identification of individual parameters”, Proceedings of the 2005 IEEE Conference on Control Applications Toronto, Canada, August 28-31, 2005,154-159.
• N. Cardoso and J.M. Lemos, “Model Predictive Control of depth of Anesthesia: Guidelines for controller configuration”, 30th annual international IEEE EMBS conference vancouver, british columbia, canada, August 20-24, 2008.
• D. Ingole, D. N. Sonawane, V. Naik, D.Ginoya, V. Patki, “Implementation of Model Predictive Control for Closed Loop Control of Anesthesia”, proceeding of the third International Conference on control, communication and power engineering (CCPE-2012),Bangalore, India: Springer-Verlag,2012, pp.415-421.
Fix to float conversion:
Addition/subtraction :
Multiplication:
Division: