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FPGA Design FPGA Design Techniques ITechniques I
Ruth Markenson:
Version changed
Original slides 11, 14, 23, 24-30 removed
http://www.asicfpga.com
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ObjectivesObjectives
Use hierarchy effectively Increase circuit reliability and performance
by applying synchronous design techniques
After completing this module, you will be able to:
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Hierarchical DesignHierarchical Design
Using Hierarchy leads to greater design readability, re-use,and debug
State MachinesOne-hotBinary
Enumerated
CountersAdders/Subtractors
Bit ShiftersAccumulators
Building BlocksStandard widthsPipeline RAMs
Data PathsPipelining
Muxing/De-muxingArithmetic
CoregenParametizable functions
FIFOsFIR Filters
RAMTechnology Specific Functions
Specific FunctionsLogiblox
RAMOther IP/Cores
Top Level of DesignInfer or instantiate I/O here
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Benefits of Using HierarchyBenefits of Using Hierarchy
Use the best design entry method for each type of logic
Design readability—Easier to understand design functionality and data flow—Easier to debug
Easy to reuse parts of a design Synthesis tool benefits
—Covered in a later section
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Design Entry MethodsDesign Entry Methods
Use HDL for:—State machines—Control logic—Bused functions
Use schematics for:—Top-level design—Manually optimized logic
“Mixed mode” designs can utilize the best of both worlds—However, they are less portable than an all-HDL design
Ruth Markenson:
3rd bullet changed
3rd bullet, sub-bullet added
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Design Readability TipsDesign Readability Tips
Choose hierarchical blocks that have:—Minimum of routing between blocks—Logical data flow between blocks
Choose descriptive labels for blocks and signals Keep clock domains separated
—Makes the interaction between clocks very clear Keep the length of each source file manageable
—Easier to read, synthesize, and debug
Ruth Markenson:
4th bullet changed
Notes, 1st paragraph, bold text changed
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Design Reuse TipsDesign Reuse Tips
Build a set of blocks that are available to all designers —Register banks—FIFOs—Other standard functions—Custom functions commonly used in your applications
Name blocks by function and target Xilinx family—Easy to locate the block you want—Example: REG_4X8_SP (bank of four eight-bit registers
targeting Spartan) Store in a separate directory from the Xilinx tools
—Prevents accidental deletion when updating tools
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Why Synchronous Design?Why Synchronous Design?
Synchronous circuits are more reliable—Events are triggered by clock edges that occur at
well-defined intervals—Outputs from one logic stage have a full clock cycle
to propagate to the next stage– Skew between data arrival times is tolerated within the
same clock period Asynchronous circuits are less reliable
—Delay may need to be a specific amount (for example, 12 ns)
—Multiple delays may need to hold a specific relationship (For example, DATA arrives 5-ns before SELECT)
Ruth Markenson:
Originally slide 12
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Asynchronous Design:Asynchronous Design:Case StudiesCase Studies
The design I did two years ago no longer works. What did Xilinx change in their FPGAs?—SRAM process improvements and geometry shrinks
increase speed—Normal variations between wafer lots
My design passes a timing simulation test but fails in circuit. Is the timing simulation accurate? YES—Timing simulation uses worst-case delays—Actual board-level conditions are usually better
Ruth Markenson:
Originally slide 13
2nd bullet and it’s sub-bullet deleted
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Clock SkewClock Skew
This shift register will not work because of clock skew!
Expected operation
Clock
Q_A
Q_B
Q_C
3 cycles
Clock skewed version
A & C Clock
Q_A
Q_B
Q_C
B Clock
2 cycles
D Q_B Q_CINPUT
CLOCK
DD Q_A3.1
3.0
3.1 3.3
12.5 3.0A B C
Ruth Markenson:
Originally slide 15
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Use Global Buffers toUse Global Buffers to Reduce Clock Skew Reduce Clock Skew
Global buffers are connected to dedicated routing—This routing network is balanced to minimize skew
All Xilinx FPGAs have global buffers—Virtex-II devices have sixteen BUFGMUXes—Virtex and Spartan-II have four BUFGs
You can always use a BUFG symbol, and the software will choose an appropriate buffer type—All major synthesis tools can infer global buffers onto
clock signals that come from off-chip
Ruth Markenson:
Originally slide 16
2nd bullet, all sub-bullets changed
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Traditional Clock DividerTraditional Clock Divider
Introduces clock skew between CLK1 and CLK2 Uses an extra BUFG to reduce skew on CLK2
D QCLK2
CLK1 BUFG
D Q
BUFG
Ruth Markenson:
Originally slide 17
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Recommended Clock DividerRecommended Clock Divider
No clock skew between flip-flops
D QCLK2_CE
CLK1
D
CE
Q
BUFG
Ruth Markenson:
Originally slide 18
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Avoid Clock GlitchesAvoid Clock Glitches
Because flip-flops in today’s FPGAs are very fast, they can respond to very narrow clock pulses
Never source a clock signal from combinatorial logic—Also known as “gating the clock”
Shorter routing
Glitch may occur here
MSB
BinaryCounter
0111 1000 transition can become0111 1111 1000 due to faster MSB
MSB
FFLSB
Ruth Markenson:
Originally slide 19
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Avoid Clock GlitchesAvoid Clock Glitches
This circuit creates the same function, but without glitches on the clock
D Q3INPUT
CLOCK
Counter
Q2Q1
Q0
CE Q
D
FF
Ruth Markenson:
Originally slide 20
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Avoid Set/Reset Glitches Avoid Set/Reset Glitches
Glitches on asynchronous Set/Reset inputs can lead to incorrect circuit behavior
CLOCK
Q[x]
BinaryCounter
Q[0]
INPUT
RESET
Q
FF
D
CLR
Asynchronous Reset
Ruth Markenson:
Originally slide 21
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Avoid Set/Reset GlitchesAvoid Set/Reset Glitches
CLOCK
Q[x]
Counter
Q[0]
Convert to synchronous set/reset when possible
RESET
INPUT Q
FF
D
R
Synchronous Reset
Ruth Markenson:
Originally slide 22
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Review QuestionsReview Questions
List three benefits of hierarchical design
Why should you use global buffers for your clock signals?
Ruth Markenson:
Originally slide 33
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AnswersAnswers
List three benefits of hierarchical design—Allows you to use different design entry methods—Design readability—Design reuse
Why should you use global buffers for your clock signals?—To reduce clock skew
Ruth Markenson:
Originally slide 24
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SummarySummary
Proper use of hierarchy aids design readability and debug
Synchronous designs are more reliable than asynchronous designs
FPGA design tips—Global clock buffers and DLLs eliminate skew—Avoid glitches on clocks and asynchronous set/resets
Ruth Markenson:
Originally slide 25
3rd bullet, last 2 sub-bullets deleted
(change to last 3 if FSM removed)
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Where Can I Learn More?Where Can I Learn More?
Application notes on http://support.xilinx.com—Under the Design tab, click App Notes
Software documentation—Development System Reference Guide, Chapter 2 “Design
Flow,” FPGA Design Techniques section—Libraries Guide—Documentation for your synthesis tool
Ruth Markenson:
Originally slide 36
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FPGA Design FPGA Design Techniques IITechniques II
Version 4Version 4
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ObjectivesObjectives
Increase design performance by duplicating flip-flops Increase design performance by adding pipeline stages Increase board performance by using I/O flip-flops Build reliable synchronization circuits
After completing this module, you will be able to:
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D Qfn1
D Qfn1
D Qfn1
Duplicating Flip-FlopsDuplicating Flip-Flops
High-fanout nets can be slow and hard to route
Duplicating flip-flops can fix both problems— Reduced fanout shortens
net delays— Each flip-flop can fanout to
a different physical region of the chip to help with routing
Design tradeoffs— Gain routability
and performance— Design area increases
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Which Flip-Flops Which Flip-Flops Should I Duplicate? Should I Duplicate?
Duplicate flip-flops that source:—Address and control lines to large memory arrays—Clock enables or output enables —Synchronous reset signals
Do not duplicate flip-flops that are sourced by asynchronous signals—Synchronize the signal first—Feed synchronized signal to multiple flip-flops
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Tips on Duplicating Flip-FlopsTips on Duplicating Flip-Flops
Name duplicated flip-flops _a, _b NOT _1, _2—Numbered flip-flops are mapped by default into the same
CLB—You want duplicated flip-flops to be separated
– Especially if the loads are spread across the chip Synthesis tips
—Most synthesis tools have fanout-control features– However, they do not always pick the best implementation
—Xilinx recommends explicitly creating duplicate flip-flops in HDL code
—Many synthesis tools will optimize out duplicated flip-flops– Tell your synthesis tool to keep redundant logic
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Duplicating Flip-Flops ExampleDuplicating Flip-Flops Example
The source flip-flop drives two register banks that are constrained to different regions of the chip
The source flip-flop and pad are not constrained
PERIOD = 5 ns timing constraint
Implemented with default options
Longest path = 6.806 ns — Fails to meet timing
constraint
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Duplicating Flip-Flops ExampleDuplicating Flip-Flops Example
The source flip-flop has been duplicated
Each flip-flop drives a region of the chip—Each flip-flop can be
placed closer to the register that it is driving
—Shorter routing delays Longest path =
4.666 ns —Meets timing
constraint
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Pipelining ConceptPipelining Concept
D QfMAX = nMHz
fMAX = 2nMHz
two logic levels
one level
one level
D Q
D Q D Q D Q
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PipeliningPipelining
Inserting flip-flops into a datapath is called pipelining Pipelining increases circuit performance by reducing
the number of logic levels between flip-flops—Fewer logic levels = shorter delays between flip-flops =
faster clock speeds Xilinx FPGA architectures support pipelining
—Many flip-flops are available—Slice structure is a Look-Up Table (Logic Level) followed
by a flip-flop
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Pipelining ConsiderationsPipelining Considerations
Are there enough flip-flops available?—Refer to the Map Report—You generally will not run out of FFS
Are there multiple logic levels between flip-flops?— If there is only one logic level between flip-flops, pipelining
will not improve performance– Exception: Long carry-logic chains can benefit from pipelining
—Refer to the Post-Map Static Timing Report or Post-Place & Route Static Timing Report
Can the system tolerate latency?
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Latency in PipelinesLatency in Pipelines Each pipeline
stage adds one clock cycle of delay before the first output will be available— Also called
“filling the pipeline”
After the pipeline is filled, a new output is available every clock cycle
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Original circuit—Two logic levels between SOURCE_FFS and DEST_FF— fMAX = ~137 MHz
Pipelining ExamplePipelining Example
Q
DEST_FF
LUT
D Q
DLUTLUT
LUT
SOURCE_FFS
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Pipelined circuit—One logic level between each set of flip-flops— fMAX = ~228 MHz
Pipelining ExamplePipelining Example
LUT
D Q
D QLUT
DEST_FF
LUT
LUT
SOURCE_FFS
D Q
D Q
D Q
PIPE_FFS
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Given the original circuit, what is wrong with the pipelined circuit?
How can the problem be corrected?
Pipelining QuestionsPipelining Questions
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What is wrong with the pipelined circuit?— Latency mismatch— Older data is mixed with
newer data— Circuit output is incorrect
How can the problem be corrected?— Add a flip-flop on
SELECT— All data inputs now
experience the same amount of latency
Pipelining AnswersPipelining Answers
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I/O Flip-Flop OverviewI/O Flip-Flop Overview
Each Virtex-II I/O Block contains six flip-flops— For single data rate:
– IFD on the input– OFD on the output– ENBFF on the three-state enable (not shown)
D
CE
Q
Q
CE
D
I/O pad
OFD
IFD
Clock
Clock
Input clock enable
Data from FPGA
Data to FPGA
Output clock enable
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Benefits of Using I/O Flip-FlopsBenefits of Using I/O Flip-Flops
Guaranteed setup, hold, and clock-to-out times— When the clock signal comes from a BUFG
Programmable delay on input flip-flop Programmable slew rate on output flip-flop
D
CE
Q
Q
CE
D
I/O pad
OFD
IFD
Clock
Clock
Input clock enable
Data from FPGA
Data to FPGA
Output clock enable
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Programmable Input DelayProgrammable Input Delay
Delay is added to the D input of the IFD or ILD— Guarantees 0-ns hold time when using a global buffer— Trades an increase in setup time for a decrease in hold time
Delay is controlled by attributes— NONE is the default, if the clk input of the IFD/ILD is driven by a DCM clk output— IFD is the default, if the clk input of the IFD/ILD is not driven by a DCM clk output
BUFG
IFD
DCE
QDelay
NONE
IFD
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Programmable Input Programmable Input Delay Example Delay Example
XC2V250-5 (taken from timing analysis report with v1.90 Virtex-II speed files) — Clk = DCM output (default is NONE)
– IFD Delay tSU = 4.0ns tH = 0.0ns– NONE tSU = 1.3ns tH = 0.0ns
— Clk = NOT a DCM output (default is IFD Delay)– IFD Delay tSU = 1.2ns tH = 0.0ns– NONE tSU = -1.5ns tH = 1.7ns
BUFG
IFD
DCE
QDelay
NONE
IFD
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Programmable Output Slew RateProgrammable Output Slew Rate
Slew rate can be SLOW or FAST—By default the slew rate is SLOW—Virtex/E/II/Pro: Only the LVTTL I/O standard supports
programmable slew rate Slew rate is controlled by attributes
— Included in the input design, or specified in the Constraints Editor
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How to Access I/O Flip-FlopsHow to Access I/O Flip-Flops
During synthesis—Based on the input/output timing requirements, the synthesis
tool will move a flip-flop into the IOB—The designer may specify which registers should be placed
in the IOB– The synthesis tool will specify an IOB=True attribute on a given
register in the netlist for both cases above
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How to Access I/O Flip-FlopsHow to Access I/O Flip-Flops
During implementation—The mapper can move eligible flip-flops into the I/O blocks
– In the Implementation Options dialog, select the Optimize and Map tab
• Pack I/O Registers/Latches into IOBs for (-pr):• [Off | Inputs Only | Outputs Only | Inputs and Outputs]
– -Timing option will map registers in IOB for timing critical paths—Using the Xilinx Constraint Editor’s Misc. tab
– Specify individual registers that should be placed in the IOB
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IOB Flip-Flop RequirementsIOB Flip-Flop Requirements
There are some restrictions to accessing the IO flip-flops:— Input and output registers cannot have combinatorial logic
between pad and register—For three-state IO, all registers must share the same reset
– Can have separate clocks and clock enable—For three-state flip-flop, output must be active-low
– The input to the three-state flip-flop can be inverted, but there is no inverter between the flip-flop and the three-state buffer
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Synchronization CircuitsSynchronization Circuits
What is a synchronization circuit?—Captures an asynchronous input signal and outputs it
onto a clock edge Why do I need synchronization circuits?
—Prevent setup and hold time violations—End result is a more reliable design
When do I need synchronization circuits?—Signals cross between unrelated clock domains—Chip inputs that are fully asynchronous
(not controlled by any clock)
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Violations occur when the flip-flop input changes too close to a clock edge
Three possible results:— Flip-flop clocks in
old data value— Flip-flop clocks in
new data value— Flip-flop output
becomes metastable
Setup and Hold Time ViolationsSetup and Hold Time Violations
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MetastabilityMetastability
What is it?—Flip-flop output enters a transitory state
– Neither a valid zero nor a valid one logic state– The value may be interpreted as a zero by some loads and as a
one by others—The output remains in this state for an unpredictable
length of time before settling to a valid zero or one– Only statistical analysis of metastability is possible
When does it occur?—Result of a transition on the input during the tiny timing
window where the flip-flop accepts new data– Even smaller than the setup-hold-time window
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Guarding Against MetastabilityGuarding Against Metastability
Due to its statistical nature, the occurrence of metastable events can only be reduced, not eliminated
Mean Time Between Failures (MTBF) is exponentially related to the length of time the flip-flop is given to recover—A few extra ns of recovery time can dramatically
reduce the chances of a metastable event The circuits shown in this section allow a full
clock cycle for metastable recovery
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Asynchronous InputsAsynchronous Inputs
This refers to two types of signals—Signals not controlled by any clock—Signals controlled by a clock that is not seen by the FPGA
Two cases to consider— Input pulses are always at least one clock period wide— Input pulses may be less than one clock period wide
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Use this circuit when input pulses will always be at least one clock period wide
The “extra” flip-flop guards against metastability
Synchronization Circuit #1Synchronization Circuit #1
Asynchronous Input
CLK
Synchronized signalD Q D Q
Guards against metastability
FF2FF1
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Synchronization Circuit #1Synchronization Circuit #1
Sample Waveform
Guards against metastability
Asynchronous Input
CLK
Synchronized signalD Q D Q
FF2FF1
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Synchronization Synchronization Circuit #2Circuit #2
Use this circuit when input pulses may be less than one clock period wide— FF1 captures short pulses
D Q
CLR
Asynchronous Input
CLK
Synchronized signalD Q D Q
Guards against metastabilityVCC
FF3FF2FF1
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Synchronization Synchronization Circuit #2Circuit #2
SampleWaveform
D Q
CLRAsynchronous Input
CLK
Synchronized signalD Q D Q
Guards against metastabilityVCC
FF3FF2FF1
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Capture Asynchronous BusCapture Asynchronous Bus
Leading edge detector
Synchronizedbus inputs
Asynchronous Input Clk
CLK
One-shot enable
D Q D Q
Guards against metastability
FF2FF1
D Q
n bitbus
D Q
CE
Guards against metastability
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Capture Asynchronous BusCapture Asynchronous Bus
Leading edge detector VCC Guards against metastability
Q
Asynchronous Input Clk
CLK
One-shot enable
D Q
FF3D Q
FF2D
CLR
FF1
D Q
n bitbus
D Q
CESynchronizedbus inputs
Guards against metastability
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Asynchronous Input ClkAsynchronous
Input Clk
Synchronization Circuit #3Synchronization Circuit #3
Use a FIFO to cross domains
Write Addr
Data
System ClkRead Addr Data
BlockRAMBlockRAM
PortA -Write Port
PortB -Read Port
Wr
Rd
System ClkRd
Wr
FIFO Flags
Full
HalfFullAlmostFull
Empty
HalfEmptyAlmostEmpty
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This page intentionally left blankSkills CheckSkills Check
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Review QuestionsReview Questions
High fanout is one reason to duplicate a flip-flop. What is another reason?
Give an example of a time when you do not need to resynchronize a signal that crosses between clock domains
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AnswersAnswers
High fanout is one reason to duplicate a flip-flop. What is another reason?—Loads are divided between multiple locations on
the chip Give an example of a time when you do not need to
resynchronize a signal that crosses between clock domains—Well-defined phase relationship between the clocks—Example: Clocks are the same frequency, 180º out of phase,
net delays will meet timing
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SummarySummary
You can increase circuit performance by—Duplicating flip-flops—Adding pipeline stages—Using I/O flip-flops
Some tradeoffs—Duplicating flip-flops increases circuit area—Pipelining introduces latency— I/O flip-flop programmable delay trades off setup time and
hold time Synchronization circuits increase reliability
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Where Can I Learn More?Where Can I Learn More?
Online Documentation Virtex-II Data Book: Chapter 2 > Virtex-II Switching
Characteristics Virtex-II Data Book: Chapter 3 > Detailed Description >
Input/Output Blocks (IOBs) XAPP 094: Metastability Recovery