Final Design Review of a 1 GHz LNA / Down-Converter

Charles Baylis

University of South Florida

April 22, 2005

LNA Design Summary

IBM SiGe Design Kit - 4 layers of metal Load resistance = 50 ohms (Filter) Feedback Resistor from collector to base

stabilizes circuit, provides better matching For feedback configuration

IC = 6 mA, RF = 460 ohms (initial – values were changed for final schematic.

50

131.61

om R

AG )50)(131.6()1( OF RAR

LNA Design Summary

Power Consumption: Current through gain transistor + 1 mA reference current through current mirror.

LC Match on Input/Output “De-Q” Inductors with resistors to

improve bandwidth.

LNA Schematic

9.3 pF6.5 nH

83 pF

560 Ω

27 pF

1.4 kΩ7.3 nH

4.5 pF

650 Ω

Input

Output

Ground

Vcc

LNA Gain

LNA Noise Figure

LNA Input IP3

LNA Input/Output Match

LNA ComplianceReqt. Spec. Min Spec. Max Minimum Maximum Pass/Fail

DC Current - 10 mA - 9.8 mA Pass

Gain 14.5 dB 17.5 dB 16.5 dB 16.9 dB Pass

Noise Figure

- 2.5 dB 2.3 dB 2.8 dB Fail

Input IP3 -20 dBm - -2.7 dBm - Pass

Uncond. Stability

- - - - Pass

Input Return Loss

15.0 dB - 15.7 dB 20.9 dB Pass

Output Return Loss

15.0 dB - 15.0 dB 30.3 dB Pass

LNA Compliance-TemperatureReqt. Spec.

MinSpec. Max

Minimum Maximum Pass/Fail

DC Current - 10 mA 9.3 mA (-20˚) 10.2 mA (70˚) Fail

Gain 14.5 dB 17.5 dB 16.0 dB (70˚) 17.5 dB (-20˚) Pass

Noise Figure

- 2.5 dB 1.93 dB (-20˚) 3.24 dB (70˚) Fail

Uncond. Stability

- - - - Pass

Input Return Loss

15.0 dB - 14.7 dB (-20˚) 21.6 dB (70˚) Fail

Output Return Loss

15.0 dB - 14.0 dB (70˚) 31.4 dB (-20˚) Fail

LNA Compliance - BiasReqt. Spec.Min SpecMax Minimum Maximum Pass/Fail

DC Current - 10 mA 8.1 mA (2.7 V) 11.6 mA (3.3 V)

Fail

Gain 14.5 dB 17.5 dB 14.9 dB (2.7 V)

18.0 dB (3.3V)

Fail

Noise Figure

- 2.5 dB 2.3 dB (3.3 V) 2.9 dB (2.7 V)

Fail

Uncond.Stability

- - - - Pass

Input ReturnLoss

15.0 dB - 12.9 dB (3.3 V)

22.2 dB (3.3V)

Fail

OutputReturnLoss

15.0 dB - 10.7 dB (2.7 V)

30.3 dB (3 V)

Fail

LNA Layout

LNA In

Vcc

LNA Out

Mixer Design Approach

fRF = 1 GHz, fLO = 860 MHz, fIF = 140 MHz Conversion gain = 9 dB = 2.82

Output Resistance = 50 ΩRL= 25 Ω

Solve conversion gain equation for gm (gives starting value for current IC1)..

Use LC network for input matching.

82.22 1

ML

v

gRA

Mixer Design Approach

Noise figure improved by shrinking reference transistor for current mirror (and associated current). Also, beta helper transistor size was increased.

As in LNA, “de-Q” inductors with shunt resistors to improve bandwidth.

Mixer Schematic

Input

Out + Out -7.03 kΩ

7 kΩ

Vcc

Ground

7.8 nH

3.7 pF

250 Ω83 pF

LO+ LO-

Mixer Conversion Gain

Mixer Input IP3

Mixer Input/Output MatchInput Reflection Coefficient Output Reflection Coefficient

Mixer Noise Figure

Mixer Compliance

Specified Gain and Bandwidth

Reqt. Spec. Min Spec. Max Minimum Maximum Pass/Fail

DC Current - 25 mA - 12.4 mA Pass

Gain 7.5 dB 10.5 dB 9.3 dB 10.0 dB Pass

Noise Figure

- 11 dB 9.0 dB 10.7 dB Pass

Input IP3 -15 dBm - -12.95 - Pass

Input Return Loss

15.0 dB - 15.2 dB 26.4 Pass

Output Return Loss

15.0 dB - 31.5 dB 31.2 dB Pass

Mixer Compliance - Temperature

Specified Gain and Bandwidth

Reqt. Spec. Min Spec. Max Minimum Maximum Pass/Fail

DC Current - 25 mA 11.47 mA 13.3 mA Pass

Gain 7.5 dB 10.5 dB 7.9 dB 11.1 dB Fail

Noise Figure

- 11 dB 7.1 dB 11.59 dB Fail

Input Return Loss

15.0 dB - 15.0 dB 31.7 Fail

Output Return Loss

15.0 dB - 31.2 dB 31.6 dB Pass

Mixer Compliance - Bias

Specified Gain and Bandwidth

Reqt. Spec. Min Spec. Max Minimum Maximum Pass/Fail

DC Current - 25 mA 9.9 mA 15.1 mA Pass

Gain 7.5 dB 10.5 dB 8.2 dB 10.7 dB Fail

Noise Figure

- 11 dB 7.9 dB 10.9 dB Pass

Input Return Loss

15.0 dB - 13.7 dB 45.4 Fail

Output Return Loss

15.0 dB - 27.8 dB 40.2 dB Pass

Mixer Layout

Vcc

Out -

Out +

LO - LO +-

Mixer In

LNA DRC and LVS

Mixer DRC and LVS

Conclusion

Only LNA noise figure does not meet specification at nominal temperature and bias.

Design has been run through multiple simulations to test its robustness.