Post on 03-Apr-2018
Data Sheet
1
Product Overview
Service providers and enterprises
are constantly required to support
higher numbers of customers per
interface, which in turn maximizes
their revenue potential and
reduces operational and capital
expenditures for each router
deployed. The Juniper Networks
Enhanced IQ PIC family is a
collection of SONET/SDH, PDH,
channelized and non-channelized
interfaces that can support
large numbers of customers per
interface across a broad range
of interface types and speeds
(from T1/E1 to OC48/STM16) with
advanced class-of-service (CoS)
capabilities.
Product Description The Juniper Networks® Enhanced IQ PIC product family is a suite of highly sophisticated
hardware and software modules that implement the next generation of class of service,
class-based traffic management and high-level channelization capabilities. The product
suite consists of ten PICs to meet various speed and density requirements:
• Seven Type-1 PICs: 1-port Channelized OC12/STM4, 1-port clear-channel
OC12/STM4, 2-port Channelized OC3/STM1, 4-port clear-channel OC3/STM1,
4-port Channelized DS3/E3, 4-port clear-channel DS3/E3, and 10-port Channelized
E1/T1 PIC
• Two Type-2 PICs: 4-port Channelized OC12/STM4 and 1-port Channelized
OC48/STM16 Nonconcatenated
• One Type-3 PIC: 4-port clear channel OC48/STM-16
Juniper Networks innovative Enhanced IQ PIC family extends the latest technical
advancements in traffic management technology, allowing service providers and
enterprises to meet their most demanding needs in term of cost-effective TDM aggregation.
Leveraging Juniper Networks flexible channelization capabilities of the queuing FPGA,
the Enhanced IQ PIC family applies a rich set of CoS features and hierarchical Traffic
Management capabilities that underpin the assured delivery of high-value multiplay
services in both enterprise and service provider environments. The FPGA is software
programmable, increasing investment protection by permitting the future addition of new
features via new software releases.
Features and BenefitsFlexible Port Configuration
The Enhanced IQ PIC family allows per-port selection of the SONET or SDH framing
type, providing customers with the ability to consolidate different access types on the
same PIC. SONET/SDH PICs use standard small form-factor pluggable transceiver
(SFP) modular optics, which adds another level of flexibility and further simplifies spare
management. The PICs also support the full DLCI range along with sparse numbering for
maximum ease of operation.
Flexible and Dense Channelization
In the case of Channelized PICs, the hardware based Traffic Manager provides deep
channelization support of any type of port down to NxDS0 and offers the flexibility of
mixing any combination of channel sizes on the same port. By offering an interface that
can support a full range of access speeds, service providers and enterprises achieve a great
level CapEx and OpEx savings by only needing to deploy one interface for any combination
of NxDS0, DS1/E1, fractional DS1/E1 or subrate DS3 and OC3/STM1. The Enhanced IQ PICs
multiple levels of channelization enable service providers and enterprises to easily grow
subscribers from lower to higher bandwidth speeds without changing interfaces.
Enhanced IQ PICs
Your ideas. Connected.™
2
Data SheetEnhanced IQ PICs
Advanced Hierarchical Traffic Management
The Enhanced IQ PIC family supports the allocation of up to
eight1 queues per channel and features a dual-rate shaper
capability (committed and excess) with priority propagation from
queues2 to channel levels across a 3-level hierarchy. Accordingly,
the Traffic Manager can deliver differentiated multiplay services
with distinct class-of-service requirements while ensuring
proper prioritization and fairness among the various services
and customers. These hierarchical scheduling3 capabilities allow
enterprises and service providers to efficiently consolidate their
access networks and consequently maximize their revenue per
port without compromising on the service quality and value.
Enhanced Queuing Capabilities with Low Latency Egress Queuing
The Traffic Manager supports up to eight queues per channel
with five levels of priorities—three guaranteed and two excess.
An optional Layer 2 (L2)-aware rate limit can be enforced on the
strict4 high-priority level to prevent lower priority queues from
traffic starvation. These queuing capabilities allow defining a very
fine-grained class-of-service model to meet the most stringent
multiplay traffic requirements, ensuring that prioritization, delay
and jitter characteristics are enforced for each traffic class.
Increased Delay Buffers
The FPGA is capable of buffering several seconds5 of traffic.
This high level of buffering permits shaping of outgoing traffic on
low-speed interfaces with minimal packet loss to meet assured
forwarding network traffic requirements like critical file transfers.
Enhanced Statistics and Diagnostic
The FPGA also provides a complex and granular set of
instrumentations and counters, such as L2 per-queue packet/
byte counters and L2 per-queue packet/byte drop counters.
These features enable superior billing and accounting
functionalities and allow statistics to be collected for network
design and planning. The Enhanced IQ PIC family also features
advanced diagnostics6 such as far end activation code (FEAC),
loopback testing at channel levels and a wide selection of bit
error rate test (BERT) patterns for simplifying troubleshooting
operations.
4-port Channelized DS3/E3
4-port DS3/E3
4-port OC3/STM11-port OC12/STM4
2-port channelized OC3/STM1
1-port Channelized OC12/STM4
10-port Channelized T1/E1
4-port Channelized OC12/STM4
1-port Channelized OC48NC/STM16
3
Data SheetEnhanced IQ PICs
SpecificationsPhysical (W x H x D)
• 4 x 1 x 7 in (10.16 x 2.54 x 17.78 cm)
CoS Support• Weighted Random Early Detection (WRED)
- 16 unique drop profiles7
- 4 drop precedences
- Tail queue drop
• Ingress DSCP rewrite
• Three levels of hierarchical scheduling with LLQ8
- PQ-MDRR algorithm
• 8k egress queues
MIB Support • SNMP information retrievable at all levels of channelization
• RFC 1595 (SONET/SDH MIB)
• RFC 1406 (T1/E1 MIB)
• RFC 1407 (T3/E3 MIB)
Encapsulation • Point-to-Point Protocol (PPP)
• MPLS Circuit Cross-connect (CCC)
• MPLS translational cross-connect (TCC)
• Frame Relay
• Frame Relay CCC
• MLPPP8
• MLFR8
• FRF.15, FRF.168
• Flexible Frame Relay (not necessary)
• PPP over Frame Relay8
• Cisco High-Level Data Link Control (cHDLC)
BERT Support8
• Support at DS0, DS1/E1, DS3/E3
• Default setting is 215-1 pseudorandom
• Test patterns configurable to run in framed and unframed mode – BERT pattern is transmitted unframed
• BERT sessions are simultaneous
• Test patterns configurable per channel
• Test patterns with bit-error rates from 0 to 10-3 inject, detect and count
• Test patterns
- All ones
- All zeros
- Alternating ones and zeros (AA/55)
- 1:3 or 1 in 4 pattern - 1 bit set in every 4
- 1:7 or 1 in 8 pattern - 1 bit set in every 8
- PRBS 29-1 (as specified in ITU-T O.153)
- PRBS 211-1 (as specified in ITU-T O.153)
- PRBS 215-1 (as specified in ITU-T O.151/O.153)
- PRBS 220-1 (as specified in ITU-T O.153)
- PRBS 223-1 (as specified in ITU-T O.151/O.153)
• 32-bit programmable pattern
• Error insertion at user-defined rate of 10-3 SONET/SDH Features
SONET/SDH Features • Loopback supported on all interface speeds
- Remote payload loopback
- Local line loopback
- Remote line loopback
- Each channel can be looped back individually and independently
• Mapping Granularity: Each DS3/STS1 is individually configurable
• SONET scrambler
• SONET APS
• CRC: 16 bit and 32 bit
• SONET error detection:
- Loss of Light (LOL)
- Phase Lock Loop (PLL)
- Loss of Frame (LOF)
- Loss of Signal (LOS)
- Severely Errored Framing (SEF)
- Alarm Indication Signal - Line (AIS-L)
- Alarm Indication Signal - Path (AIS-P)
- Loss of Pointer (LOP)
- Bit Error Rate - Signal Degrade (BERR-SD)
- Bit Error Rate - Signal Fail (BERR-SF)
- Remote Defect Indicator - Line (RDI-L)
- Remote Defect Indicator - Path (RDI-P)
- Remote Error Indicator (REI)
- Unequipped (UNEQ)
- Payload Label Mismatch - Path (PLM-P)
- Loss of Clock (LOC)
- Virtual Container Alarm Indication Signal (VAIS)8
- Virtual Container Loss of Pointer (VLOP)8
- Virtual Container Remote Defect Indicator (VRDI)8
- Virtual Container Unequipped (VUNEQ)8
- Virtual Container Mismatch (VMIS)8
- Virtual Container Loss of Clock (VLOC)8
• SDH error detection:
- Loss of Light (LOL)
- Phase Lock Loop (PLL)
- Loss of Frame (LOF)
- Loss of Signal (LOS)
- Severely Errored Framing (SEF)
- Multiplex Section Alarm Indication Signal (MS-AIS)
- High Order Path Alarm Indication Signal (HP-AIS)
- Loss of Pointer (LOP)
- Bit Error Rate – Signal Degrade (BERR-SD)
- Bit Error Rate – Signal Fail (BERR-SF)
- Multiplex Section – Far-End Receive Failure (MS-FERF)
- High-order Path – Far-End Receive Failure (HP-FERF)
- Remote Error Indication (REI)
4
Data SheetEnhanced IQ PICs
- Unequipped (UNEQ)
- High-order Path – Payload Label Mismatch – Path (HP-PLM)
- Loss of Clock (LOC)
- Tributary Unit – Alarm Indication Signal (TU-AIS)8
- Tributary Unit – Loss of Pointer (TU-LOP)8
- Tributary Unit – Remote Defect Indicator (TU-RDI)8
- Tributary Unit – Unequipped (TU-UNEQ)8
- Tributary Unit – Mismatch (TU-MIS)8
- Tributary Unit – Loss of Clock (TU-LOC)8
DS3/E3 Features • DS3 and E3 are selectable on a per-port granularity
• Framing: M13, C-bit parity, framed clear channel
• DS3 Scrambling:
- Digital Link/Quick Eagle
- Kentrox
- Larscom
- ADTRAN
- Verilink
• Subrate is supported on DS3 with the following vendor algorithms:
- Digital Link/Quick Eagle
- Kentrox
- Larscom
- ADTRAN
- Verilink
• DS1 and E1 interface supports fractional DS1/E1
• Loopbacks that are supported:
- Remote payload loopback
- Local line loopback
- Remote line loopback
• Clocking: Internal and loop
• DS3 FEAC
• DS3/E3 Alarms (conformance to ANSI specification T1.404)
- Alarm Indication Signal (AIS)
- Out Of Frame (OOF); also known as Loss Of Frame (LOF)
- Loss Of Signal (LOS)
- Phase-Locked Loop (PLL)
• Alarm reporting – 24-hour history maintained for error statistics and failure counts, 15-minute intervals on all errors
- Alarm logged in system log file
- Intervals shown on Command Line Interface (CLI) show command
• DS3/E3 Error Detection (per-second polling)
- P-bit Code Violations (PCV)
- C-bit Code Violations (CCV)
- Line Errored Seconds (LES)
- P-bit Errored Seconds (PES)
- C-bit Errored Seconds (CES)
- Severely Errored Framing Seconds (SEFS)
- P-bit Severely Errored Seconds (PSES)
- C-bit Severely Errored Seconds (CSES)
- Unavailable Seconds (UAS)
- Far-end block error (FEBE)
- Excessive zeroes (EXZ)
- Far-end receive failure (FERF)
- CRC errors
DS1/T1 Features • Framing: Superframe (D4) and Extended Superframe (ESF),
framed clear channel
• Loopback support:
- Remote payload
- Local line
- Remote line
• Clocking: Internal and loop (clock recovered from network and used for TX) will be supported– Default for Channelized T1: Internal timing
• CRC: 6-bit (ESF only)
• Support sending and receiving inband loopback codes in both framed and unframed mode
- Framed inband loopback at CSU
- Framed inband loopback at Smartjack (ANSI)
- Unframed inband loopback at CSU
- Unframed inband loopback at Smartjack (ANSI)
- FDL loopback for T1-ESF mode interfaces (ANSI T1.403)
• MTU: 9K
• T1 Alarms (conformance to ANSI specification)
- Alarm Indication Signal (blue) – AIS
- Out Of Frame (red) – OOF; also known as Loss Of Frame (LOF)
- Remote Alarm Indication Signal (yellow) – RAIS
- Alarm reporting – 24-hour history maintained for error statistics and failure counts, 15-minute intervals on all errors
• Error Detection (conformance to ANSI specification)
- Controlled Slipped Seconds (CSS or CS)
- Line Errored Seconds (LES)
- Errored Seconds (ES)
- Bursty Errored Seconds (BES)
- Severely Errored Seconds (SES)
- Severely Errored Framing Seconds (SEFS)
- Loss Of Signal Seconds (LOS)
- Loss Of Framing Seconds (LOFS)
- Unavailable Seconds (UAS)
- CRC errors
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Data SheetEnhanced IQ PICs
Agency Approvals
Safety
• UL1950 (USA)
• EN 60950 (Europe, derivative of IEC 60950)
• EN 60825-1 (Europe, special for laser safety)
• CSA C22.2 No.950 (Canada)
• AS/NZS 60950 (Australia, New Zealand, derivative of IEC 60950)
EMC
• FCC Part 15 Class B (USA)
• EN 55022 Class B (Europe) (colloquially called CISPR 22)
• VCCI Class B (Japan)
• BSMI Class B (Taiwan)
• AS/NZ 3548 Class B (Australia)
Immunity
• EN-61000-3-2 Power Line Harmonics
• EN-61000-4-2 ESD
• EN-61000-4-3 Radiated Immunity
• EN-61000-4-4 EFT
• EN-61000-4-5 Surge
• EN-61000-4-6 Low Frequency Common Immunity
• EN-61000-4-11 Voltage Dips and Sags
• ETS-300386-2 Switching Equipment
CE Marking
• Meets European CE marking requirements
Channelization Supported
SONET/T-CARRIER Hierarchy
PIC OC12 OC3 DS3 DS1 DS0
1 x ChOC48/ChSTM16
4 x ChOC12/ChSTM4
1 x ChOC12/ChSTM4 1011
2 x ChOC3/ChSTM1 1011
4 x ChDS3/E3 1011
10 x ChT1/ChE1
SDH/E-CARRIER Hierarchy
PIC STM4 STM1 E3 E1 DS0
1 x ChOC48/ChSTM16
4 16 48 504 974
4 x ChOC12/ChSTM4
4 16 48 504 974
1 x ChOC12/ChSTM4 1 4 12 252 1011
2 x ChOC3/ChSTM1 - 2 6 126 1011
4 x ChDS3/E3 - - 4 - -
10 x ChT1/ChE1 - - - 10 310
Optical Diagnostics and Monitoring (SFF-8472 Rev 9.5)
High Alarm
Low Alarm
High Warning
Low Warning
Temperature ±3° C ±3° C ±3° C ±3° C
Supply Voltage ±3% ±3% ±3% ±3%
TX Bias Current ±10% ±10% ±10% ±10%
TX Output Power ±3 db ±3 db ±3 db ±3 db
RX Recv Power ±3 db ±3 db ±3 db ±3 db
Minimum CFEB/FPC9 Requirements
Platform Type-1 Type-2 Type-3
M10i/M7i Enhanced CFEB N/A N/A
M40e M40e-FPC1-EP M40e-FPC2-EP N/A
M120 M120-FPC1 and associated M120-FEB
M120-FPC2 and associated M120-FEB
M120-FPC3
M320 M320-FPC1-E2,M320-FPC1-E3
M320-FPC2-E2,M320-FPC2-E3
M320-FPC3-E3
T320 T320-FPC1-E,T320-FPC1-E2
T320-FPC2-E,T320-FPC2-E2
N/A
T640/T1600
T640-FPC1-E,T640-FPC1-E2
T640-FPC2-E,T640-FPC2-E2
T640-FPC3-ES
MX240/MX480/MX960
N/A N/A MX-FPC3
Juniper Networks Services and SupportJuniper Networks is the leader in performance-enabling services
that are designed to accelerate, extend, and optimize your
high-performance network. Our services allow you to maximize
operational efficiency while reducing costs and minimizing
risk, achieving a faster time to value for your network. Juniper
Networks ensures operational excellence by optimizing the
network to maintain required levels of performance, reliability,
and availability. For more details, please visit www.juniper.net/us/
en/products-services.
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Data SheetEnhanced IQ PICs
1000251-007-EN Dec 2014
Ordering InformationPart numbers that begin with PE- are for deployment on M7i/
M10i routers; PB- part numbers are for installation in M40e, M120,
M320, and T Series routers.
Channelized PICs
IQ-E Part Number* Description Type
PB-4CHDS3-E3-IQE-BNC PE-4CHDS3-E3-IQE-BNC
4-port Channelized DS3/E3 1
PB-1CHOC12-STM4-IQE-SFP PE-1CHOC12STM4-IQE-SFP
1-port Channelized OC12/STM4 - requires separate SFP optics
1
PB-2CHOC3-STM1-IQE-SFP PE-2CHOC3-STM1-IQE-SFP
2-port Channelized OC3/STM1 - requires separate SFP optics
1
PB-10CHE1-T1-IQE-RJ48 PE-10CHE1-T1-IQE-RJ48
10-port Channelized T1/E1 1
PB-4CHOC12-STM4-IQE-SFP
4-port Channelized OC12/STM4 - requires separate SFP optics
2
PB-1CHOC48-STM16-IQE 1-port Channelized OC48NC/STM16 - requires separate SFP optics
2
Non-Channelized PICs
IQ-E Part Number* Description Type
PB-4DS3-E3-IQE-BNC PE-4DS3-E3-IQE-BNC
4-port DS3/E3 1
PB-1OC12-STM4-IQE-SFP PE-1OC12-STM4-IQE-SFP
1-port OC12/STM4 - requires separate SFP optics
1
PB-4OC3-STM1-IQE-SFP PE-4OC3-STM1-IQE-SFP
4-port OC3/STM1 - requires separate SFP optics
1
PC-4OC48-STM16-IQE-SFP 4-port OC48/STM16 - requires separate optics
3
SFP Options
IQ-E Part Number Description
SFP-1OC3-SR OC3 SFP 1310 nm 2 km reach multimode
SFP-1OC3-IR OC3 SFP 1310 nm 15 km reach single mode
SFP-1OC3-LR OC3 SFP 1310 nm 40 km reach single mode
SFP-1OC12-SR OC12 SFP 1310 nm 2 km reach multimode
SFP-1OC12-IR OC12 SFP 1310 nm 15 km reach single mode
SFP-1OC12-LR OC12 SFP 1310 nm 40 km reach single mode
SFP-1OC12-LR2 OC12 SFP 1510 nm 80 km reach single mode
SFP-1OC48-SR OC48 SFP 1310 nm 2 km reach multimode
SFP-1OC48-IR OC48 SFP 1310 nm 15 km reach single mode
SFP-1OC48-LR OC48 SFP 1550 nm 80 km reach single mode
1 On appropriate platforms.2 Type-3 4xOC48 PIC does not support queue level shaper.3 Hierarchical scheduling capabilities not supported with the Type-3 PIC.4 Type-3 4xOC48 PIC supports rate limit for any queue either strict of non-strict.5 Type-3 4xOC48 PIC supports 214ms buffer which can be used for the 4DLCI where each
DLCI is running 2.5 Gbps (one DLCI per OC48).6 This is for channelized PICs only. For the non-channelized PICs, this is supported only at the
port level.7 Type-3 PIC 32 drop profiles are supported (4 drop profiles per queue).8 Not supported on Type-3 4xOC48 PIC.9 Compact Forwarding Engine Boards/Flexible PIC Concentrator.
About Juniper NetworksJuniper Networks is in the business of network innovation. From
devices to data centers, from consumers to cloud providers,
Juniper Networks delivers the software, silicon and systems that
transform the experience and economics of networking. The
company serves customers and partners worldwide. Additional
information can be found at www.juniper.net.