EE247 Lecture 16 - University of California, Berkeleyee247/fa05/lectures/L16... · 2005-10-20 ·...

EE247Lecture 16

D/A converters continued:• Current based DACs-unit element versus binary weighted• Static performance

– Component matching-systematic & random errors• Practical aspects of current-switched DACs• Segmented current-switched DACs• DAC self calibration techniques

– Current copiers– Dynamic element matching

ADC Converters• Sampling

– Sampling switch induced distortion– Sampling switch charge injection

Current Source DACUnit Element

• “Unit elements ”• 2B-1 current sources & switches • Monotonicity does not depend on element matching• Suited for both MOS and BJT technologies• Output resistance of current source causes gain error

Iref Iref

IrefIref

……………

Current Source DACUnit Element

• Output resistance of current source à gain error problemàUse transresistance amplifier

- Current source output held @ virtual ground - Error due to current source output resistance eliminated- New issues: offset & speed of the amplifier

Iref IrefIrefIref

……………

Current Source DACBinary Weighted

• “Binary weighted”• B current sources & switches (2B-1 unit current

sources but less # of switches)• Monotonicity depends on element matching

4 Iref Iref

2Iref2B-1 Iref

……………

Static DAC INL / DNL Errors• Component matching• Systematic errors

– Finite current source output resistance – Contact resistance– Edge effects in capacitor arrays– Process gradient

• Random errors– Lithography– Often Gaussian distribution (central limit

theorem)

*Ref: C. Conroy et al, “Statistical Design Techniques for D/A Converters,” JSSC Aug. 1989, pp. 1118-28.

Gaussian Distribution

-3 -2 -1 0 1 2 30

1p( x ) e

where standard deviat ion : E( x )

−−

( )2xX

P X x X

− ≤ ≤ + =

0 0.5 1 1.5 2 2.5 30

0.20.40.60.8

X/σ P(-X ≤ x ≤ X) [%]

0.2000 15.85190.4000 31.08430.6000 45.14940.8000 57.62891.0000 68.26891.2000 76.98611.4000 83.84871.6000 89.04011.8000 92.81392.0000 95.4500

X/σ P(-X ≤ x ≤ X) [%]

2.2000 97.21932.4000 98.36052.6000 99.06782.8000 99.48903.0000 99.73003.2000 99.86263.4000 99.93263.6000 99.96823.8000 99.98554.0000 99.9937

Example

• Measurements show that the offset voltage of a batch of operational amplifiers follows a Gaussian distribution with σ = 2mV and µ = 0.

• Fraction of opamps with |Vos| < 6mV:– X/σ = 3 à 99.73 % yield

• Fraction of opamps with |Vos| < 400µV:– X/σ = 0.2 à 15.85 % yield

Component Mismatch

1004 1008 1012996992988R[ ]Ω

Example: Side-by-side resistors

E.g. Let us assume in this example large # of Rs with average of 1000OHM measured: 68.5% within +-4OHM or +-0.4% of averageà 1σ for resistorsà 0.4%

Large # of devices measured & curved àtypically if sample size is large shape is Gaussian

…….…….

Component Mismatch

dR R R

Areaσ

σ 2σ 3σ−σ−2σ−3σdR

Two side-by-sideResistors

For typical technologies & geometries1σ for resistorsà 0.02 το 5%

In the case of resistors σ is a function of area

DNL Unit Element DAC

i i refR I∆ =

DNL of unit element DAC is independent of resolution!

E.g. Resistor string DAC:

median ref

i i re f

median ii

median

i median

imedian median

DNL dR

R R dR dR

∆ − ∆=

−= = ≈

DNL Unit Element DAC

Example:If σdR/R = 0.4%, what DNL spec goes into the datasheet so that 99.9% of all converters meet the spec?

DNL of unit element DAC is independent of resolution!Note similar results for all unit-element based DACs

DNL dR

σ σ=

X/σ P(-X ≤ x ≤ X) [%]

0.2000 15.85190.4000 31.08430.6000 45.14940.8000 57.62891.0000 68.26891.2000 76.98611.4000 83.84871.6000 89.04011.8000 92.81392.0000 95.4500

X/σ P(-X ≤ x ≤ X) [%]

2.2000 97.21932.4000 98.36052.6000 99.06782.8000 99.48903.0000 99.73003.2000 99.86263.4000 99.93263.6000 99.96823.8000 99.98554.0000 99.9937

DNL Unit Element DACExample:If σdR/R = 0.4%, what DNL spec goes into the datasheet so that 99.9% of all converters meet the spec?

Answer:From table: for 99.9% à X/σ = 3.3σDNL = σdR/R = 0.4%3.3 σDNL = 1.3%

àDNL= +/- 0.013 LSB

DNL dR

σ σ=

DAC INL Analysis

N=2B-1n

Input [LSB]

Ideal VarianceA=n+E n n.σε

B=N-n-E N-n (N-n).σε2

E = A-n r =n/N N=A+B= A-r(A+B)= A (1-r) -B.rà Variance of E:

σE2 =(1-r)2 .σΑ

2 + r 2 .σB2

=N.r .(1-r).σε2

DAC INL

• Error is maximum at mid-scale (N/2):

• INL depends on DAC resolution and element matching σε

• While σDNL = σε

Ref: Kuboki et al, TCAS, 6/1982

To find max. variance: 0dn

n N / 2

2 with N 2 1

−= ×

Untrimmed DAC INL

Example:

Assume the following requirement:σINL = 0.1 LSB

Then:σε = 1% à B = 8.6σε = 0.5% à B = 10.6σε = 0.2% à B = 13.3σε = 0.1% à B = 15.3

−≅

B 2log22

Simulation Example

σε = 1%B = 12Random # generator used in MatLab

Computed INL:σDNL = 0.01 LSBσINL = 0.3 LSB(midscale)

500 1000 1500 2000 2500 3000 3500 4000-1

]12 Bit converter DNL and INL

-0.04 / +0.03 LSB

500 1000 1500 2000 2500 3000 3500 4000-1

] -0.2 / +0.8 LSB

Binary Weighted DAC INL/DNL

• INL same as for unit element DAC

• DNL depends on transition– Example:

0 to 1àσDNL2 = σ(dΙ/Ι)

1 to 2 àσDNL2 = 3σ(dΙ/Ι)

• Consider MSB transition: 0111 … à 1000 …

4 Iref Iref

2Iref2B-1 Iref

……………

MOS Device Matching Effects

d1 d 2d

d d1 d2

Wd thL

W GSd thL

dI I II I

dI d dVI V V

= +−

Id1 Id2

• Current matching depends on:- Device W/L ratio matching à Larger device area less mismatch effect

- Threshold voltage matchingà Larger gate-overdrive less threshold voltage mismatch effect

Current-Switched DACs in CMOS

Wd thL

Wd GS thL

dI d dV

I V V= +

……

Switch Array

•Advantages:Can be very fastSmall area for < 9-10bits

•Disadvantages:Accuracy depends on device W/L & Vth matching

256 128 64 ………..…..1

Example: 8bit Binary Weighted

Binary Weighted DAC DNL

( ) ( )

DNLmaxB

INL DNLmax max

2 B 1 2 B 1 2DNL

1 12 1

0111... 1000...

σ σ σ

− −

≅ − ≅

= − +

1442443 14243

• Worst-case transition occurs at mid-scale:

• Example:B = 12, σε = 1%àσDNL = 0.64 LSBàσINL = 0.32 LSB

2 4 6 8 10 12 140

DAC input code

L2 / σ ε

“Another” Random Run …Now (by chance) worst DNL is mid-scale.

Close to statistical result!500 1000 1500 2000 2500 3000 3500 4000-2

DNL and INL of 12 Bit converter

-1 / +0.1 LSB,

500 1000 1500 2000 2500 3000 3500 4000-1

-0.8 / +0.8 LSB

Unit Element versus Binary Weighted DAC

Unit Element DAC Binary Weighted DAC

Number of switched elements:

Key point: Significant difference in performance and complexity!

DNL INL

σ σ σ

σ σ−

Unit Element versus Binary Weighted DACExample: B=10

S 2 1024

σ σ σ−

Significant difference in performance and complexity!

S B 10

σ σ σ

σ σ σ−

Unit Element DAC Binary Weighted DAC

Number of switched elements:

DAC INL/DNL Summary• DAC architecture has significant impact on DNL

• INL is independent of DAC architecture and requires element matching commensurate with overall DAC precision

• Results are for uncorrelated random element variations

• Systematic errors and correlations are usually also important

Ref: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of resistor string A/D converters. IEEE Transactions on Circuits and Systems, vol.CAS-29, (no.6), June 1982. p.383-9.

Segmented DAC• Objective:

Compromise between unit element and binary weighted DAC

• Approach:B1 MSB bits à unit elementsB2 LSB bits à binary weighted

• INL: unaffected• DNL: worst case occurs when LSB DAC turns off and one more MSB

DAC element turns on- same as binary weighted DAC with B2+1 bits• Number of switched elements: (2B1-1) + B2

Unit Element Binary Weighted

VAnalog

MSB (B1 bits) (B2 bits) LSB

… …

BTotal = B1+B2

ComparisonExample:

B = 12, B1 = 5, B2 = 7B1 = 6, B2 = 6

σε = 1%

( )B 122

DNL INL

S 2 1 B

σ σ σ

= − +

409512

31+7=3863+6=69

0.010.640.160.113

0.320.320.320.32

Unit element (12+0)Binary weighted(0+12)Segmented (5+7)Segmented (6+6)

# of switched elements

σDNL[LSB]σINL[LSB]DAC Architecture

MSB LSB

Practical AspectsCurrent-Switched DACs

• Unit element DACs ensure monotonicity by turning on equal-weighted current sources in succession

• Typically current switching performed by differential pairs

• Based on the code only one of the diff. pair devices are onà device mismatch not an issue

• Issue: While binary weighted DAC can use the incoming binary digital code directly, unit element requires a decoderà N to (2N-1) decoder

Binary Thermometer000 0000000001 0000001010 0000011011 0000111100 0001111101 0011111110 0111111111 1111111

SegmentedCurrent-Switched DAC

• 4-bit MSB Unit element DAC + 4-bit binary weighted DAC

• Note: 4-bit MSB DAC requires extra 4-to-16 bit decoder

• Digital code for both DACs stored in a register

Segmented Current-Switched DACCont’d

• 4-bit MSB Unit element DAC + 4-bit binary weighted DAC

• Note: 4-bit MSB DAC requires extra 4-to-16 bit decoder

• Digital code for both DACs stored in a register

Segmented Current-Switched DACCont’d

• MSB Decoderà Domino logicà Example: D4,5,6,7=1

• Registerà Latched NAND gate:à CTRL=1 OUT=INB

Register

Domino Logic

Segmented Current-Switched DACReference Current Considerations

• Iref is referenced to VDD

à Problem: Reference current varies with supply voltage

Segmented Current-Switched DACReference Current Considerations

• Iref is referenced to VssàGND

Segmented Current-Switched DACConsiderations

• Example: 2-bit MSB Unit element DAC + 3-bit binary weighted DAC

• To ensure monotonicity at the MSBà LSB transition: First OFF MSB current source is routed to LSB current generator

Dynamic DAC Error: Glitch

• Consider binary weighted DAC transition 011 à 100

• DAC output depends on timing

• Plot shows situation where– LSB/MSBs on time– LSB early, MSB late– LSB late, MSB early

1 1.5 2 2.5 30

ly1 1.5 2 2.5 3

TimeLa

Glitch Energy

• Glitch energy (worst case) proportional to: dt x 2B-1

• dt à error in timing & 2B-1 associated with half of the switches changing state

• LSB energy proportional to: T=1/fs

• Need dt x 2B-1 << T or dt << 2-B+1 T

• Examples:

<< 488<< 1.5<< 2

121610

dt [ps]Bfs [MHz]

DAC Reconstruction Filter

• Need for and requirements depend on application

• Tasks:– Correct for sinc distortion– Remove “aliases”

(stair-case approximation)

B fs/2

0 0.5 1 1.5 2 2.5 3

tFrequency

Reconstruction Filter Options

• Digital and SC filter possible only in combination with oversampling (signal bandwidth B << fs/2)

• Digital filter– Bandlimits the input signal à prevent aliasin– Could also provide high-frequency pre-emphasis to

compensate in-band sinc amplitude droop associated with the inherent DAC ZOH function

DigitalF ilter

DAC SCFilter

ZOH CTFilter

DAC Implementation Examples• Untrimmed segmented

– T. Miki et al, “An 80-MHz 8-bit CMOS D/A Converter,” JSSC December 1986, pp. 983

– A. Van den Bosch et al, “A 1-GSample/s Nyquist Current-Steering CMOS D/A Converter,” JSSC March 2001, pp. 315

• Current copiers:– D. W. J. Groeneveld et al, “A Self-Calibration Techique for

Monolithic High-Resolution D/A Converters,” JSSC December 1989, pp. 1517

• Dynamic element matching:– R. J. van de Plassche, “Dynamic Element Matching for High-

Accuracy Monolithic D/A Converters,” JSSC December 1976, pp. 795

2µ tech., 5Vsupply6+2 segmented8x8 array

Two sources of systematic error:- Finite current source output resistance- Voltage drop due to finite ground bus resistance

Current-Switched DACs in CMOS( )

M 2 M 1

M 3 M 1

M 4 M 1

2GS th1

GS GS2

2GS th2 1

GS th2

m2 1 1 m

3 1 1 m

V VI kV V 3RIV V 5RIV V 6RI

3RI1V VI k I

3RgI I I 1 3Rg12

5RgI I I 1 5Rg12

6RgI I 12

−== −= −= −

−−= = − =

→ = ≈ −−

→ = −

( )M 1

1 mI 1 6Rg≈ −

•Assumption: RI is small compared to transistor gate overdriveà Desirable to have gm small

Example: 4 unit element current sources

I1 I2 I3 I4

3RI 2RI RI

M1 M2 M3 M4

More recent published DAC using symmetrical switching built in 0.35micron/3V

I/2 I/2

Current Divider

16bit DAC (6+10)- MSB DAC uses calibrated current sources

I/2 I/2

Ideal Current Divider

Current Divider Accuracy

I/2+dId /2

Real Current Divider

M1& M2 mismatched

d1 d 2d

d d1 d 2

thWLd GS th

dI I I

ddI 2dV

= × +

I/2-dId /2

M1 M2M1 M2

àProblem: Device mismatch could severely limit DAC accuracy

Dynamic Element Matching

( ) ( )

(1) ( 2 )2 2

for smal l2

− ∆ + + ∆=

≈ ∆

( )( )

(1) 1 o 11 2(1) 1 o 12 2

= + ∆

= − ∆

/ 2 error ∆1

During Φ1 During Φ2

Io/2Io/2( )( )

( 2 ) 1 o 11 2( 2 ) 1 o 12 2

= − ∆

= + ∆

Dynamic Element Matching

( )( )

( )( )( )214

121)1(

∆+∆+=∆+=

∆−=

II ( )( )

( )( )( )214

121)2(

∆−∆−=∆−=

∆−=

During Φ1 During Φ2

( )( ) ( )( )

∆∆+=

∆−∆−+∆+∆+=

E.g. ∆1 = ∆2 = 1% à matching error is (1%)2 = 0.01%

/ 2 error ∆1

/ 2 error ∆2

Io/4Io/4

SummaryD/A Converter

• D/A architecture – Unit element – complexity proportional to 2B- excellent DNL – Binary weighted- complexity proportional to B- poor DNL– Segmented- unit element MSB(B1)+ binary weighted LSB(B2)à complexity

proportional (2B1-1) + B2 – DNL compromise between the two• Static performance

– Component matching• Dynamic performance

– Glitches• DAC improvement techniques

– Symmetrical switching rather than sequential switching– Current source self calibration– Dynamic element matching

MOS Sampling Circuits

Re-Cap

• How can we build circuits that "sample"

Analog Post processing

D/AConversion

A/D Conversion

Analog Preprocessing

Analog Input

Analog Output

000...001...

Anti-AliasingFilter

Sampling+Quantization

"Bits to Staircase"

Reconstruction Filter

Ideal Sampling

• In an ideal world, zero resistance sampling switches would close for the briefest instant to sample a continuous voltage vIN onto the capacitor C

• Not realizable!

vIN vOUT

T=1/fS

Ideal T/H Sampling

vIN vOUT

• Vout tracks input when switch is closed• Grab exact value of Vin when switch opens• "Track and Hold" (T/H) (often called Sample & Hold!)

T=1/fS

Ideal T/H Sampling

ContinuousTime

T/H signal(SD Signal)

DT Signal

Practical Sampling

vIN vOUT

• Switch induced noise power à kT/C • Finite Rswà limited bandwidth• Rsw = f(Vin) à distortion• Switch charge injection • Clock jitter

kT/C Noise

In high resolution ADCs kT/C noise usually dominates overall error (power dissipation considerations).

−≥

∆≤

0.003 pF0.8 pF13 pF

206 pF52,800 pF

812141620

Cmin (VFS = 1V)B

Acquisition Bandwidth

• The resistance R of switch S1 turns the sampling network into a lowpass filter with risetime = RC = τ

• Assuming Vin is constant during the sampling period and C is initially discharged

vIN vOUT

( )τ/1)( tinout evtv −−=

Switch On-Resistance

Example:B = 14, C = 13pF, fs = 100MHz

T/τ >> 19.4, R << 40Ω

vIN vOUT

T=1/fS

Worst Case:

12 ln 2 1

1 12 ln 2 1

in outs

V V tf

− = << ∆

<< ∆=

<< −−

Switch On-Resistance

( ) ( )

( )( )

D triodeDSD triode ox GS TH DS

ON DS V

ox GS th ox DD th in

ox DD th

dIW VI C V V V

L R dV

C V V C V V VL L

C V VL

= − − ≅

= =− − −

Sampling Distortion

outT V

12 V V

v 1 e τ

− − −

10bit ADC & T/τ = 10VDD – Vth = 2V VFS = 1V

Sampling Distortion

10bit ADC T/τ = 20VDD – Vth = 2V VFS = 1V

• SFDR is very sensitive to sampling distortion

• Solutions:• Overdesignà Larger

switchesà increased switch

charge injection• Complementary switch• Maximize VDD/VFSà decreased dynamic range

• Constant VGS ? f(Vin)à …

EE247 Lecture 16 - University of California, Berkeleyee247/fa05/lectures/L16... · 2005-10-20 ·...

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