DRAM Tutorial Vivek Seshadri - ECE:Course Pageece447/s14/lib/exe/fetch.php?... · 2014. 4. 19. ·...

DRAM Tutorial

18-447 Lecture

Vivek Seshadri

Vivek Seshadri – Thesis Proposal

DRAM Module and Chip

• Cost

• Latency

• Bandwidth

• Parallelism

• Power

• Energy

DRAM Chip

Row Decoder

Array o

lifiers

ll Array

Row Decoder

Array o

lifiers

ll Array

Sense Amplifier

enable

bottom

Inverter

Sense Amplifier – Two Stable States

Logical “1” Logical “0”

Sense Amplifier Operation

VT > VB1

DRAM Cell – Capacitor

Empty State Fully Charged State

Logical “0” Logical “1”

Small – Cannot drive circuits

Reading destroys the state

Capacitor to Sense Amplifier

DRAM Cell Operation

VDD½VDD+δ

DRAM Subarray – Building Block for DRAM Chip

Cell Array

Array of Sense Amplifiers (Row Buffer) 8Kb

DRAM Bank

Array of Sense Amplifiers (8Kb)

Cell Array

Array of Sense Amplifiers

Cell Array

Bank I/O (64b)

AddressData

DRAM Chip

Row Decoder

Array o

plifie

ll Array

Row Decoder

Array o

plifie

ll Array

Row Decoder

Array o

plifie

ll Array

Row Decoder

Array o

plifie

ll Array

Row Decoder

Array o

f Sense

plifiers

Cell A

Row Decoder

Array o

f Sense

plifiers

Cell A

Row Decoder

Array o

f Sense

plifie

ll Array

Cell A

Row Decoder

Array o

f Sense

plifie

ll Array

Cell A

Row Decoder

Shared internal bus

Memory channel - 8bits

DRAM Operation

Array of Sense Amplifiers

Cell Array

Bank I/O

ACTIVATE Row

READ/WRITE Column

3 PRECHARGE

Column Address

RowCloneFast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization

Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu,

P. B. Gibbons, M. A. Kozuch, T. C. Mowry

Vivek Seshadri

Memory Channel – Bottleneck

Channel

Limited Bandwidth

High Energy

Goal: Reduce Memory Bandwidth Demand

Channel

Reduce unnecessary data movement

Bulk Data Copy and Initialization

Bulk Data Copy

Bulk Data Initialization

src dst

dstval

Bulk Data Copy and Initialization

Bulk Data Copy

Bulk Data Initialization

src dst

dstval

Bulk Copy and Initialization –Applications

Forking

Zero initialization(e.g., security)

VM CloningDeduplication

Checkpointing

Page Migration

Many more

Shortcomings of Existing Approach

MC Channelsrc

High latency(1046ns to copy 4KB)

Interference

High Energy(3600nJ to copy 4KB)

Our Approach: In-DRAM Copy with Low Cost

MC Channeldst

High latency

Interference

High Energy

RowClone: In-DRAM Copy

Two Key Observations

Any operation on one senseamplifier can be easilyperformed in bulk

Many DRAM cellsshare the samesense amplifier

Bulk Copy in DRAM – RowClone

VDD½VDD +δ

Data getscopied

Fast Parallel Mode – Benefits

Latency Energy

Bulk Data Copy (4KB across a module)

1046ns to 90ns 3600nJ to 40nJ

No bandwidth consumption

Very little changes to the DRAM chip

11X 74X

Fast Parallel Mode – Constraints

• Location constraint

– Source and destination in same subarray

• Size constraint

– Entire row gets copied (no partial copy)

Can still accelerate many existing primitives(copy-on-write, bulk zeroing)

Alternate mechanism to copy data across banks(pipelined serial mode – lower benefits than Fast Parallel)

End-to-end System Design

• Software interface

– memcpy and meminit instructions

• Managing cache coherence

– Use existing DMA support!

• Maximizing use of Fast Parallel Mode

– Smart OS page allocation

Applications Summary

bootup compile forkbench mcached mysql shell

Zero Copy Write Read

Results Summary

bootup compile forkbench mcached mysql shell

aselin

IPC Improvement Memory Energy Reduction

DRAM Tutorial Vivek Seshadri - ECE:Course Pageece447/s14/lib/exe/fetch.php?... · 2014. 4. 19. ·...

Documents

Transcript of DRAM Tutorial Vivek Seshadri - ECE:Course Pageece447/s14/lib/exe/fetch.php?... · 2014. 4. 19. ·...

memory - The College of Engineering at the University of …cs6710/slides/memoryx2.pdf2 Array-Structured Memory Input-Output (M bits) Row Decoder AK AK+1 AL-1 2L-K Column Decoder Bit

memoria Dram

Progress in Z2-FET 1T-DRAM: Retention time, writing modes ...Progress in Z2-FET 1T-DRAM: Retention time, writing modes, selective array operation, and dual bit storage Jing Wana, ,

HY425 Lecture 15: DRAM Technology - University of Cretehy425/2012f/lectures/lecture15...DRAM basics Advanced DRAM technology Virtual memory HY425 Lecture 15: DRAM Technology Dimitrios

DRAM Refresh

Computer Architecture: Main Memory (Part I)ece740/f13/lib/exe/fetch.php?media=se… · Page Mode DRAM A DRAM bank is a 2D array of cells: rows x columns A “DRAM row”is also called

VRL-DRAM: Improving DRAM Performance via Variable Refresh ... · VRL-DRAM: Improving DRAM Performance via Variable Refresh Latency Anup Das Drexel University Philadelphia, PA, USA

Fine-Grained DRAM: Energy-Efficient DRAM for Extreme ...niladrish.org/pubs/micro17.pdf · Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems Mike O’Connor∗†‡

Gather-Scatter DRAM: In-DRAM Address ranslationT …people.inf.ethz.ch/omutlu/pub/GSDRAM-gather-scatter-dram...Gather-Scatter DRAM: In-DRAM Address ranslationT to Improve the Spatial

DDR3 Synchronous DRAM Memory - … · DDR3 Synchronous DRAM Memory ... Read/Write leveling . DDR3 Synchronous DRAM 3 8-bit prefetch/burst length . DDR3 Synchronous DRAM 4 Commands

1 Multi-Core Systems CORE 0CORE 1CORE 2CORE 3 L2 CACHE L2 CACHE L2 CACHE L2 CACHE DRAM MEMORY CONTROLLER DRAM Bank 0 DRAM Bank 1 DRAM Bank 2 DRAM Bank.

A FLEXIBLE DECODER AND PERFORMANCE EVALUATION FOR ARRAY-STRUCTURED LDPC CODESspiral.ece.cmu.edu:8080/pub-spiral/pubfile/sungh_diss_108.pdf · unsuitable for practical applications

128Mb: x32 SDRAMDQM mask logic read data latch write drivers Column decoder Bank 0 memory array (4096 x 2048 x 4) Bank 0 row-address latch and decoder 4096 Sense amplifiers Bank control

DRAM Errors

Scalable Many-Core Memory Systems Topic 1: DRAM Basics …users.ece.cmu.edu/~omutlu/pub/onur-ACACES2013-Topic1-dram-basic… · Solution 1: Tolerate DRAM ! Overcome DRAM shortcomings

EE-382M VLSI–II Early Planning for Memory Array Designusers.ece.utexas.edu/~mcdermot/vlsi-2/Lecture_7.pdf · – Width of array is increased by the decoder • Decoder width is

MX25L4005, MX25L8005 - mct.net · · 2005-11-173 P/N: PM1130 REV. 0.04, MAY. 31, 2005 MX25L4005, MX25L8005 BLOCK DIAGRAM Address Generator Memory Array Page Buffer Y-Decoder X-Decoder

ProactiveDRAM: A DRAM-initiated Retention Management ......DRAM cell DRAM row sense amp DRAM bank subarray wordline bitline Fig. 2. DRAM internal bank architecture. banks. A rank can

TRRespass: Exploiting the Many Sides of Target Row Refresh · Inside a bank. A DRAM bank can be logically seen as a two-dimensional array of DRAM cells (Figure 2). Cells that share

DRAM capacity