Post on 09-Jan-2020
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Digital Logic and Design (Course Code: EE222)
Lecture 11: Combinational Logic Design
Indian Institute of Technology Jodhpur, Year 2018‐2019
Course Instructor: Shree PrakashTiwari
Email: sptiwari@iitj.ac.in
b h //h / /Webpage: http://home.iitj.ac.in/~sptiwari/
Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/DLD/
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Note: The information provided in the slides are taken form text books Digital Electronics (including Mano & Ciletti), and various other resources from internet, for teaching/academic use only
Design Concepts Combinational Logic Circuits
Outputs are functions of (present) inputs Outputs are functions of (present) inputs
No memory
Can be described using Boolean expressions
Hierarchical design
Used to solve large design problems
Break problem into smaller (sub-)problems
Solve each sub-problem (i.e. realize design)
Combine individual solutions2
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Design Concepts
Specification
Describes the problem to be solved.
Describes what needs to be done,
not how to do it.
Implementation Implementation
Describes how the problem is solved.
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Design Concepts Issues
M t l ti t i Most solutions are not unique.
More than one solution may meet the specifications
Cannot always satisfy all of the requirements.
Must identify (and study) design tradeoffs.
Cost Cost
Speed
Power consumption
etc.
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Design Process
• Identify requirements (i.e. circuit specifications)
• Determine the inputs and outputs.
• Derive the Truth Table
• Determine simplified Boolean expression(s)
• Implement solution
• Verify solution
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Logic Circuit Design
• Example:
• Design a combinational logic circuit that compares two 2-bit numbers, A (a1a0) and B (b1b0), and outputs a 1 when A > B.
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To implement the design, follow the 5 steps specified in the Design Process.
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Logic Circuit Design
• Example:
• Design a combinational logic circuit to convert between Binary Coded Decimal (input) and Excess-3 Code (output)
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Logic Circuit Design
1. Circuit Specification
• The combinational logic circuit must convert a code value in Binary Coded Decimal to its corresponding code value in Excess-3 Code.
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Logic Circuit Design
2. Determine Inputs and Outputs
• Input: Binary Coded Decimal value
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Binary Coded Decimal
Assign a 4-bit code to each decimal digit.g g
A 4-bit code can represent 16 values.
There are only 10 digits in the decimal number system.
Unassigned codes are not used.
How do we interpret these unused codes? How do we interpret these unused codes?
Hint: think about K-maps.
Remember “don't cares”?
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Binary Coded Decimal
Decimal Digit BCD Code
0 00000 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
12
7 0111
8 1000
9 1001
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Logic Circuit Design
2. Determine Inputs and Outputs
• Output: Excess-3 Code value
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Excess-3 Code
Decimal Digit Excess-3 Code
0 00110 0011
1 0100
2 0101
3 0110
4 0111
5 1000
6 1001
7 1010
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7 1010
8 1011
9 1100
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Logic Circuit Design
4. Determine simplified Boolean expression(s)
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Code Conversion
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Code Converter
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Logic Circuit Design
6. Verify Solution
• (Analyze, Simulate, or Test the Logic Circuit)
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Multiple-Output Logic Circuits
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Example:p
Given two functions, F1 and F2, of the same input variables x1.. x4, design the minimum-cost
implementation.
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Multiple-output Logic Circuit
x 1 x 2 x x
x 1 x 2 x xx 3 x 4 00 01 11 10
1 1
1 1
1 1
1 1
00
01
11
10
(a) Function
1
f 1
x 3 x 4 00 01 11 10
1 1
1 1
1 1 1
1 1
00
01
11
10
(b) Function f 2
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F1 = X1'.X3 + X1.X3' + X2.X3'.X4 F2 = X1'.X3 + X1.X3' + X2.X3.X4
Multiple-output Logic Circuit
x 2
x
f 1
f 2
x 3
x 4
x 1
x 3
x 1
x 3
x 2
x 3
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3
x 4
(c) Combined circuit for f 1 f 2 and
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Example:p
Given two functions, F3 and F4, of the same input variables x1.. x4, design the minimum-cost implementation for the combined circuit.
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Note: the minimum-cost implementation for the combined circuit may notbe the same as the minimum-cost implementations for the individual circuits.
Multiple-output Logic Circuitx 1 x 2
x 3 x 4 00 01 11 10
00
x 1 x 2 x 3 x 4 00 01 11 10
00
1
1 1
1
01
11
10
(a) Optimal realization of (b) Optimal realization of
1
f 3 f 4
1
1
1 1
1
1
01
11
10
1
1 1
F3 = X1'.X4 + X2.X4 + X1'.X2.X3 F4 = X2'.X4 + X1.X4 + X1'.X2.X3.X4'
Logic Gates required:2 2-input AND1 3 input AND
Logic Gates required:2 2-input AND1 4 input AND
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1 3-input AND1 3-input OR
1 4-input AND1 3-input OR
Total Gates and Inputs required:8 Logic Gates21 Inputs
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Multiple-output Logic Circuitx 1 x 2
x 3 x 4 00 01 11 10
1
00
01 11
x 1 x 2 x 3 x 4 00 01 11 10
1 1
00
01 1
(c) Optimal realization of f 3
1
1 1
1
01
11
10
1 1
1
1 1
1
1
01
11
10
1
1 1
and togetherf 4
F3 = X1'.X4 + X1.X2.X4 + X1'.X2.X3.X4' F4 = X2'.X4 + X1.X2.X4 + X1'.X2.X3.X4'
Logic Gates required:1 2-input AND1 3 i t AND
Logic Gates required:1 2-input AND1 3 i t AND
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1 3-input AND1 4-input AND1 3-input OR
1 3-input AND1 4-input AND1 3-input OR
Total Gates and Inputs required:6 Logic Gates17 Inputs
shared logic gates
Multiple-output Logic Circuit
x 1
f 3
f 4
x 1
x 4
x 3
x
x 1
x 2
x 2
x 4
x 4
x 2
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x 4
(d) Combined circuit for f 3 f 4 and
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The Half Adder
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Half AdderAdd two binary numbersA0 , B0 -> single bit inputs
S0 -> single bit sum
C tC1 -> carry out
C A B S 0 0 0 1 A 0 B 0
S 0
C 1
0 0 0 00 1 1 01 0 1 01 1 0 1
Dec Binary1 1
+1 +12 10
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Multiple-bit Addition
A3 A2 A1 A0 B3 B2 B1 B0
Consider single-bit adder for each bit position.
3 2 1 0
0 1 0 1A 0 1 1 13 2 1 0
B
0 1 0 1A111
Ai
+B
CiCi+1
0 1 1 1B
0011
+Bi
Si
Each bit position creates a sum and carry
Multiple-bit Addition
0 0 0 00 0 1 10 0 1 1
+ 0 + 1 + 0 + 10 1 1 10
1 1 1 10 0 1 1
+ 0 + 1 + 0 + 1
Carry-in
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Carry-out Sum
+ 0 + 1 + 0 + 11 10 10 11
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Full Adder
Full adder includes carry in Ci
Notice interesting pattern in Karnaugh map.
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 0
Ci Ai Bi Si Ci+1
1 1
1 1
Ci
AiBi00 01 11 10
0
1
1 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
Si
Now consider implementation of carry outMinimize circuit for carry out - Ci+1
AiBi
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 0
Ci Ai Bi Si Ci+1 Ci
i i00 01 11 10
0
1
1
1 11
Ci+11 0 1 0 11 1 0 0 11 1 1 1 1
i 1
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The Full Adder
Cin Cout
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The Full Adder
Cin
Cin
Cin
Cin
S Cout
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Cin Cin
S = X xor Y xor Cin
Cout = X.Y + X.Cin + Y.Cin
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The Full Adder
X
Y
Cin
S
Cout
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Full adder made of several half adders
Si = Ci (Ai Bi)
Ci+1 = AiBi + Ci(Ai Bi)
A
B
S
C
i
i
i
i
C i+1
Half-adder Half-adder