Development of CMOS CSA for Point Contact HPGe Detectors

Zhi Deng for HPGe detector group @ 

Department of Engineering Physics, Tsinghua University

Application of Germanium Detector in Fundamental ResearchBeijing, March 23‐29, 2011

Outlines

• Introduction

• CMOS CSA Design– Noise Optimization

– Reset

• Test Results

• Summary & Future Plan

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Introduction

• ULE HPGe Detector

2011/03/25 Application of Germanium Detector in Fundamental Research

The key technologies for lowering the energy threshold is using small capacitance detector and ultra low noise readout

Point-contact HPGe, ~1pF

3

• JFET vs. CMOS for small capacitance detectors

Application of Germanium Detector in Fundamental Research2011/03/25

C C C

ENCa e C

a K C a i

tot in

nw totF tot n

= +

= + +

det

2 12 2

22

32

ττ

tm, ns

As the detector capacitance goes down, the contribution from 1/f noise become non-dominant anymore!

4

• What is the limit for 1/f noise

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e.g., Kf = 10-25J, Cd=1pF ENCf ~ 5 e-

( )222

, 2

ff d g

g

f opt f d

KENC a C C

C

ENC K C

π

π

= + →

≈Borrowed from Paul O’Connor’s talk in FEE2006

Why not CMOS then?

CMOS CSA Design

• Noise Optimization

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PMOS for lower 1/f noise, with optimized size Adjustable bias current

for noise study

Pulse reset for dischargingSee the next slide

• Reset

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Pulse Reset 1 Pulse Reset 2

On Chip Off Chip

Charge Injector with opposite polarity

• Layout and test board

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250μm

200μ

m

Test Results

• Test Setup 

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Shaper

Signal Generator

Oscilloscope

Vacuum chamber

Power Supply

BumpTemperature sensor

• Injected with test signals

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Rise time is about 30ns for 1.5m long cable

After shaper

2011/03/25 Application of Germanium Detector in Fundamental Research

0 2 4 6 8 10 120

5

10

15

20

25

30

Shaping Time [μS]

ENC

[e]

T=25oCT=18oCT=10oCT=0oCT=-10oCT=-20oCT=-30oCT=-45oCT=-60oCSys@T=25oCSys @ T=-60oC

6.5e

11

• ENC

Summary & Future Plan

• A CMOS charge sensitive preamplifier has been designed for point‐contact HPGe detectors, with noise optimized for 1pF capacitance. Sub‐10e ENC has been achieved without detector. Testing with detector is undergoing.

• A second version chip has been designed and fabricated and it will also be evaluated soon.

• More deep study on cryogenic CMOS transistor model, long term stability…

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Thanks

The test setup has been done for the first prototype ASIC with the first prototype of point contact HPGe detector