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Design Flows for the Microelectronics Industry
The term microelectronics describes the group of technologies used to integrate multiple devicesinto a small physical area such as a microchip used in computers or mobiles. Every examplespans several technologies, each with their own goals and challenges. The microelectronicsindustry is dynamic and rapidly changing. Design flows (the rigorous engineering methods usedfor quality assurance) must evolve just as rapidly to embrace new technological advancement.
Despite the small physical size of the systems in microelectronics, complexity can be very high.In order to accommodate this engineering methods have developed that allow details to behidden, or abstracted to lower levels of the design process. This allowed larger systems to becreated with building blocks, which are small systems themselves.
Analysing the phases involved in the design process is the first step in understanding thechallenges facing the microelectronics industry in Australia. The rising demand for smallersmarter chips has the knock-on effect of increasing levels of design integration, and the level ofdesign automation must also increase to manage the inherent complexity. The use of ElectronicDesign Automation (EDA) tools are an integral part of implementing design flows, but its influencevaries across sectors of the industry.
These are the various design flows or sectors, with a brief explanation and the key issuesinvolved with each.
1. Field Programmable Gate Array (FPGA) Design Flow
A FPGA is an array of regular logic blocks, which may be configured to operate within a particularlogical function. Digital logic functions can be synthesized onto the logic blocks of the FPGA andit is then programmed with the configuration information to perform that function. FPGA devicesare economical at small volumes because the non-repetitive engineering (NRE) costs are lowerthan with an Application Specific Integrated Circuit (ASIC). (As production volumes rise, thelonger-term cost efficiency of ASIC outweighs the increased NRE to make customimplementation viable.) FPGAs can also offer a time to market advantage, as the device can beprogrammed and tested after the design phase more quickly than an ASIC takes to synthesise.Design modification and re-programming costs are also low compared to re-fabrication.
Design tool costs for FPGA development are traditionally lower than for ASICs, making FPGAs aviable training and prototyping vehicle and opening the FPGA market to smaller organizationsFPGA part vendors have traditionally provided FPGA design software. However, advances infabrication technology have seen an explosion in FPGA logic capacity, and this has moved thecomplexity beyond software provided by FPGA tool vendors. ASIC tool vendors have nowmoved into the market place to provide very high quality front-end tools to the FPGA market at areduced cost.
With front-end procedures being similar to digital ASIC and System on Chip development, FPGAsare a low cost proof of concept or training tool. EDA tools are also more financially accessible to
small organizations and educational facilities.
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User Constraints File
Test Bench
Synthesis Libraries
Timing Constraints
Module Generator/Library
Specification
Simulation/Timing
RTL
Synthesis
Gate Level Simulation
FPGA Place & Route
Simulation/Timing
Post Layout
Bit JEDEC file
System Level Modeling
Architectural Exploration
RTL Description
MeetSpecification?
Yes
No
FPGA Design Flow
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Place & Route
Floorplan
Scan Chain Reordering
Pass?
Yes
No
Physical Rules
Pass?
Yes
No
Fault Simulation
ATPG
Test Vectors
Test Bench
Simulation Library
Synthesis Libraries
Module Generator/Library
Physical Constraints
Timing Libraries
Physical Libraries
Scan/BIST configuration
Constraints
Specification
RTL description
Initial Floorplan
Simulation/Timing
Logic Synthesis &
Scan Insertion
Power Analysis
Clock Tree Synthesis
forw
a
rd-a
nn
otati
on
ba
ck
-an
no
tati
on
RC Extraction
Gate Level Simulation
Timing Verification
Post-Layout Verification
(LvS, DRC, ERC)
Tape Out
System Level Modeling
Architectural Exploration
2. Digital Application Specific Integrated Circuits (ASIC) Design Flow
Timing driven design flow for digital ASIC
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Digital Application Specific Integrated Circuits (ASIC) Design Flow (continued)
ASIC developments in digital CMOS (complimentary metal oxide semiconductor) technologiesare the most common microelectronics pursuit. They are suited to medium to high levels ofproduction where NRE costs may be recouped by production cost savings due to lowercomponent counts or lower per part costs.
A timing driven design flow (TDD) is suitable for fabrication technologies of 0.25 micron andabove. The Register Transfer Language (RTL) is synthesised to a symbolic implementation interms of logic gates and a netlist, which is then implemented with a separate physical place androute stage. The separation of these activities means that estimates of wire delays need to besupplied to the synthesis tool. Satisfying timing constraints becomes more difficult if thismethodology is employed for finer line, deep sub-micron technologies.
A deep sub-micron (DSM) design flow addresses a number of physical effects that arise as thefabrication technology moves below 0.18 micron. Signal integrity becomes the central issuebecause the inter-line capacitance (that is wire to wire) becomes more dominant than the line tosubstrate capacitance, causing cross talk and interference between signals. At the same time thefine line technology produces narrower wires, which are more resistive, and the drive strength ofthe transistors in the logic gates is reduced as less transistor area is used. The net result is that
interconnect can no longer be considered as ideal and the signal propagation delay due tointerconnect can be more significant than the gate delay.
Design complexities rise as larger, more complex systems can be integrated into fine linetechnologies. This complexity has a large impact on design testability and practices that Designfor Test (DFT) must be employed. Demands for faster clock speeds and lower power pushdesign techniques to the limit of the time.
(see over for deep sub-micron digital design flow)
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Physical Rules
Pass?
Yes
No
Pass?
Yes
No
Fault Simulation
ATPG
Module Generator/Library
Timing Constraints
Area Constraints
Power Constraints
Scan/BIST configuration
Synthesis LibrariesPhysical Constraints
Floorplan
Scan Insertion
Placed-Gate Synthesis
Clock Tree Synthesis
Power Analysis
Detailed Route
Scan Chain Connections
RC Extraction
Synthesis:
Test Vectors
Simulation Library
Test Bench
Simulation/Timing
RTL Description
Initial Floorplanning
Specification
Post-Layout Verification
(LvS, DRC, ERC)
Tape Out
back-annotation
Timing Verification
Architectural Exploration
System Level Modeling
Deep Sub-Micron Digital Design
Flow
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3. Analog Integrated Circuit (Analog IC) Design Flow
An analog design flow can be broken into two parts; one for large analog systems where analogmodules are assembled, and another for generation of the individual analog modules. Issuessuch as reduced noise immunity, a greater dependence on device matching and processvariation means that most analog implementations require manual design (no synthesis) andmanual layout. With less automation available, analog design practises turn to hierarchymanagement and modular design practices to cope with increasing complexity.
The physical implementation affects circuit performance to a far greater extent than in digitalcircuits. Consequently, synthesis of analog circuits has not progressed very far and analogimplementations are substantially manual pursuits.
Process variation in manufacture can impact heavily on performance and yield. Circuit designneeds to use process tolerant topologies and process variation needs to be allowed for duringsimulation. Design portability (between fabrication facilities) is reduced for the same reason.
Design Rules
Test Bench
Cell Library
Cell Models
Test Bench
Cell models
Specification
Physical Verification
RC Extraction
MeetSpecification
Yes
No
Post-LayoutAMS Simulation
Tape Out
Module SpecificationAMS Simulation
System level Modeling
Floorplan
Analog System Development
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Design Rules
Test Bench
Simulation models
Test Bench
Simulation models
Schematic Capture
Topology Selection
Layout
Design Simulation
Physical Verification
RC Extraction
Post-Layout Simulation
MeetSpecification
Yes
No
Callibrated AMS Model
ModuleSpecification
Analog Module Development
4. Mixed Signal Integrated Circuit (Mixed Signal IC) Design Flow
A Mixed Signal IC is appropriate for small and medium sized chips (
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Test Vectors
Test Bench
Constraints
Scan/BIST configuration
Synthesis Library
Simulation Library
Cell Library
Physical Constraints
Test Bench
Test Vectors
Timing Information
Timing Estimates
Implementation Netlist
Logic Synthesis
with test insertion
Floorplan
and simulationRTL description
Specification
Detailed Route
Layout Database
Physical Verification
(LvS, DRC, ERC)Pass?
No
Yes
Scan path reordering
Clock Tree synthesis
Architectural Exploration
Schematic Capture
Topology Selection
Layout
Design Simulation
Physical Verification
RC Extraction
Post-Layout Simulation
AMS description
Gate level & AMSAMS Models
Timing Estimates
Timing Verification
Formal Verification
Placement
RC Delay estimation
Simulation
Analog / Digital Partitioning
System level modelling
Calibrated AMS Models
Mixed Signal Design Flow
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5. Radio Frequency Integrated Circuit (RFIC) Design Flow
RFIC design covers the development of integrated wireless communication and signal processingdevices. Typical RFIC design involves a high frequency RF front end, and a lower frequencyback end responsible for modulation or decoding of a signal. However, RF developments rangefrom predominantly digital systems with an RF front end, to those almost entirely analog RFdesigns in the case of Microwave Monolithic Integrated Circuits. (When systems becomeparticularly large or contain multiple technology domains the term RF SoC may be applied.)
RFIC design often requires a considerable amount of signal processing. Algorithm design at thesystem level is critical to achieving noise immunity and high system performance. RF systemsoften merge digital signal processing and analog RF techniques in the one system. Futuredevelopments will call for MicroElectro Mechanical Systems devices, further broadening the skilbase required for development.
System-level design and verification is required. Packaging and loading effects need to beconsidered through the whole design cycle to ensure that system performance targets are met.
Significant complexity is introduced by the high frequency of operation. Specialised simulatorsand analysis methods have been developed for RF design. Sections of an RF system thaoperate at high frequency or have an analog nature have a high reliance on the physica
implementation. They may also be sensitive to process variation and require considerable efforto optimise for a new fabrication process.
Design Rules
Test Bench
Cell Library
Test Bench
Behavioural Models
Behavioural models
Specification
Algorithm Design
Physical Verification
RC Extraction
Post-Layout
Floorplan
RF Simulation
verification / RF SimulationSystem Behavioural
Architecture explorationSystem partitioning
RF IC Design Flow
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Design Rules
Test Bench
Simulation models
Test Bench
Simulation models
Schematic Capture
Topology Selection
Layout
Design Simulation
Physical Verification
RC Extraction
Post-Layout Simulation
MeetSpecification
Yes
No
ModuleSpecification
Calibrated Behavioural
model
RF Module Design Flow
6. Microwave Monolithic Integrated Circuit (MMIC) Design Flow
MMIC development is a form of RFIC development that tends to occupy the high frequency endof the spectrum. In general MMIC circuits are low density (10s of transistors) and tend to operateat a higher frequency (1GHz and above). At the lower frequency range MMIC devices can befabricated in standard silicon technologies, while higher performance can be obtained by movingto SiGe, GaInP or GaAs processes.
The high frequency range of MMIC devices introduces significant complexity. Microwave design
principles are required and transmission line structures are often employed for interconnectSpecialised simulators and analysis methods have been developed for RF design, their useimportant to model transmission line and distributed effects within the circuit. Electromagneticsimulators may also be used to analyse the physical structure of particularly complex circuits.
Considerable Intellectual Property is contained in RF device models. These may not always beavailable from the fabrication facility and may require significant development resources.
Sections of an RF system that operate at high frequency or have an analog nature have a highreliance on the physical implementation. They may also be sensitive to process variation andrequire considerable effort to optimise for a new fabrication process. Prototype runs and design
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iteration are an accepted part of the design flow for MMIC and high frequency analogimplementations. As simulation and RF modelling techniques mature, the need for this mayreduce.
Design Rules
Package model
System loading
System loading
Package model
Device models
Layout
Design Simulation
Physical Verification
RC Extraction
Post-Layout Simulation
Specification
Schematic CaptureTopology Selection
Prototype Fabricationand packaging
Device Testing
Device models
MeetSpecification
Yes
No
Device production
MMIC Design Flow
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7. System on Chip (SoC) Design Flow
SoC development is distinguished from traditional integrated development by the markedincrease in system complexity and the integration of several technology domains. For exampleSoC designs will incorporate traditional digital systems like microprocessors (once a chip in theirown right) with embedded memory and RF analog devices. In the future MicroElectro MechanicaSystems, Optical Systems and Electro-Biological Systems will find their way into SoC designs.
SoC development falls into two main categories:
Cost based SoC (C-SoC) is characterized by large volume production directed at theconsumer electronics market. Systems are integrated on chip to reduce manufacturingcosts and power consumption for hand held devices. Device packaging tends to be asinexpensive as possible and pin counts are reduced to assist this. A major emphasis forC-SoC is the reduction of engineering development times to reduce time to market andextend a products life in an environment of decreasing product life cycles.
Performance based SoC (P-SoC) is characterized by smaller volumes of highperformance, high value products. SoC is employed in these applications as the onlymeans available to meet project specifications (such as high speed or low power). P-SoCoccurs at or near the upper technological limits of the time. Military and aerospace
applications are classic candidates for P-SoC.
SoC developments occur in deep sub-micron technology, therefore key issues affecting deepsub-micron affect SoC, including signal integrity and need for physical synthesis and system levelplanning to meet timing constraints. As system complexity is rising exponentially, designpractices need to integrate design for test (DFT) and design for verification (DFV). Verification ofmodern deep sub-micron projects consumes up to 70% of development time. Unless designtechniques embrace testing and verification from system level, time to market of SoC devices willblow out to unsustainable levels.
Effective reuse of previous designs and Intellectual Property (IP) is critical to building complexsystems while reducing time to market. To achieve this, standards for IP development must be
developed to ensure integration and verification can occur in a timely fashion. Robuststandardised interface and bus models are vital to avoid significant re-work of IP in order tointegrate it. The reuse of general purpose, programmable cores (like microprocessors) shiftsfunctionality from the hardware to the software domain. As software content increases, its designcomplexity rises rapidly and software verification becomes an important issue, thus SoC designflows must allow for hardware/software co-design and co-verification at all levels of the designprocess.
Integration of multiple technologies on a single chip introduces new range of design challengesSoC developments already incorporate embedded memories. The International TechnologyRoad-map for Semiconductors (ITRS) predicts emergence of FPGA technology in SoCs in 2001MEMS, FRAM and Chemical sensors in 2002, electro-optical devices in 2004 and electro-biological in 2006.
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IP Core models
Cell Library
IP Core layout / box
Test Bench
IP Core models
Cell models
Design Rules
Timing/Power Constraints
Scan / BIST etc
Design Rules
Test Bench
Test Bench
IP Core models
Specification
System levelalgorithm development
Architecture explorationSystem level
Timing Verification
Physical Verification
HDL Design entryand simulation
Tape Out
Block based Floorplan
Synthesis
SoC Block Based Developmentis evolving from digital ASIC methodologies like Timing DrivenDesign (TDD). This diagram shows an abbreviated TDD flow evolving into a physical synthesisstage, removing the need for iterations in the design flow.
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Test Bench
Virtual Component library
Test Bench
Design Rules
Timing/Power Constraints
Scan / BIST etc
Design Rules
Virtual Components
Virtual component models
Specification
System levelalgorithm development
Architecture explorationSystem level
Tape Out
Virtual component
functional verificationPhysical Verification
Floorplan
Synthesis
SoC Platform Based Development (PBD)
8. Bipolar Process
Bipolar integrated circuits provide some specialised features that have seen them in use over a
very long period. The power rating of the devices is one of most important properties, and theyhave wide spread applications in power and automotive electronics. Their power sinkingcapability also makes them more immune to switching spikes and inductive fly back than CMOStechnology. This has seen bipolar technology take up an important role as an interface betweensensitive CMOS circuitry and harsh high voltage or mechanical environments
The bipolar process is predominantly an analog design process. Technology provides medium-scale integration and integration of traditional passive components. High currents can producethermal effects, which must be carefully modelled. The level of integration and feature sizeallows prototype designs to be internally probed and tested effectively.
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Physical Constraints
Prototype
Simulation Models
Design Rules(LvS, DRC)
Floorplan
Layout
Simulation
Physical Verification
Schematic Capture
System Level Modelling
System Tests
Pass?
Specification
No
Yes
NoMeet
Specification?
Final Circuit for
Production
Yes
Bipolar System Development
9. MicroElectro Mechanical Systems (MEMS) Design FlowMEMS are small electrical/mechanical devices utilised for their functionality in electrical systemsas sensors and switches. MEMS applications range from on-chip RF components, as antennastructures, to micro-mirrors in optical systems. Current examples of MEMS technology are foundin devices like inkjet-printer heads, and accelerometers for the deployment of car airbags. Thewidespread application possibilities give massive growth potential to development of thetechnology and its market
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MEMS devices are primarily a mechanical structure, but a variety of physical domains impact ontheir behaviour. The mechanical, electrostatic, electromagnetic, thermal and fluidic domains alrequire consideration and simulation at differing levels of accuracy.
Electrical models are often used as an analysis technique to leverage off more advancedelectrical design tools, but this technique requires careful interpretation on designers behalf.
The match between simulation results and device performance is poor by other microelectronicsstandards. Prototype and design iteration is an accepted reality.
Process definition
Stimulus / test bench
Environment (package)
Specification
Schematic Entry &2D Mask layout
Physical Verification(LvS + limited DRC)
No
Yes
Device for
analysis & modelling
3D Visualization
Simulate FEA modelSimulate electrical analog
Production
Specification?Meet
Device Tests
Fabrication & Packaging
Finite element
MEMS Design Flow
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10. Integrated Optoelectronic Devices (Opto)
These devices range from laser/light sources, detectors, modulation devices, amplifiers,multiplexers and demultiplexers. A large area for these chip-integrated optical systems is in thecommunications industry, for applications such as switching devices and connectors.
The design flow for opto-electronic devices is concentrated on the physical characteristics ofstructures. Complexity lies in developing and modelling the physical structures to produce therequired function rather than in sheer system size. Wavelength of operation is in the order of amicron and below, so packaging must be included as an integral part of the design. Differingmaterial systems are used for various functional groups, but the design process used is similar.
Fabrication techniques are still maturing and manufacturing limits are currently a major factor inperformance and functionality.
2D Cross-Section
Design Rules
Mask Exports
Prototype Device Tests
Meet
Specification?
Production
Specification
(LvS, DRC, ?)
Physical Verification
Simulation
Pass?No
No
Yes
Yes
Device for
Package Design
Integration &
Floorplan & 3-D Layout
2-D Physical
Characteristic Modelling
Optoelectronic Device Development