Post on 17-Mar-2020
Design and Test Solutionsfor Networks-on-Chip
Jin-Ho AhnHoseo University
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Topics
• Introduction• NoC Basics• NoC-Related Research Topics • NoC Design Procedure• Case Studies of Real Applications• NoC-Based SoC Testing Issues• Conclusions
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SoC: Core of Digital Convergence
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SoC Components
• Processing unit• On-chip memory• H/W accelerator• I/O device controllers
(peripherals)• Interconnection structure
S3C2510(Samsung)
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Future SoCs
• In 45 nm, up to 10x on a single chipPhilips Viper2
130 nm 50M trans.1 MIPS 2 Trimedia
60 IP blocks 250 RAMs
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On-Chip Interconnect Evolution
ASB
core core core core
core core core core
Shared Bus
core core
Bridge corecore core
Hierarchy or Bridged Bus
core core core core
core core core core
Direct/Indirect network
Network Based
AHBAXI
AHBML
(Example) AMBA Case
??
– Complexity– Scalability– Predictability
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Wire Design in Sub-100 nm Tech.
•65nm low-power library•very high frequencies or very long links infeasible
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Networks-on-Chip• NoC (Networks-on-Chip)
– An evolution of on-chip bus interconnect technology– Interconnection model implemented on a chip in the form of a
micro-network
• Borrow models, techniques, and tools from the computer network design field and apply them to SoC design
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NoC Pros and Cons
• Pros– Canonical interconnect
structure– Shared interconnect
bandwidth– Increased flexibility
• Cons– Intra-PE interconnect delay– Overhead due to
interconnects
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NoC TopologyR
Mesh
R R R
R R R R
R R R R
R R R R
Butterfly Fat-Tree
R
RR
R
RR
Octagon
R RR
R
RR
R
R
Core
Router
R R
R R
R
R
R
R
R
R
R
R R
R R
R
R
R
R
R
R
H-Tree
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NoC-Based SoC
• Typical applications– Complex– Highly heterogeneous (component specialization)– Communication intensive
• Tailor-made interconnects for applications• NoCs are resource constrained:
– Power, area constraints – low buffering available• Large available wire bandwidth
– But tapping it with modular, structured design is key
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Design Space for NoC-Based SoC
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Category of NoC Platform
• Hard NoC– NoC and IP positions are fixed
• Firm NoC– NoC is pre-designed, but IP positions can
be changed • Soft NoC
– NoC components and IP positions can be changed
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Topology Synthesis
• From multi-computer networks
• Designed for general-purpose and homogenous systems
Regular-Topology NoC
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Topology Synthesis• Application-Specific NoC• Customized NoC for
each application– ASNoC brings significant
performance improvements
• For both homogenous and heterogeneous systems
Irregular-Topology NoC
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Regular-Topology NoC Synthesis
• Example: XPipe
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Other NoC Synthesis
• Irregular and hybrid-Topology NoC– can produce optimal topology at a given application – difficult to develop EDA tools – heuristic approaches are required
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Design of NoC Components
• Router– Network Interface– Switching fabric– Buffering scheme– Flow control– Arbitration
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Design Issues of NoC Components
• NoC channel width• NoC channel structure
– (Ex) Serial and Parallel• NoC router buffer size
– Buffer is critical to decide the overall NoC size– Needs an efficient traffic modeling
• NoC floorplaning– maximize the performance and reduce coupling
effect
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NoC Communication Protocol
• Major objective function– minimal routing path – congestion avoidance – deadlock or livelock– uniform power consumption – fault tolerant
ApplicationLayer
NetworkLayer
PhysicalLayer
Router
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Criterion for NoC Routing Policy
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General NoC Design FlowSystem Level Modeling
NoC Model
NoC Parameters
Performance and PowerEstimation
Mapping and Scheduling
Application Model
Design Objective
Objective is satisfied ?N Y
RTL Generation
HW/SW Co-Sim.
Verified?
Synthesis andFormal Verification
Verified?
Emulation andLayout
Verified?
To Fab.
N
Y
Y
N
N
Y
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NoC Scheduling and Mapping
NoC Characteristics
Task Scheduling
Task and PE mapping to NoC Model
TargetObjective Feasible ?
Application Model
Satisfied ?
NoC Model • Application mapping– Assign embedded cores
to the given NoC model
• Key of the overall performance
• For simplification, mapping and scheduling process are separated
• Mapping constraints– avg. hop number– power consumption– etc...
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Re-mapping for Flexible NoC
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SunFloor NoC Design Flow
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Æthereal NoCDesign Flow
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NoC Research Projects
• Nostrum at KTH• Æthereal at Philips• Proteo at Tampere University of Technology• SPIN at UPMC/LIP6 in Paris• XPipes at Bologna and Stanford Univ.• Octagon at ST and UC San Diego• SoCIN at UNIVALI and UFRGS• CHAIN at the Univ. of Manchester• MANGO at the Tech. Univ. of Denmark
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Case Studies of Real Applications
• H.264 HDTV decoder system-on-chip• High-end consumer-electronics TV system-on-chip• KAIST Bone series
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H.264 HDTV Decoder SoC• Candidate for HDTV broadcast• High compression rate: 2X of MPEG2• High definition: 2 million pixel/frame
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H.264 HDTV Decoder SoC• ASNoC has two local networks• RAW is implemented based on its design documentation• Positions of computation nodes are optimized• The same group of computation nodes• Different communication architectures• ASNoC has less switches and links
ASNoCRAW
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H.264 HDTV Decoder SoC
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High-End Consumer-ElectronicsTV SoC• The main TV chip, companion chip, and external
memories.
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High-End Consumer-ElectronicsTV SoC
• Architecture of companion chip with NoC
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High-End Consumer-ElectronicsTV SoC
• 100MHz in a 0.13um tech.• IP: 100MHz, NoC: 300MHz(1.2Gbit/sec)• Area overhead: 4%• Power overhead: 12%• Latency overhead : 10%• Simulation overhead : 15 ~ 60%• Design time: 12 months by 2 designers
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KAIST BONE Series• BONE(Basic On-Chip Networks) Project
– launched in 2002 at KAIST– covers circuit-level design, architectural researches and system
integration on an NoC platform (http://ssl.kaist.ac.kr/ocn/)
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NoC-Based SoC Testing Issues
under investigation(standard-compliant wrapper design)
Wrapper Design
NoC reuseTAM Design
under investigation(mainly related to integrated test
scheduling)Test Strategy
NoC reuseTAM Design
standardized wrapper definition Wrapper Design
Functional Core Testing
Test Strategy
Category
open problemIntegrated System Testing
under investigation(related to testing with multiple identical
cores or distributed BIST scheme for multiple FIFOs)
NoCCommunication Fabric Testing
StatusIssue
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Generic Procedure
NI NI NI NI NI
P MP P M
R R R
R RNI
NI NI NI
M P M
NI NI NI NI NI
P MP P M
R R R
R RNI
NI NI NI
M P M
NoC Testing Core Testing
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NoC Testing
• Testing target– router(=switch) blocks– comm. wire segments
• Fault model– comm. link: max. aggressor fault(MAF)– switch
• routing logic: SAF• routing FIFO: 2-port memory
– mem. cell array: SAF, TF, DRF, BF– addressing fault: SAF– other functionality faults
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Packet-Based Test Data Transport
• Unicast mode• Multicasting mode• Broadcasting mode
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Problems of Data Transport
• Unicast mode– High latency, Long test time
• Multicasting mode– High traffic load, High power consumption
• Broadcasting mode– High traffic load, High power consumption– Needs a list of all sending packets to avoid loops
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NoC Router Testing• Routing logic
– small F/F and gates: full-scan– uses multiple identical core testing approaches
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NoC Router Testing• Routing buffer
– main problem for the router testability– normal BIST is not suitable: small buffers are spread over NoC– NoC buffer: 2-port memory type
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NoC Wrapper Design
• IEEE 1500 standard wrapper assumes that– TAM wires connected to a core can be assigned individually– wrapper control signals can be controlled individually by an
external ATE
• Thus, standard wrapper is unsuitable for NoC test reusing NoC as TAM
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NoC Wrapper Example (1)
A single test wrapper for the whole NoC
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NoC Wrapper Example (2)
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Conclusions• Present
– Interconnect now dominates the design process– Interconnect-aware design methodologies are needed
• NoC era is coming– NoC is here and important for on-chip global data transfer
• Designing NoCs– Huge design space– Demonstrate good potential
• Application-specific networks can pay off in performance/energy– But, take more time to design
• Efficient NoC-based SoC test is important in real cases– NoC-based TAM is a prerequisite