Dense-Near/Sparse-Far Hybrid Reconfigurable Neural Network Chip

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Dense-Near/Sparse-Far Hybrid Reconfigurable Neural Network Chip. Robin Emery Alex Yakovlev Graeme Chester. Overview. Motivation System Elements & Structure Current Work Future Work. Previous Work. Artificial neural network Xilinx Virtex-II FPGA Variable precision - PowerPoint PPT Presentation

Transcript of Dense-Near/Sparse-Far Hybrid Reconfigurable Neural Network Chip

Dense-Near/Sparse-FarHybrid ReconfigurableNeural Network Chip

Robin EmeryAlex Yakovlev

Graeme Chester

Overview

• Motivation• System Elements & Structure• Current Work• Future Work

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Previous Work

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• Artificial neural network• Xilinx Virtex-II FPGA• Variable precision• Generated using mark-up• Controlled via PC

Threshold

Sum

FireLatch

WeightTable

DecayModule

ExternalStimulus

ReservedFor Decay

FiredInputs

Previous Work

• Exhausted area before routing resource

• Synchronous, Low neuron count• No autonomous learning• FPGA routing

resources occupy70-90%

• Real-time learningawkward

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A Neuron

A Network of Neurons

• Billions of neurons in the brain• 100 to 3000 connections per neuron• Majority of connections are proximal• Spikes are generally the same

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Clusters

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• Axons of neocortical neurons form connections in clusters

Learning

• In the synapse• Plastic connection• Use learning rule• Autonomous in

synapse• Wider mechanism may

exist

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Motivation

• A FPGA-like neural network device would be of interest to neuroscience

• Connectivity is also of interest• Observations support a hybrid of

local and distal connectivity• More useful with real-time learning

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System Elements

• Neuron• Synapse• AER Router• AER/Spike Bridge• Routing Resource• Protocol

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AER

• Address Event Representation• Asynchronous digital multiplexing• Stereotyped digital amplitude events• Nodes share frame of reference• Information is encoded in the time

and number of events

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Dense-Near Connectivity

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Sparse-Far Connectivity

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Network Structure

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Current Work

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• Neuron– Configurable threshold– Asynchronous– 7-bit count– Decay– Spike generator

Current Work

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• Neuron & Spike Generator• 130nm UMC CMOS

Area 1145.6μm2 (90nm: 700μm2)

Gates 390

Density 873 p. mm2 (90nm: 1429 p. mm2)

Spike Period 4.5ns

Generated Clock Frequency

160MHz

Max. Spike Rate (theshold=100)

2.35 million p. second

Current Work

• Software model & protocol refinement

• Ongoing work:– Autonomous Synapses– AER Router/Bridges

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Evaluation

• Topographic map• Compare to popular software

modelling tool such as NEURON

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Future Work

• Long-term learning process• Improve capacity of AER link by

grouping spikes• Aggregation of pulse-widths could

improve range of dendritic input• Multiplexing of some direct links

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Conclusions

• Reconfigurable, adaptive neural network system

• Real qualities of interest to neuroscientists

• Neuron and spike generator manufactured

• Interesting avenues for further work

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Thank you

r.a.emery@ncl.ac.uk