Post on 12-Feb-2018
Custom Single Purpose Processor Design
Dr. Shubhajit Roy Chowdhury,
Centre for VLSI and Embedded Systems Technology,
IIIT Hyderabad, India
Email: src.vlsi@iiit.ac.in
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
The Design Process
We ask ourselves the question:
What is electronic Design?
Given specifications, we want to develop a
circuit by connecting known devices such that circuit by connecting known devices such that
the given specifications are met.
“Specifications” refer to the description of the
(desired) behavior of the circuit.
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
Electronic Design
So electronic design is the process of
converting a behavioral description (what
happens when …) to a structural description
(what is connected to what etc.)(what is connected to what etc.)
Apart from structural design, we need to do
physical design, which involves choosing
device sizes, placement, routing interconnects
etc.
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
General Purpose versus Single Purpose
Processors in Electronic Design• Processor
– Digital circuit that performs a computation tasks
– Controller and datapath
– General-purpose: variety of computation tasks
– Single-purpose: one particular computation task
CCD
preprocessor
Pixel coprocessorA2D
D2A
Digital camera chip
CCD
computation task
– Custom single-purpose: non-standard task
• A custom single-purpose processor may be– Fast, small, low power
– But, high NRE, longer time-to-market, less flexible
MicrocontrollerJPEG codec
DMA controller
Memory controller ISA bus interface UART LCD ctrl
Display
ctrl
Multiplier/Accum
lens
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
Custom single-purpose processor basic model
controller datapath
…
external
control
inputs…
external
data
inputs
datapath
control
inputs
… …
controller datapath
next-state
and
control
logic
registers
controller and datapath
…
external
control
outputs
…
external
data
outputs
datapath
control
outputs
a view inside the controller and datapath
… …
state
register
logic
functional
units
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
Example: greatest common divisor
GCD
(a) black-box
view
x_i y_i
d_o
go_i
(b) desired functionality
1:
1
!1
x = x_i3:
y = y_i4:
2:
2-J:
!go_i
!(!go_i)
(c) state
diagram• First create algorithm
• Convert algorithm to
“complex” state machine
– Known as FSMD: finite-
state machine with
0: int x, y;
1: while (1) {
2: while (!go_i);
3: x = x_i;
4: y = y_i;
5: while (x != y) {
6: if (x < y)
7: y = y - x;
else
8: x = x - y;
}
9: d_o = x;
}
(b) desired functionality
y = y -x7: x = x - y8:
6-J:
x!=y
5:!(x!=y)
x<y !(x<y)
6:
5-J:
d_o = x
1-J:
9:
state machine with
datapath
– Can use templates to
perform such conversion
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
State diagram templates
Assignment statement
a = b
next
statement
Loop statement
while (cond) {
loop-body-
statements
}
next statement
Branch statementif (c1)
c1 stmts
else if c2
c2 stmts
else
other stmts
next statement
7
a = b
next
statement
loop-body-
statement
s
cond
next
statement
!cond
J:
C:
next statement
c1
c2 stmts
!c1*c2 !c1*!c2
next
statement
othersc1 stmts
J:
C:
A typical Digital Hardware design flowRequirements
Behavioral Model
RTL Model
Logic Level
Functional SimulationTiming, Area,
Power
VHDL/Verilog
Gate Level Netlist
RTL Simulation
Timing, Power and
Synthesis Verify
Logic Level
Floorplanning
Place and Route
Chip Fabrication
Gate Level Netlist
Chip Area
Cells
Interconnect
Timing, Power and
Gate Level Simulation
Verification and
Testng
Post Silicon Validation
Conquest over complexityThe main challenge for modern electronic design is that the circuits we want to design are extremely complex.
(In a few years, the complexity of circuits will become comparable to that of living systems!)
While technology has moved at a rapid pace, capabilities
of human brain have remained the same.
Systematic methods must be developed to conquer complexity.
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
Take a page out of
Software designers’ book!
We must learn from our experience in
developing complex software.
Hierarchical designHierarchical design
Modular architecture
Text based, rather than pictorial description
Reuse of existing resources
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
But Hardware is different!
Hardware is concurrent (all modules work at
the same time) – whereas (traditional)
software is sequential (execute an instruction
at a time).at a time).
Hardware behavior has timing as an integral
part. (Traditional) software is not timing
sensitive.
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
Hardware Description Languages
Need the ability to
Describe
Simulate
at Behaviouralat Behavioural
Structural and
Mixed level
And to
Synthesize
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
Top-down approach
The designer
1. Repeatedly decomposes the system-level
specifications into groups and subgroups of
simpler tasks. simpler tasks.
2. The lowest-level tasks are implemented in
silicon with standard circuits that have been
previously designed and tested (Standard
Cells)
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
The Bottom-up Approach
1. The designer starts at the transistor or gate
level and designs sub-circuits of increasing
complexity.
2. These are interconnected to realize the
required functionality.required functionality.
Top-down approach is better suited for digital
design, bottom-up for analog.
Combination of both is the usual mode.
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
The Two Approaches
Top
DownSpeed
Bottom
UpAccuracy
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
Algorithmic and System Design
• A formal description in HDL.
• Simulator to detect errors in specifications.
• Synthesizer to generate equivalent logic netlist.
• Hierarchical FSMs. • Hierarchical FSMs.
• Hardware-software codesign.
• Formal verification etc.
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
Structural and Logic Design
• Netlist from synthesis or schematic editor.
• Simulator to detect errors in design.
• Fault simulation.
• Automatic test vector generation etc.• Automatic test vector generation etc.
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
Transistor Level DesignHigh usage of simulation tools, depending on the
accuracy needed.
• Switch: digital + signal strengths + capacitances.
• Timing: analog + piecewise linear transistor
models.models.
• Circuit: accurate transistor models in terms of
nonlinear differential equations.
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
• Partitioning keeps tightly connected subblocks in the
same place and helps in floorplanning and placement.
• Floorplanning and Placement assigns space to each
subblock.
• Routing generates wiring patterns for correct
interconnections and aims for minimal area.
Layout Design
interconnections and aims for minimal area.
• Design Rule Checkers for checking mask geometries.
• Circuit Extractors are used for extracting the final circuit
from the masks layout, and then simulated for verifying
the functionality.
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
Importance of Simulation in VLSI Design Flow
• Simulation programs are tools for verifying
IC design at different stages.
• They enable us to verify functionality and
timing of the chip before fabrication (saving timing of the chip before fabrication (saving
time and cost) and allow easy modification
of circuit components .
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
Why simulation?
Modern day VLSI circuits contain thousands of thousands of
transistors.
P-III processor contains 65 million transistors, Itanium 320
million!
Traditional “Breadboard” method fails for VLSI (or even LSI
and MSI) circuits.and MSI) circuits.
God save me, my friends and my company, if an IC is
fabricated only to be discovered during the test phase that
the design is faulty!
70% of the total cost is in the design stage, i.e. before the
silicon goes to the furnace.
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
VHDL
VHDL = VHSIC Hardware Description Language,
VHSIC = Very High Speed Integrated Circuit.
� Using VHDL, one can design, simulate and synthesize.and synthesize.
� Concurrency, timing and clocking can all be modeled.
� Can handle asynchronous as well as synchronous sequential circuits.
� Logical operation and timing behavior
can be simulated.
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
VHDL Based Design Flow
CodingHierarchy Compile Simulate
/VerifyFront
end
Synthesis
Place
+
Route
Timing
Verification
Back
end
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
Capture
Use of VHDL
Specify Verify Formalize
Implement1. For design specification(Specify) 2. For design entry (Capture) 3. For design simulation (Verify) 3. For design simulation (Verify) 4. For documentation (Formalize) 5. As an alternative to schematics. 6. Allows alternative architectures for the
same entity.
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury
Thank you
CVEST, IIIT HYDERABADDr. Shubhajit Roy Chowdhury