Course: Analog Circuit Design

Time schedule:Tu 11.00-13.00We 14.00-16.00Th 14.00-16.00

Office hours: Tu 16.00-18.00

Exams:Feb. (2), Jun.-Jul. (2), Sep. (2)Oral examination

Additional course material:ftp://ftp.dii.unisi.it/pub/users/vignoli/Analog_Circuit_Design

References:

F. MalobertiAnalog Design for CMOS VLSI SystemsKluwer 2001

J. Millman, C. HalkiasIntegrated Electronics: Analog and Digital Circuit and SystemsMcGraw-Hill 1972

R. Spencer, M. GhausiIntroduction to Electronic Circuit DesignPrentice Hall 2003

P. Gray, R MeyerAnalysis and Design of Analog Integrated Circuits (3rd ed.)Wiley 1993

M.S. TyagiIntroduction to Semiconductor Material and DevicesWiley 1991

MATERIALS: electric behavior

semiconductor Insulator conductor

In semiconductors EF is in the Band-Gap

SEMICONDUCTORS: electric behavior

kT

EE F

e

Ef

1

1)(

Fermi-Dirac distribution: occupation probability for the energy level E

 NC is the number of available states (per cm-3) in the conduction band

kT

EE

CkT

EEd

eii

FcFc

eNekTh

mdEEfENpn

2/3

2'

2

4

1)()(

where Ne(E) is Energetic State Density function in the material.

 

Intrinsic Semiconductors: free carriers

DOPING

The Fermi energy

moves with doping

EF n-type

EF p-type

T effect

ACCEPTORDONOR

PHOTOLITOGRAPHY

Photoresist

spin.-coating

Thick film: 1 mm

EXPOSITION:

The mask is transferred to

the photoresist

Uv - X-ray

• The photoresist chemically reacts and dissolves in the developing solution, only on the parts that were not masked during exposure (positive method).

• Development is performed with an alkaline developing solution.

• After the development, photoresist is left on the wafer surface in the shape of the mask pattern.

Masked photoresist

solvents remove exposed (unexposed) resistEtching removes material from wafer surface where resist has been removed

Wet etching

Dry etching

Also PVD

Materials: Si substrate• Monocrystalline silicon is

produced from purified polycrystalline silicon by “pulling” an ingot– polysilicon is melted

using radio frequency induction heaters

– “seed crystal” of monocrystalline silicon is dipped into melt

– silicon grows around structure of seed as seed is slowly withdrawn

• Sawed into wafers about 600 microns thick– only a few microns are

actually used for IC devices

– then etched, polished, and cleaned

– stacked in carriers

• Single crystal silicon – SCS– Anisotropic crystal– Semiconductor, great heat conductor

• Silicon dioxide is created by interaction between silicon and oxygen or water vapor

– Si + O2 = SiO2 or Si + 2H2O = SiO2 + 2H2

– Excellent thermal and electrical insulator– protects surface from contaminants– forms insulating layer between conductors– forms barrier to dopants during diffusion or ion implantation– grows above and into silicon surface– Thermal oxide, LTO, PSG: different names for different deposition conditions and

methods• Polycrystalline silicon – polysilicon

– Mostly isotropic material– Semiconductor– also a conductor, but with much more resistance than metal or diffused layers– created when silicon is epitaxially grown on SiO2

– commonly used (heavily doped) for gate connections in most MOS processes

• Silicon nitride – Si3N4

– Excellent electrical insulator• Aluminum – Al

– Metal – excellent thermal and electrical conductor

Materials

EFFECT OF FLATBAND VOLTAGE VFB (VFB < 0)

VGB = 0

GATEPolisilicon

OXIDESiO2

SUBSTRATEP-type Si

SUBSTRATE CONTACTPolisilicon

- -

Space charge regions

x-tOX 0 xD

x-tOX 0 xD

PotentialVGB-VFB

-VFB

VGB

VOX

Φs(0)

+

VOX

STRONG INVERSION CONDITION

SMALL SIGNAL EQUIVALENT CIRCUIT OF A MOS TRANSISTOR

MOS TRANSISTOR LAYOUT

•SOURCE AND DRAIN PARASITIC RESISTANCES

•SOURCE AND DRAIN PARASITIC CAPACITANCES

•MATCHING

SOURCE AND DRAIN PARASITIC RESISTANCES

SOURCE AND DRAIN PARASITIC CAPACITANCES

MATCHING

You must avoid:

D DS S

Use always the same MOS orientation in your layout: silicon is anisotropic

MATCHING

1

2 3

MATCHING

1

2 3

MATCHING

DESIGN RULES

Geometrical recommendations due to the limited accuracy of the technology (mask alignment, lateral diffusion, etching undercut, optical resolution…)Design Kit: design rules + Spice models and technology features

INTEGRATED RESISTORS 1

DIFFERENT SOLUTIONS (a)

INTEGRATED RESISTORS 2

POLYSILICON RESISTORS

•Lower coupling with substrate

•Up to two shieldings

•Top shielding (from noisy metal lines, package coupling….)

DIFFERENT SOLUTIONS (b)

INTEGRATED RESISTORS 3

INTEGRATED RESISTORS 3

•Poor absolute accuracy (20-40% - large parameter drift)•Good matching (ratio) accuracy (0.1-0.2% - it depends on local parameter variations)

INTEGRATED RESISTORS 4

FACTORS AFFECTING ACCURACY

Design Guidelines (a)

INTEGRATED RESISTORS 5

Design Guidelines (b)

INTEGRATED RESISTORS 6

Design Guidelines (c)

INTEGRATED RESISTORS 7

INTEGRATED CAPACITORS 1

INTEGRATED CAPACITORS 2

tox ≤ 10 nmεr(SiO2)=3.8COX ~ 3.36 fF/μm2COX

INTEGRATED CAPACITORS 3

INTEGRATED CAPACITORS 4

INTEGRATED CAPACITORS 5

A’ = W’L’ WL – 2 (L+W)Δx = A – P Δx = A (1 - Δx P/A)

•The relative reduction of A remains constant, given Δx, if the ratio P/A is constant (matched elements)

•The fringe effect increases the capacitance at the plate boundary proportionally tox P/A -> (L, W >> tox)

•Effect of the thick oxides at the plate boundary

INTEGRATED CAPACITORS 6

Layout examples for poly1-poly2 capacitors

INTEGRATED CAPACITORS: LAYOUT 1

Matching: capacitors with integer ratio

Shielding (well)

INTEGRATED CAPACITORS: LAYOUT 2

Matching: capacitors with not-integer ratio

squared capacitors with area C1 = L2 [C2/C1]

1 rectangular capacitor with area Ck= Wk Lk = (C2/C1 - ) C1

All the capacitors with constant P/A

L2/4L=L/4=LkWk/2(Lk + Wk)Ck/C1=LkWk/L2

[C2/C1]

INTEGRATED CAPACITORS: LAYOUT 3

PASSIVE COMPONENTS: CAPACITORS – Design Guidelines