Post on 21-Dec-2021
CORA RDHC Compact Reconfigurable Avionics – Reconfigurable Data Handling Core
ESA contract 4000121650/17/NL/LF
Presenter Jan Andersson
Cobham Gaisler 2018-10-16
Commercial in Confidence
0
www.Cobham.com/gaisler
Main objective and consortium
1 Commercial in Confidence
To design and manufacture a module hosting a high performance microprocessor and high capacity reconfigurable FPGA(s). The module shall be developed as an Elegant Bread Board (EBB) and will support standardised interfaces (Mil1553B, CAN1), SpaceWire) and lower level digital interfaces (sensor buses) used natively or as a bridge to Analog interface devices. This module acts as the execution platform for the “Compact Reconfigurable Avionics” cross sectorial activity.
1) CAN has been agreed to be excluded.
• Cobham Gaisler, Sweden, prime for the activity and responsible for the VHDL design and
hardware deliverables. • Thales Alenia Space France, responsible for middleware software design. • Thales Alenia Space España S.A., Spain, responsible for FPGA reconfiguration code and
HW/SW validation • Airbus Defence & Space, France will contribute to the systems analysis and trade-off,
requirements and system architecture. • External service provider(s) used for circuit board development.
www.Cobham.com/gaisler
Main concept
2 Commercial in Confidence
• Provide a hardware platform that allows model based avionics SW development to be readily deployed on different avionics modules • GPP based on GR740 – high-performance processor • Utilise the BRAVE NG-Medium – reconfigurable FPGA
– for AOCS sensor processing as well as other tasks. • System hardware architecture – based on OpenVPX
(VITA 65) backplane for module development. • Develop modules to be forward compatible with
Space VPX, VITA 78. • Inter-module communication links – are based on
SpaceWire RMAP. • Data plane links will also be based on SpW-RMAP
due to lack of high speed serial interfaces in the selected FPGA and GPP. • RTEMS environment, boot loader and PUS terminal
software.
Complete with SCOE and EGSE
www.Cobham.com/gaisler
CoRA – Hardware Overview
3 Cobham Proprietary
SCOE
(NIPXI-6230)
(SDSpaceWirePXIInterface)
RDHCEGSE
RDHC
Backplane
8 x Tacho in
Power
REG240 VAC
3xRS422
RW1i
4 analogue in (nom)
ELEV-EURCS-EUFADS-EU
(NIPXIe-8431/8)
GNSS1&2INS1&2STR1STR2
Syncro(NIPXI-6683H)
PPS
OtherpotentialEGSE
interfacesnotincludedinthisview
PC
USB-JTAG converter
JTAGUSB
Ethernet switch
Ethernet
USB
RS232
GRESBSpW
SpW
SpW
CAN
Ethernet
GPIO(16)
SpW (red)
RW2iRW3iRW4i
8 x analogue out
SpW (nom)
SpW
SpW
SpWDP
USB
Power Adapter(s)
ReservedforPL3
ReservedforredundantPLmodules
ReservedforredundantSC
ReservedforredundantSC
SpWCP
Auriga STR
Reservedfor2xnominalandredundantPL4xSpWDP
Reservedfor2xnominalandredundantPL
DIGANIF Board
8-chADC
8-chDAC
8-chTACH
BRAVE
3xRS422trx
SPIhdr
SPI
SpWhdr
SpW
ControlPlaneSpW
DataPlaneSpW
PWR,RST,CLKetc.
FlashSPI
SDRAM
SCn
SCr
SCnSCr
JTAG
SelectConfigLogic
SpWconf
PL0nPL0rPL1nPL1r
SCn_bSCr_b
SpWgen
JP1
SM[3..0]
JP2
JP3
TofutureSpaceUMmodule
1
SpW+DC
3xRS422
FTDI
4xADC
DAC
STR
TACHO
SPWIF Board
2xSpW-ControlPlane
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
SPIhdr
SPI
6xSpW-DataPlane
SpW
SpW
SpW
SpW (red)
SpW (red)
SpW (red)
PWR,RST,CLKetc.
SCn
SCr
SCn
SCr
LVDS
LVDS
SpW (extra)
SpW (extra)
LVDS
LVDSSpW (misc)
SpW (misc)
PL0nPL0rPL1nPL1r
GR718
P1
P2
EBB
Mezzanine
GR740
BRAVE
PWR,RST,CLKetc.
BRAVEconf
LVDSSpW
HDRSpWI/O
7
SODIMM
VMBRAVE(SDRAM64Mx(32+16))
SODIMMSDRAM64Mx(32+16)
BOOT(PROM≥32kx8)
HDR(forstand-alone
use)
LVDSCGSpW (red)
8xGPIO
USBFTDIUART/JTAG
eSATASpFi
10
APST(SPIFlash≥32MB
NVMBRAVE(defaultbitstSPIFlash≥2MB)
JTAG
SDRAMctrlw.EDAC
PROMctrlw.EDAC LEON4x4
JTAGDCL
MIL-STD1553B Ethernet 8xSpW
routerUART0&1
GPIO2(22)
GPIO1(16)
SPIcontroller
PCImaster
GR718conf
PL1r-CPPL2r-CPPL3r-CP
PL1r-DPPL2r-DPPL3r-DP
PL1n-CPPL2n-CPPL3n-CP
PL1n-DPPL2n-DPPL3n-DP
PPSPPS in
Backplanesupply
DRVETHEthernet
8 x GPIO
MIL-1553
USBFTDIUART UARTUART
1
PL_bkpn-DP
PL_bkpr-DP
4xSpWdata GR718
P1
UART
JTAG FTDI
GPIO/UD_SC_sel
ViaRTMorfuturecustom-
backplanes
UD/SC_N/R1
(NI6581)
RW1oRW2oRW3oRW4o
SM[3..0] TofutureSpaceUMmodule
BRAVE_CONFIG_RDY
Mezzconn
DRV1553
SAS1SAS2
(NIPXIe-4322)
TB
4xADC
4 analogue in (red)
DRVSpFi
SC_sel4UD/BR_CNTRL_NUD/BR_CNTRL_R4+4
1(CONF_GEN_SEL)
3(RST,ERR,INT)
5(UDforGPIOetc)
SAGE activity HW
www.Cobham.com/gaisler
COTS BB configuration Delivered to neighbour activities in relation to PDR
4 Commercial in Confidence
GR-CPCI-GR740
MIL-1553
Ethernet
UART
GPIO(8)
BRAVE CLGA625Development Kit
JTAG/I2C
SPIExt
SpWConf
SpWUsr1
SpWUsr2
FMCHPC
HSMC
POWER
Bk0Hdr
BRAVENG-Medium
128Mx16DDR2
SDRAM2x256 MiB
SPI Flashlarge
Power Adapter 9V
Boot Flash8Mx8
SPI Flashsmall
GPIO(8)
PPS
JTAG-to-USB
UARThdr
• GR-CPCI-GR740 Development Board • BRAVE NG-Medium
Development Kit • Misc. parts and cables
• Used with SCOE and EGSE and parts of RDHC for SW development
www.Cobham.com/gaisler
RDHC configuration 6U OpenVPX designed with SpaceVPX compatibility in mind
5 Commercial in Confidence
RDHC
Backplane
Power
REG240 VAC
SpWDP
ReservedforPL3
ReservedforredundantPLmodules
ReservedforredundantSC
ReservedforredundantSC
SpWCP
Reservedfor2xnominalandredundantPL4xSpWDP
Reservedfor2xnominalandredundantPL
DIGANIF Board
8-chADC
8-chDAC
8-chTACH
BRAVE
3xRS422trx
SPIhdr
SPI
SpWhdr
SpW
ControlPlaneSpW
DataPlaneSpW
PWR,RST,CLKetc.
FlashSPI
SDRAM
SCn
SCr
SCnSCr
JTAG
SelectConfigLogic
SpWconf
PL0nPL0rPL1nPL1r
SCn_bSCr_b
SpWgen
JP1
SM[3..0]
JP2
JP3
TofutureSpaceUMmodule
1
SpW+DC
3xRS422
FTDI
4xADC
DAC
STR
TACHO
SPWIF Board
2xSpW-ControlPlane
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
SPIhdr
SPI
6xSpW-DataPlane
SpW
SpW
SpW
SpW (red)
SpW (red)
SpW (red)
PWR,RST,CLKetc.
SCn
SCr
SCn
SCr
LVDS
LVDS
SpW (extra)
SpW (extra)
LVDS
LVDSSpW (misc)
SpW (misc)
PL0nPL0rPL1nPL1r
GR718
P1
P2
EBB
Mezzanine
GR740
BRAVE
PWR,RST,CLKetc.
BRAVEconf
LVDSSpW
HDRSpWI/O
7
SODIMM
VMBRAVE(SDRAM64Mx(32+16))
SODIMMSDRAM64Mx(32+16)
BOOT(PROM≥32kx8)
HDR(forstand-alone
use)
LVDSCGSpW (red)
8xGPIO
USBFTDIUART/JTAG
eSATASpFi
10
APST(SPIFlash≥32MB
NVMBRAVE(defaultbitstSPIFlash≥2MB)
JTAG
SDRAMctrlw.EDAC
PROMctrlw.EDAC LEON4x4
JTAGDCL
MIL-STD1553B Ethernet 8xSpW
routerUART0&1
GPIO2(22)
GPIO1(16)
SPIcontroller
PCImaster
GR718conf
PL1r-CPPL2r-CPPL3r-CP
PL1r-DPPL2r-DPPL3r-DP
PL1n-CPPL2n-CPPL3n-CP
PL1n-DPPL2n-DPPL3n-DP
PPSPPS in
Backplanesupply
DRVETHEthernet
8 x GPIO
MIL-1553
USBFTDIUART UARTUART
1
PL_bkpn-DP
PL_bkpr-DP
4xSpWdata GR718
P1
UART
JTAG FTDI
GPIO/UD_SC_sel
ViaRTMorfuturecustom-
backplanes
UD/SC_N/R1
SM[3..0] TofutureSpaceUMmodule
BRAVE_CONFIG_RDY
Mezzconn
DRV1553
4xADC
DRVSpFi
SC_sel4UD/BR_CNTRL_NUD/BR_CNTRL_R4+4
1(CONF_GEN_SEL)
3(RST,ERR,INT)
5(UDforGPIOetc)
Two OpenVPX Payload Modules: • General I/O Board
(DIGANIF) • SpaceWire I/O
Board (SPWIF)
One OpenVPX Switch Module: • GPP and FPGA
Board (EBB with mezzanine) • Upgradable • Dataplane would
need to be adapted for SpaceVPX compatibility
OpenVPX Backplane (COTS) COTS chassis and Power module
www.Cobham.com/gaisler
RDHC configuration EBB – GR-VPX-GR740
6 Commercial in Confidence
EBB
Mezzanine
GR740
BRAVE
PWR,RST,CLKetc.
BRAVEconf
LVDSSpW
HDRSpWI/O
7
SODIMM
VMBRAVE(SDRAM64Mx(32+16))
SODIMMSDRAM64Mx(32+16)
BOOT(PROM≥32kx8)
HDR(forstand-alone
use)
LVDSCGSpW (red)
8xGPIO
USBFTDIUART/JTAG
eSATASpFi
10
APST(SPIFlash≥32MB
NVMBRAVE(defaultbitstSPIFlash≥2MB)
JTAG
SDRAMctrlw.EDAC
PROMctrlw.EDAC LEON4x4
JTAGDCL
MIL-STD1553B Ethernet 8xSpW
routerUART0&1
GPIO2(22)
GPIO1(16)
SPIcontroller
PCImaster
GR718conf
PL1r-CPPL2r-CPPL3r-CP
PL1r-DPPL2r-DPPL3r-DP
PL1n-CPPL2n-CPPL3n-CP
PL1n-DPPL2n-DPPL3n-DP
PPSPPS in
DRVETHEthernet
8 x GPIO
MIL-1553
USBFTDIUART UARTUART
1
PL_bkpn-DP
PL_bkpr-DP
4xSpWdata GR718
P1
UART
UD/SC_N/R1
Mezzconn
DRV1553
DRVSpFi
SC_sel4UD/BR_CNTRL_NUD/BR_CNTRL_R4+4
www.Cobham.com/gaisler
BRAVE as accelerator for GR740 FPGA design architecture
7 Commercial in Confidence
• The processing steps for a set of data to be processed by an accelerator:
– GR740 using RMAP commands fills the external memory connected to FPGA with the data.
– The GR740 commands the accelerator to process the data (GR740 RMAP to APB of accelerator).
– The accelerator process and store it to the external memory. – After the process is completed, the accelerator can trigger a
process done signal (interrupt) to the GR740 via a GPIO. – Based on the “process done” signal, the GR740 can send RMAP
read commands to fetch the processed data.
• The first evaluation has been performed with IP’s from ESA’s IP core portfolio using the BRAVE NG-MEDIUM CLGA625 DevKit V2.
• The design consists of an AMBA bus with SpaceWire RMAP Target, UART debug link, on-chip RAM (128 Kbytes) and other peripheral devices connected on an APB bus.
• Model Based Avionics Development (MBAD) team SW development to “auto generate” FPGA programing files, RDHC team supplies VHDL example design with interface IP from ESA IP core portfolio.
www.Cobham.com/gaisler
GR740 software architecture
8 Commercial in Confidence
From CORA neighbour activities
• RDHC platform will be provided with the following software: – RTEMS environment including drivers for EBB interfaces – Boot loader including self-test and support for in-flight patching of application SW – PUS terminal software (middleware) for accepting commands over SpaceWire – Driver software for FPGA reconfiguration over SpaceWire (allowing to upload bitstreams
through PUS)
www.Cobham.com/gaisler 9 Commercial in Confidence
Thank you for listening!