ECE 697J 1

Commercial Network Processors

ECE 697JDecember 5th, 2002

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AMCC nP7250 Network Processor

Presenter: Jinghua Hu

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AMCC nP7250

Released in April 2001Packet and cell processingFull-duplex OC-48c Network Processor

Nominated for Microprocessor Report Analysts’ Choice Award

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General Features

Offers layer 2, 3, 4 and above packet/cell processing at wire speedSupports multi-service cell/packet switching/routing inn Clear Channel Moden Multi-Channel Modes

Wide range of applications

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Hardware: nPcore

nPcore Modeln Hardware multi-threading n Optimized Network Instruction Set Computingn Zero-cycle context switchingn Four On-chip Coprocessors

n Dual nPcores offer OC-48c bandwidth

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Hardware: Co-processors

Four Embedded co-processorsn Packet Transform Enginen Policy Enginen Statistics Enginen Special Purpose Engine

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Programming Model

Fundamentally simplified multi-processor programming modeln Single-stage, run to completionn Each packet/cell executes in a single thread

on a single coren Facilitate software developers

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AMCC solution set

nP7250 OC-48c Network ProcessornPX5700 10Gbps Traffic ManagernPX5800 40-320Gbps Switch Fabric

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Motorola C-5E Network Processor

ECE697J: Active Network

Presenter: Jianhong Xia12/05/2002

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Product Picturen The C-5e™ Network

Processor (NP)

n Second generation of the C-Port™ family of network processors

n Most integrated, flexible, and functionally-rich processor

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Block Diagram

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Block Diagram

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Features (1)n Processor & Power Consumption

n 266MHZ, 9W, 1.2V typical

n Bandwidth & Computing Powern 5GBPS, non-blocking throughput, 4,500 MIPS

n RISC Cores & Co-Processorsn 17 programmable RISC Cores for cell/packet forwardingn 32 programmable Serial Data Processors for processing bit

streams

n On-chip classification coprocessor n supporting over 46 million IPv4 lookups/second

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Features (2)n Flexible interfaces

n any serial or parallel protocoln individual port data rate from DS1 to OC-48c/STM-16

n External C-Port Q-5 TMC (Traffic Management Coprocessor)

n advanced QoS

n Simple and efficient programmingn C-language with standard APIs

n Royalty-free reference applicationsn Key alliances in

n fabrics, coprocessors, network software, and design services

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Channel Processor

n Consists of n Dedicated RISC Core n Dual Serial Data Processors (SDPs)

n Data encoding/decodingn Framing / Formatting / Parsingn Error checking (CRCs)n Control programmable external pin logic

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Executive Processorn Centralized computing resource n Manages the system interfacesn Conventional supervisory tasks

n Reset and initialization of the C-5e NPn Program loading and control of CPsn Centralized exception handlingn Management of a host interface through the PCIn Management of system interfaces (PCI, Serial Bus,

PROM)

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Table Lookup Unit

n Classification Enginen High-speed, Flexiblen 46 million IPv4 lookups per second

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Queue Management Unit

n Support QoS Managementn Up to 512 queue to satisfy the traffic

management requirementsn More powerful with Q-5 TMC (Traffic

Management Coprocessor)

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Buffer Management Unit

n Interfaces to Single Data Rate Synchronous DRAM. n Used as buffers for receiving and

transmitting data between CPs, the FP, and the XP

n Used as second level storage in the XP memory hierarchy

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Agere Payload PlusJayakrishnan Nair

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Traditional NP Approach

Custom ICs for wire-speed routing/ queuingn High Development Costsn Long time to market n No Flexibility or scalability to support future enhancements (IPv6)

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Traditional Methods Insufficient

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The Novel Agere’s Approach

Have a highly pipelined Chipset for fast Data-Path

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How is Agere’s Approach Novel?The Payload Plus is a breakthrough 3-chip solution for handling fast traffic, as in OC-48 or Gbps networks

Performs all of the classification, policing, traffic management, QoS, traffic shaping and packet modification functions needed for Gbps network platform

Focus on wire-speed data stream, by working in tandem with physical interface devices, microprocessors, and backplane fabric offerings

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The Payload Plus FamilyPayload plus NPU family has three chips

Fast Pattern Processor (FPP)Routing Switching Processor (RSP)Agere System Interface (ASI)

These chips are connected to:Physical Layer (PHY) - For Data to Come InBackPlane Interface (BPI) – Data OutMicroprocessor (µP) – For Data Processing

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The Payload Plus Chipset

Agere Chipset forms the wire-speed path

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Fast Pattern Processor (FPP)Functions

• Recognition, Classification

• Packet Filtering

• Functional Processing

• Assembly if necessary

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Fast Pattern Processor (FPP)Programmable classification up to Layer 7High performance scalable architectureHighly pipelined multi-threaded processing of PDUsTable lookup with millions of entries & variable entry lengthsEliminates need for external CAMs;Functional Programming Language (FPL) compatibleConfigurable UTOPIA/POS interfacesATM re-assembly at OC-48c ratesSimplifies design and reduces development cost and time

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FPP System Architecture

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Routing Switch Processor (RSP)Functions

• Transmit queuing

• Quality of Service (QoS)

• Class of Service (CoS)

• Packet Modification including segmentation

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Routing Switch Processor (RSP)Programmable packet modificationsn Discard Policy, QoS, CoSn 16 levels of priority

Support for MulticastGenerates required CRC/ ChecksumOC-48c bandwidthSupport for emerging applicationsHigh performance architecture – pipelined processingSmart processing at very high bandwidths

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RSP System Architecture

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The Software Landscape

Agere Chipset forms the wire-speed path

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The Chip Details

TSMC 0.18um Technology, Max Power Consumption- 6.2 Watts

26.4 Million Transistors, 1.33 Million RAM bits

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Bandwidth vs. Payload Length

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IPv6 Forwarding (ATM)

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ConclusionsValue Add Elements:n Classificationsn Statistics Gatheringn Buffer Managementn QoS, CoS Managementn Data Modifications

Overheads:n Linked List and Queue Maintenancen Parallel Processingn Pipeline Processing

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Thank You

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EZchip NP-1

Presented by Hemant Kumar

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Ezchip

l Task optimized processorsl 4 types of tasks :parse, search, resolve and

modifyl Pipelinedl Superscalar (multiple instances of each

processor)l Multiple Embedded memory coresl No caches

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Architecture

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Vitesse IQ2000

Youngsuk Jun

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Applicationsn Complex multi-protocol routingn QoSn Classificationn Filteringn Stateful inspectionn Traffic policingn Traffic grooming/shapingn Multicast/stream managementn Address translation

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Highlights

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Architecture

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Solutions

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Lexra NetVortex

Presented by Ramaswamy Ramaswamy

LexraNetVortex PowerPlant (NVP)

ECE 697J, Fall 2002

Features

OC-192, OC-768 processing (10 Gbps to 40 Gbps)16 LX8380 packet processors (420MHz)128kB on-chip SRAM0.13um process12W typical power dissipation

LX8380 Packet Processing Device

MIPS ISA based

Special instructions for packet processing

Bit field manipulation Check sum computation

Hardware multi-threading support (4 threads)

Fine grained HMT16 kB I-cache, D-cache

Crossbar switch allows access of shared resources

LX4580 Processor