Post on 02-Apr-2020
International Journal of Energy Policy and Management
2015; 1(1): 20-32
Published online April 30, 2015 (http://www.aascit.org/journal/ijepm)
Keywords Distributed Cloud Computing
Network,
Switching,
FPGA Device,
Automated Change Over,
Solar
Received: March 29, 2015
Revised: April 13, 2015
Accepted: April 14, 2015
Cloud DPI: A Cloud Datacenter Power Isolation Design Using Embedded FPGA Device, a Case for DCCN
K. C. Okafor1, O. U. Okparaku
2, F. N. Ugwoke
3, G. N. Ezeh
1,
I. E. Achumba1, U. Diala
1, 4
1Dept. of Electrical Electronic Engineering, Federal University of Technology Owerri, FUTO,
Nigeria 2Dept. of Electronic Engineering, University of Nigeria, Nsukka, Nigeria 3Dept. of Computer Science, Michael Okpara University of Agriculture, Umudike, Umuahia,
Nigeria 4Dept. of Automatic Control and Systems Engineering, University of Sheffield, UK
Email address arissyncline@yahoo.com (K. C. Okafor), ogbonna.oparaku@unn.edu.ng (O. U. Okparaku),
ndidi.ugwoke@gmail.com (F. N. Ugwoke), ugoezeh2002@yahoo.com (G. N. Ezeh),
ifeyinwaeucharia@yahoo.com (I. E. Achumba), uhdiala1@sheffield.ac.uk (U. Diala)
Citation K. C. Okafor, O. U. Okparaku, F. N. Ugwoke, G. N. Ezeh, I. E. Achumba, U. Diala. Cloud DPI: A
Cloud Datacenter Power Isolation Design Using Embedded FPGA Device, a Case for DCCN.
International Journal of Energy Policy and Management. Vol. 1, No. 1, 2015, pp. 20-32.
Abstract The Distributed Cloud Computing Network (DCCN) architecture in a previous work did
not address the issue of power system isolation for continuous day to day operations.
Owing to the limitations of existing isolation and changeover systems, this research then
developed a very fast switching Cloud DPI system which can switch from utility grid to
the solar satellite micro-grid plant while offering great flexibility from FPGA device
(Altera Cyclone II development board). The work completed the initial design prototype
while assuring that this will open a new platform for further research and development
for improved automated change over systems particularly in the DCCN architecture.
1. Introduction
The unreliability of power supply in developing countries inhibits the growth and
development of both commercial and industrial sectors. Furthermore, these intermittent
power outages result to damage of equipment and business losses, hence the need to
automate changeover switching systems particularly for a datacenter networks. Smart
Green Energy Management System (SGEMS) presented in an earlier work failed to
explain the power supply system of the DCCN [1] [2]. However, when comparing with
other methods of automated power supply changeover systems, this paper presents a cost
effective approach. This seeks to replace the power supply changeover from public
utility to backup supply generator or vice in any case of power failure or insufficient
voltage. This was achieved by the use of very fast Field Programmable Gate Array
(FPGA) as a central control unit that serves to reduce component count while engaging
electromechanical relays to effect switching. Some characteristics of the system include:
i. Stability to long hours of operation
ii. Resilience for any rugged environment
iii. High reliability
iv. System Simplicity
International Journal of Energy Policy and Management 2015; 1(1): 20-32 21
v. Highly cost effective because of the FPGA
component count merit
In this paper, efforts were made to exploit the advanced
programmable logic device (PLD) hardware architecture in
bringing about automation of changeover process in a
proposed DCCN. This system is designed to proffer solution
to the shortcomings of the already existing manual
changeover by performing power swap from public power to
generator automatically and vice-versa.
The rest of this paper is organized as follows: Section II
discussed the literature review. Section III presented the
design methodology. Section IV detailed the system
implementation.Section V concludes the work.
2. Literature Review
Various efforts have been made in developing automatic
change over systems for both domestic and industrial
applications.
The authorsin [3] developed a model of an intelligent
changeover fuzzy logic switching system (ICOFLS)
fordomestic load management. The presented model
combined the benefits of fuzzy logic controller (FLC) and
vector-control in a single system controller to derive a hybrid
controller that was contextualized for management of three
major entities in fuzzy logic rule base: Phase lines, Generator
system and Inverter system. MATLAB Simulink fuzzy logic
blockset was used in their research for the modelwhile
relying on the mamdani fuzzy inference structure. The work
in [4] presented the design and construction of an automatic
phase change-over switch that switches electrical power
supply from public supply to generator in the event of a
power outage or insufficient voltage. The system uses an
electronic control circuit involving integrated circuits,
transistor and electromechanical devices. Similar discussions
in [5] and [6] explained a cost effective approach to
implementing a change over system. In the work, digital
integrated circuits and microcontroller were used to reduce
the component count as well as improve the speed of the
system.
Existing works lacks flexibility, involves high component
count, and requires complex troubleshooting procedure as
well as hectic system maintenance. This is not acceptable for
the DCCN changeover system earlier proposed. Hence,this
paper proposes and implements a change over system
(CloudDPI) that leverages the hardware parallelism of Field
Programmable Gate Arrays (FPGA) to:
i. Improve performance and speed of automation.
ii. Reduce component count.
iii. Miniaturize the system with reduced overall system
complexity.
FPGAs are a recent breakthrough in the family of
semiconductor devices and so are quite costlier than the
typical microcontrollers implemented in the previous
automatic changeover systems.
3. Methodology
3.1. Electronic Device Automation Approach
A detailed study on FPGA architectures was carried out to
understand the logic and configuration layers ie.
Configuration Logic Blocks (CLB), lookup tables, registers,
interconnect network and I/Os. The following steps were
adopted.
3.1.1. Design Entry Phase
Gate level modelling involving compilation, simulation,
programming, and verification in the FPGA hardware was
carried out.In the system development phase, Altera Quartus
II software was used. In this phase, design entry was done for
the behavioural description. Pin assignments were carried out
on the design schematics. A library of parameterized modules
(LPM) functions and the use Verilog HDL code to add a logic
block that terminates the design entry phase was leveraged
for design synthesis.
3.1.2. Project Compilation
Compilation comes after creating the design. Compilation
converts the design into a bitstream that can be downloaded
into the FPGA. The most important output of compilation is
an SRAM Object File (.sof), which is used to program the
device. The software also generates other report files that
provide information about the code as it compiles.
3.1.3. Device Programming
After the compilation and verification of the design, next
step was to program the FPGA on the development board.
The SOF created in the above step is downloaded into the
FPGA using the USB-Blaster circuitry on the board.
3.1.4. Hardware Verification
Afterverifying the design in hardware, an observation on
the runtime behavior of the FPGA hardware design was made
while ensuring proper functioningof the system. The EDA
simulatorwas used to check functionalities also.
3.2. System Design
For the switching system, the thereare different methods of
electrical transfer. The break before makemethod is adopted
in this design as the transfer switch will break the
contactfrom one power source, before switching to the other
power source [7]. Thisbreak can serve for a small or large
amount of time, depending on theconfiguration of switch
used. The advantage of this method is that it preventsback
feeding from the emergency generator into the electric power
supply line.This method ensures that there is no feedback of
power from any of thethree inputs into the electric power
supply line when one is in use.
3.3. Design Considerations
Several factors were considered in the Cloud DPI design:
-Environmental considerations
22 K. C. Okafor et al.: Cloud DPI: A Cloud Datacenter Power Isolation Design Using Embedded FPGA Device, a Case for DCCN
1. Τhe effect of moisture on electrical system can be
hazardous; therefore measures were taken to secure electrical
connections from moisture and rain.
2. The casing was made of a rugged material so as to
withstand stressthat may occur during use.Power systems
generate heat, adequate spacing of components and modules
was ensured to keep the system at ambient operating
temperature.
3. Components outside the casing must have a high
environmental tolerance.
-Operation and Maintenance considerations:
1. Components were not closely packed together to aid
ease of de-soldering or replacing components without
damaging other components.
2.Circuit diagrams are made as simple as possible for ease
of understanding and troubleshooting.
3. Common conventional components were used in this
design for ease ofreplacement.
4.De-rating components was made to continue operation
even with slight changes in input conditions.
5.Method of electrical joint adopted was soldering.
Soldered joint has two major advantages over other electrical
connections:
-It is an excellent physical connection. Solder fills in the
pores of a metal surface, becoming part of the surface. A
good solder connection is as strong as the metal surface itself.
- It is an excellent electrical connection. Properly applied
solder has virtually no electrical resistance. This is especially
important in low voltage applications [8].
6.This system will be in for long hours of operation;
therefore highly reliable components with little sensitivity to
temperature will be used.
7.Designing for safety is very important. Hence, all wired
connections was made to be intact and covered to prevent
risk of electric shock.
8. Indicators (LEDs) will make it easy to understand mode
of operation and ease of information extraction during
maintenance.
9.FPGA pin are assigned to aid wiring routes. This
featurenot obtainable in ASICs.
-Cost considerations
1. Using FPGA to automate this changeover system
essentially reduces component cost during the design
integration. Unlike custom microcontrollers which will
require other components to aid control, FPGA solely
controls the system with lesser component count.
2. In trying to achieve high reliability in this system, it
must not be too costly to afford. This system is designedwith
cheap but reliable components.
3. The casing is designed to size of the circuit board so as
not to further increase cost of construction.
3.4. Design Specification
The following are the design specifications for the FPGA
design in order to function properly in the DCCN power
room.
1. Input to each power supply conditioning 220V.
2. Output of power supply conditioning per phase:
- 3.3V to FPGA inputs.
- 12V to power the FPGA.
3. It must give a usable output voltage (i.e. 100~240V).
4. It must produce a pure and constant AC voltage.
5. Four input and output modules.
6. Priorityto public power supply over the generator phase.
3.5. System Block Diagram
This changeover system is comprised of four sections as
shown in the blockdiagram in Fig 1. The Simplicity of this
block diagram is as a result of the use of FPGA which
reduces component count in this work. However, each block
has sub components and as a result, will require a brief
explanation detailed next.
3.5.1. The Input Power Supply Conditioning
This is the first phase of the block diagram. The input
power conditioning stage involves the four input supplies (3
phases plus one auxiliary). The power from each of the
phases will undergo a full-wave rectification and then
stepped down to a level which will be usable by the
electronic controller. This is shown in Fig 2.
3.5.2. Electronic Control
This phase consists solely of the FPGA. The FPGA is
programmed to select from the inputs, which phase will
supply power to the output. As earlier described, the
programming code is loaded and implemented by the FPGA
to automate the changeover system.
3.5.3. Switching System
In phase one, the power from the supplies is stepped down
to a usable level for the FPGA to operate. The input and
output voltage of the FPGA is of very low level (3.3V)
therefore must be increased (or amplified) and maintained at
a suitable level for its intended load. This sub system
contains all the components required to increase the voltage
well enough to operate the contactors which perform the
switching as instructed by the electronic control. A switched
multi plug socket is provided from which a plug can be used
to extend power to any other device or load. The socket has a
light indicator which will be used for testing purposes.
The block diagram in Fig 1 gives a conceptual general
overview of the whole system.
Fig. 1. A Simplified Block diagram of CloudDPI Changeover System
International Journal of Energy Policy and Management 2015; 1(1): 20-32 23
Fig. 2. Signal Conditioning Circuit Diagram for Input Power Conditioning.
The Input Power conditioning or the Input Power Supply
Conditioning have the following optimized components for
the design.
R1=220Ω; R2=5kΩ; R3=100kΩ; Diode =IN4001;
Transistor= 2SC3279; Voltage regulator=317; C1=470µF;
Voltage transformer 220V:24V. The220/24V transformer is
used to step down power from an AC source andconverting
24V. 24V is required at the contactor. Four diodes are
arranged to become a full wave rectifier as shown in the
circuitdiagram. The full wave rectifier converts the negative
half-wave of an AC into apositive half-wave (i.e. constant
polarity AC to DC).The capacitor acts as a filter.The voltage
regulator works with the two resistors R1 & R2 to step down
thevoltage to 12V required as power supply for FPGA.
The voltage regulator relationship is given as:
Vout=1.25[1+ (R2/R1)] (1)
The 12V is passed through a diode to prevent backward
flow of current into thepower supply.R3 is a variable resistor
tuned to provide 3.3V to the base of an NPN transistorbiased
to function as a switch to the FPGA. This module is
duplicated for thefour inputs to the FPGA.
For the electronic control of Fig 1, the programming code
required to affect this function is shown in Fig 3, Fig 4 and 5
A behavioural level of abstraction in Verilog programming
language was used. Recall that Verilogis a Hardware
Description Language (HDL). This hardware description
language is a language used to describe any digitalsystem.
Verilog allows us to design a digital design at behavior Level,
RegisterTransfer Level (RTL), and gate level and at switch
level. Verilog allows hardwaredesigners to express their
designs with behavioural constructs, deterring thedetails of
implementation to a later stage of design in the final design
[9].As shown in Fig 3, this code describes the system as a 4:1
multiplexer. By assigning the phases as inputs R, Y, B, G into
the multiplexer, the switching conditions were described. The
Altera Software then generates the hardware corresponding
to the description given above. The Altera Cyclone II
development boardis used in the Cloud DIP design in the
initial prototype.
In the design, 12V from the diode is used to power the
FPGA boards while 3.3V from four transistors are connected
tothe FPGA as input to the FPGA. The FPGA gives out 3.3V
from the four outputs (four phases) to theswitching system.
Fig. 3. Verilog Code description –A Snapshot
Fig. 4. FPGA development board (Altera Cyclone II development board)
24 K. C. Okafor et al.: Cloud DPI: A Cloud Datacenter Power Isolation Design Using Embedded FPGA Device, a Case for DCCN
Fig. 5. FPGA Board Detailed diagram
3.6. CloudDIP Switching System
The optimal component specification includes: R4=1KΩ;
R5=22KΩ; R6=10KΩ Variable; R7=100KΩ; R8= 1KΩ;
Contactor=24V rated; Op Amp=LM358. The switching
system consists of an Op Amp with 12V input power. It
compares the 3.3V input voltage from IKΩ resistor and a
voltage divider combination of 22kΩ and 10kΩ voltage
resistor to give 1V. If 3.3V > 1V, the output will be 12V
indicating light in any phase. If there is no power from any
phase, 0V<1V , then there is no output from the comparator.
The Op Amp requires a 100kΩ pull-up resistor. A biasing
transistor of IkΩ is used to connect an NPN switching
transistor 2SC3279 to a contactor which performs the
switching to the load/sockets.The composite circuit diagram
shows the connection of the schematic diagrams of the three
modules as explained above is presented in Fig 6 and 7.
Fig. 6. Circuit diagram for switching system.
International Journal of Energy Policy and Management 2015; 1(1): 20-32 25
Fig. 7. Composite circuit diagram
4. System Implementation
4.1. Design Synthesis
Fig. 8. Implementation Activity Model for Cloud DIP Design
Fig 8 shows the block diagram depicting the series of
activities carried out during the implementation phase of the
change over system.
As explained previously, Fig 9 shows the FPGA
programming environment. The ALTERA Quartus II
development software was used to write codes which
wasloaded intothe FPGA. The software is compatible with
Windows XP/Vista.Before the code description, pin
assignments based on table 1 was configured in Fig 11a
Table 1. Cloud DPI Pin assignments
S/N Node name Direction Location
1 B_Phase Input PIN_143
2 Gen_Phase Input PIN_142
3 R_Phase Input PIN_141
4 Y_Phase Input PIN_139
5 To_Contactor[4] Output PIN_72
6 To_Contactor[3] Output PIN_71
7 To_Contactor[2] Output PIN_70
8 To_Contactor[1] Output PIN_69
As shown in table 1, Pin assignments indicate where wires
should be connected on the pins of the FPGA. There is no
predefined pin assignments. This helps in making pin
assignments best suited for a circuit diagram to make routing
of wires easier. Fig 11b shows the FPGA body pin
assignment Snapshot capture from Quartus II IDE.
26 K. C. Okafor et al.: Cloud DPI: A Cloud Datacenter Power Isolation Design Using Embedded FPGA Device, a Case for DCCN
Fig. 9. Project File Creation Snapshot.
Fig. 10. Code Description in the Quatus II Development Environment
International Journal of Energy Policy and Management 2015; 1(1): 20-32 27
Fig. 11a. Cloud DPI Development Environment/software
Fig. 11b. FPGA body pin Assignment Snapshot
28 K. C. Okafor et al.: Cloud DPI: A Cloud Datacenter Power Isolation Design Using Embedded FPGA Device, a Case for DCCN
Fig 12 shows the snapshot for Cloud DPI Real time logic (RTL) while Fig 13 shows the Snapshot for generated hardware
after the logical compilation.
Fig. 12. A View snapshot for Cloud DPI RTL
Fig. 13. Snapshot for Generated hardware
International Journal of Energy Policy and Management 2015; 1(1): 20-32 29
4.2. Testing and Troubleshooting the FPGA
The JTAG programming method is used in the work. In
this method of programming named after the IEEE standards
Joint Test Action Group, The configuration bit stream
downloads directly into the Cyclone II FPGA through the
USB-Blaster circuitry. The FPGA retains this configuration
as long as power is applied to the board; the FPGA loses the
configuration when the power is turned off. This is why the
JTAG method is good for testing [10].The procedure is
outlined below(see Fig 14):
1. The work first ensured thatpower is applied to the
Cyclone II FPGA Starter board.
2. Connect the supplied USB cable to the USB-Blaster port
on the board.
3. A Configuration of the JTAG programming circuit on
the board was made by setting theRUN/PROG switch (on the
left side of the board) to the RUN position.
4. To program the FPGA, Quartus II Programmer module
was used to select aconfiguration bit-stream file with
the .soffilename extension.
Fig. 14. Cloud DIP JTAG Programming Architecture
After confirming that the programming codes tested on the
FPGA are working properly, the AS programming method is
used to make a “permanent” programming. In the Active
Serial programming method, the configuration bit stream
downloads into the Altera EPCS4 serial EEPROM chip. The
EEPROM provides non-volatile storage of the bit stream,
retaining the information evenwhen power to the Cyclone II
FPGA Starter board is turned off. When the board powers up,
the configuration data in the EPCS4 device automatically
loads into the Cyclone II FPGA [10]. The procedure for Fig
15 is explained below:
1. It was ensured that power is applied to the Cyclone II
FPGA Starter board.
2. Connect the supplied USB cable to the USB-Blaster port
on the board.
3. Configure the JTAG programming circuit by setting the
RUN/PROG switch (on the left side of the board) to the
PROG position.
4. To program the EPCS4 device, use the Quartus II
Programmer module to select a configuration bit-stream file
with the .poffilename extension.
5. After the programming operation completes, set the
RUN/PROG switch back to the RUN position.
6. Reset the board by turning the power switch off and
then on again. This action causes the new configuration data
in the EPCS4 device to load into the FPGA chip.
Fig. 15. Active Serial Programming Infrastructure
30 K. C. Okafor et al.: Cloud DPI: A Cloud Datacenter Power Isolation Design Using Embedded FPGA Device, a Case for DCCN
4.3. Connecting the FPGA to the Circuit
Board
This step involves using wires to connecttheFPGA and the
correspondingcomponents on the circuit board. Since the
FPGA board is quite large, it cannot besoldered on the circuit
board like other smaller component. Another test
orinspection is done to ensure that there are no tampered
connections or damageduring soldering of the FPGA wires.
Casing: The followingwere accomplishednamely:
- The circuit board is gently placed into the casing.
- Wires are connected to sockets and contactors.
- Nails are used to fasten the heavy transformers and
contactors.
- Sockets are mounted onto the casing using screws.
- Tapes are used to hold the circuit boards and FPGA
down to the base ofthe board (as fasteners).
- Wires are routed neatly within the casing and held
together using tapes.
- Wires leaving the casing are routed through one
direction andheldtogether using tapes.
- The casing is finally covered.
- LEDs are connected to the holes in the top of the
casingto indicate power in each of the phases.
Fig 16 illustrates the snapshots showing LED connections
to the casing lid. Fig17 explains the snapshots forthe soldered
components. Fig 18 and Fig 19 show the design prototypes in
this work.
Fig. 16. Snapshots showing LED connections to the casing lid.
Fig. 17. Snapshots for the soldered components
International Journal of Energy Policy and Management 2015; 1(1): 20-32 31
Fig. 18. DIP System prototype with Open lid
Fig. 19. DIP Final Prototype with Closed lid.
4.4. CloudDIP Testing and Recording of
Results
A final system test was carried outto ensure that the entire
system is workingproperly according to design. This makes it
easier for reading data. The following was observed:
i. The system has a switching time of less than 1sec.
ii. There is no output when there is no input from any of
the phases.
As such, the system offered satisfactorily test results.
5. Conclusion and Recommendation
This research is an extension on the earlier work on
SGEMS DCCN. Though the emphasis was on automating
changeover system of DCCN using FPGA, the work
developed CloudDIP system which is based on the high
switching speed FPGA for DCCN design. Various tests were
carried out and the results demonstrate that the CloudDIP is
feasible for production datacenter environments. The system
worked according to specification and offered satisfactory
results. The CloudDIP system is relatively affordable and
reliable. It is easy to operate, and it provides a high level of
power supply when there are power outages. Finally, this
system can considerable reduces stress associated with
manual change-over. This paper argues that the FPGA offers
a better replacement for microcontrollers based changeover
systems. This work will facilitate research in reliable
switching technologies for automatic changeover system and
other related embedded products. FPGA is highly capable of
incorporating more functions such as voltagemonitoring,
starting up the auxiliary power supply, LED displays and
alarms. Future work will focus on introducing expert agents
that will carry out signal sensing from thebackup generators
to theutility. This will also take care of sensing input from the
generator while sending a signal to start up thegenerator.
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