Chapter 6. Dataflow Modeling

Continuous AssignmentsThe left hand side always be a scalar or vector

net or a concatenation of scalar and vector nets. It cannot be a scalar or vector register.

Continuous assignments are always active.

right-hand side can be registers or nets or function calls.

Delay values can be specified for assignments in terms of time units. It is very useful in modeling timing behavior in real circuits.

Example 6-1 Examples of Continuous Assignment

Implicit Continuous Assignment

Regular Assignment Delayassign #10 out = in1 & in2; // Delay in a

continuous assign

Net Declaration Delay

Expressions

Operands

OperatorsOperator Type

Operator Symbol

Operation Performed

Number of Operands

Arithmetic */+-%**

multiplydivideaddsubtractmoduluspower (exponent)

twotwotwotwotwotwo

Logical !&&||

logical negationlogical andlogical or

onetwotwo

Relational ><>=<=

greater thanless thangreater than or equalless than or equal

twotwotwotwo

Equality ==!====!==

equalityinequalitycase equalitycase inequality

twotwotwotwo

OperatorsOperator Type Operator Symbol Operation Performed Number of OperandsBitwise ~

&|^^~ or ~^

bitwise negationbitwise andbitwise orbitwise xorbitwise xnor

onetwotwotwotwo

Reduction &~&|~|^^~ or ~^

reduction andreduction nandreduction orreduction norreduction xorreduction xnor

oneoneoneoneoneone

Shift >><<>>><<<

Right shiftLeft shiftArithmetic right shiftArithmetic left shift

TwoTwoTwoTwo

Concatenation { } Concatenation Any numberReplication { { } } Replication Any numberConditional ?: Conditional Three

If any operand bit has a value xin1 = 4'b101x; in2 = 4'b1010; sum = in1 + in2; // sum will be evaluated

to the value 4'bx

Logical operators

Equality Operators

// A = 4, B = 3 // X = 4'b1010, Y = 4'b1101 // Z = 4'b1xxz, M = 4'b1xxz, N = 4'b1xxx A == B // Results in logical 0 X != Y // Results in logical 1 X == Z // Results in x Z === M // Results in logical 1 (all bits match, including x and z) Z === N // Results in logical 0 (least significant bit does not

match) M !== N // Results in logical 1

Bitwise OperatorsBitwise operators are negation (~), and(&),

or (|), xor (^), xnor (^~, ~^).

Logical operators perform a logical operation// X = 4'b1010, Y = 4'b0000 X | Y // bitwise operation. Result is 4'b1010 X || Y // logical operation.

Equivalent to 1 || 0. Result is 1.

Reduction OperatorsReduction operators are and (&), nand

(~&), or (|), nor (~|), xor (^), and xnor (~^, ^~).

perform a bitwise operation on a single vector operand and yield a 1-bit result.

Shift OperatorsShift operators are right shift ( >>), left

shift (<<), arithmetic right shift (>>>), and arithmetic left shift (<<<).

Concatenation Operator

Replication Operator

Conditional Operator

Operator PrecedenceOperators Operator

SymbolsPrecedence

Unary + - ! ~ Highest precedence

Multiply, Divide, Modulus

* / %

Add, Subtract + - Shift << >> Relational < <= > >= Equality == != === !== Reduction &, ~&

^ ^~|, ~|

Logical &&||

Conditional ?: Lowest precedence

4-to-1 Multiplexer, Using Logic Equations

4-to-1 Multiplexer, Using Conditional Operators

4-bit Full Adder, Using Dataflow Operators

4-bit Full Adder with Carry Lookahead