Post on 03-Feb-2016
description
Ch.3 Overview of Standard Cell Design
TAIST ICTES ProgramVLSI Design Methodology
Hiroaki Kunieda
Tokyo Institute of Technology
4.1 Design Style
Design Method
Standard Design --------- Design by maker’s spec.
Full Custom Design ------ Design of all masks by customer’s spec.
Manual Design Cell-Based Design
Custom Cell/ Full Custom Design Standard Cell Design
Semi Custom Design ----- Design of routing wire & logic functions by customer’s spec.
Gate Array FPGA Design
Standard Cell Design
Design Using Standard Cell, pre-design by professionals.
Cells includes Verilog, Circuit, Layout Information for NAND, NOR, D-FF
Logic Design and Layout Design done by CAD. Logic Design --- by use of Cells with specified delays Layout Design – by use of Cells
Generated Data is mainly interconnection wires.
List of Standard Cells Inverter Inverting Buffer Non-inverting Buffer Tri-state Non-inverting
Buffer AND 2, 3, 4 inputs NAND 2,3,4 inputs OR 2, 3, 4 inputs NOR 2,3,4 inputs XNOR 2,3 inputs AND-OR AND-OR-Inverter OR-AND OR-AND-Inverter Multiplexer 2 to 1 Multiplexer 4 to 1
Decoder 2 to 4 Half Adder 1bit Full Adder 1bit
Pos Edge DFF Neg Edge DFF Scan Pos Edge DFF Scan Neg Edge DFF RS NAND Latch High-Active Clock Gating Latch Non-inverting Delay line Pass Gate Bidirectional Switch Hold 0/1 Isolation Cell
Standard Cell DesignLogic gates, latches, flip-flops, or larger logic
Routingchannels
Layout
Place & Rout
Standard Cell Library
Circuit description at RTL level Layout description in GDSII format TLF Format Data
Logical information Transistor and interconnect parastics Spice netlist Power information Process, temperature and supply
voltage
4.2 Cell
Library Design Flow I
Layout DesignMask Data
GDSII
Abstract Generator
Extraction
Analog Environment
Library DataLEF
Circuit DataNetlist
Circuit DataTLF
I/O delay pathsTiming check valuesInterconnect delays
Cell InformationTechnology information
Library Design Flow II
Physical Layout (gdsII, Virtuoso Layout Editor)Should follow specific design standards eg. constant height, offsets etc.
Logical View (verilog description or TLF)Verilog is required for dynamic simulation. Place and route tools usually can use TLF. Verilog description should preferably support back annotation of timing information.
Abstract View (Cadence Abstract Generator, LEF)LEF: Contains information about each cell as well as technology information
Timing, power and parasitics (TLF)Transistor and interconnect parasitics are extracted using Cadence or other extraction tools (SPACE). Spice or Spectre netlist is generated and detailed timing simulations are performed. Power information can also be generated during these simulations. Data is formatted into a TLF file including process, temperature and supply voltage variations.
Library Exchange Format (LEF)
An ASCII data format, used to describe a standard cell library includes the design rules for routing and the Abstract of the cells, no information about theinternal netlist of the cells
1.Technology: layer, design rules, via definitions, metal capacitancea. type: Layer type can be routing, cut (contact), masterslice (poly,
active), overlap.b. width/pitch/spacing rulesc. directiond. resistance and capacitance per unit squaree. antenna Factor
2. Site: Site extension3. Macros: cell descriptions, cell dimensions, layout of pins and blockages, capacitances.
Timing Library Format (TLF)
TLF is an ASCII representation of the timing and power parameters associated with any cell in a particular semiconductor technology. The timing and power parameters are obtained by simulating the cells under a variety ofconditions and the data is represented in the TLF format 、
The TLF file contains timing models and data to calculate
1. I/O delay paths
2. Timing check values
3. Interconnect delays
Standard Cell I
Standard Cell II
Layout
Cell Design Flow
Synopsys Design Compiler
Cadence Design Planner
Cadence Silicon Ensemble
Cadence ICFB
Modelsim
VHDL Model
Verilog Model
DEF File
DEF File
Verilog Model
VHDL -> VerilogConversion
Standard Cell Placement
Standard Cell Routing
Export to Other Formats,SPICE Verification
Verilog Verification
Layout Condition
parameter Symbol value figure
Cell height H 36λ 900 nm
Power rail width
W1 2λ 50 nm
Vertical grid W2 4λ 100 nm
Horizontal gird W3 4λ 100 nm
Nwell height W4 20λ+α 525 nm
45 nm Process (λ=25nm, Minimum wire width=2λ)
7/31/2001 WLT
DC Characteristic
slope -1
slope -1
VOHMIN
VOLMAX
VIHMINVILMAX
Low
VOHMIN
High
VOLMAX
Propagation Delay with loads
4.2 LSI Design Procedure
Logic Design
Functional Verification
Logic Synthesis
Scan Path Design
RTL SimulationRTL
Synthesis Netlist
Scan Netlist Timing Analysis
Functional Verification
Layout Design
Gate Level Simulatior
Layout Design
Netlist
Mask Data
Layout Netlist
DRC/LVS
Functional Verification
ATPG
TestPattern