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library ieee;

use ieee.std_logic_1164.all;

entity divider is

port (St, Clk: in std_logic;

dend: in std_logic_vector(7 donto !";

dsor: in std_logic_vector(# donto !";

v: out std_logic;$ent: out std_logic_vector(# donto !"

%e&:out std_logic_vector(# donto !"";

end divider;

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arc'itecture be' o divider is

signal C, S', su, )d: std_logic;

signal *end%: std_logic_vector(+ donto !";

signal *sor%: std_logic_vector(# donto !";

signal Sub: std_logic_vector(4 donto !";

signal State, nState: integer range ! to 6;begin

Sub - /dd4 (*end%(+ donto 4", 0! 2 not(*sor%", 01";

C-sub(4";

3ent-*end%(# donto !";

%e&-*end%(7 donto 4";

rocess (state, st, C"

5egin

- 0!; S'- 0!; Su-!; )d-!;

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Case state is

'en !8 i (St1" t'en )d-1; nState-1;

9lse nstate-!; end i;

'en 18 i(C1" t'en -1; nstate-!;

9lse S'-1; nState-; end i;

'en 8 i (C1" t'en Su-1; nstate-State;

9lse S'-1; nstate-state 1; end i;

'en # 8 i (C1" t'en Su-1; nstate-State;

9lse S'-1; nstate-state 1; end i;

'en 4 8 i (C1" t'en Su-1; nstate-State;

9lse S'-1; nstate-state 1; end i;

'en < 8 i (C1" t'en Su-1; nstate-State;

9lse S'-1; nstate-!; end i;

end case;

end process;

(C "

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process (Clk"

begin

i (Clk1 and Clkevent" t'en

state-nState;

i ()d1" t'en

*end%-! 2 dend;*sor%-dsor;

end i;

= (S'1" t'en

*end%- *end% (7 donto !" 2 0!;

end i;

= (Su1" t'en*end%(+ donto 4" -sub(4 donto !";

*end%(!"-1;

end i;

9nd i;

9nd process;

9nd divider;

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C t l Si l f Si d Di id

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Control Signals for Signed Divider LdU Load upper half of dividend from busLdL Load lower half of dividend from busLds Load sign of dividend into sign flip-flopS Sign of dividendCm1 Complement dividend register (2's complement)Ldd Load divisor from bus

Su Enable adder output onto bus (Ena) and load upper half of dividend from busCm2 Enable complementer (Cm2 equals the complement of the sign bit of the divisoso that a positive divisor is complemented and a negative divisor is not)Sh Shift the dividend register left one place and increment the counterC Carr! output from adder ("f C # $ the divisor can be subtracted from the upperdividend%)St StartV &verflow

Qneg uotient will be negative (neg # $ when sign of dividend and divisor aredifferent)

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entity sdiv isport(ClSt in bit*+bus in bit,vector($ downto .)* uotient outbit,vector($ downto .)*/ 0d! out bit)*end sdiv*

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architecture Signdiv of Sdiv is

constant 1ero,vector bit,vector($ downto .)#(others#3'.')*signal State integer range . to 4* signal Count integer range . to$*signal SignC5C bit* signal +ivisorSumCompout bit,vector($downto .)*signal +ividend bit,vector($ downto .)*alias bit,vector($ downto .) is +ividend($ downto .)*alias 6cc bit,vector($ downto .) is +ividend($ downto $4)*

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begin -- concurrent statementscompout 7# divisor when divisor($) # '$' -- $'s complementerelse not divisor*6ddvec(6cccompoutnot divisor($)SumC$4)* -- $4-bit adderuotient 7# * 0d! 7# '$' when State#. else '.'*

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processbeginwait until Cl # '$'* -- wait for rising edge of cloccase State iswhen .#3if St # '$' then6cc 7# +bus* -- load upper dividendSign 7# +bus($)* State 7# $*

/ 7# '.'* Count 7# .* -- initiali1e overflow88 initiali1e counterend if *

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when $#3 7# +bus* State 7# 2* -- load lower dividendwhen 2#3+ivisor 7# +bus*if Sign #'$'then -- two's complement +ividend if necessar!addvec(not +ividend1ero,vector'$'+ividend5C2)*end if * State 7# *

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when #3

+ividend 7# +ividend(. downto .) 9 '.'* -- left shiftCount 7# Count:$* State 7# ;*when ; #3if C #'$' then -- Cv 7# '$'* State 7# .*else -- C'+ividend 7# +ividend(. downto .) 9 '.'* -- left shiftCount 7# Count:$* State 7# *

end if *

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when #3

if C # '$' then -- C6CC 7# Sum* -- subtract(.)7# '$'*else+ividend 7# +ividend(. downto .) 9 '.'* -- left shiftif Count # $ then -- <C'count7# .* State 7# 4*else Count 7# Count:$*

end if *end if *

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when 4#3if C # '$' then -- C

6cc 7# Sum* -- subtract(.) 7# '$'*else if (Sign xor +ivisor($))#'$' then -- C'negaddvec(not +ividend1ero,vector'$'+ividend5C2)*end if * -- 2's complement +ividendstate 7# .*end if *end case*end process*end signdiv

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