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Berkeley Wireless Research CenterA Partnership of UC Researchers, Industry, and Government

Industry Members–Intel Corporation–STMicroelectronics–Infineon Technologies –Hitachi Ltd–Sun Microsystems–Cisco Systems–Agilent Technologies–Conexant Systems–Cadence Design Systems–Ericsson Radio Systems

–Atmel Corporation–Qualcomm Incorporated–Philips Research–NEC Corporation–Samsung Electronics–Xilinx Incorporated–Fujitsu Laboratories–Marvell Semiconductor–Synopsys, Inc–Toshiba Corporation–Texas Instruments

Radio SoC Implementation

BWRC Operating Model• Members Participate

– Best of academic and industrial research– Resident researchers, part of research team

• Research Focus– Pre-competitive: >5 years out– Determine relationship between theoretical

and algorithmic advances for Radio SoC Implementation– Understand tradeoffs between various implementation architectures with

respect to performance, power and cost• Open IP

– Results move quickly to the Public Domain: http://bwrc.eecs.berkeley.edu/• Realistic prototype/test environment

– Realize proof-of-concept prototypes using rapid design flow from algorithm to implementation

– STMicroelectronics, TSMC and IBM foundry• 130 nm and 90 nm CMOS, SiGe BiCMOS

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The BWRC Research Agenda

Range

Dat

a R

ate

1m 10m 100m 1km 10km

1Kb

10Kb

100Kb

1Mb

10Mb

100Mb

Cellular (WAN)

3G Cellular

2.5 G Cellular

802.11 (LAN)

802.1a

Bluetooth (PAN)

Sensor networks

Metropolitan

Zigbee (PAN)

The Wireless ArenaThe Wireless Arena

More bits/secMore bits/sec

Cheap

er bi

ts

Cheap

er bi

ts Improving Spectrum Utilization• Exploring new spectrum: 60 GHz• Re-cycling spectrum: Cognitive • Underlay spectrum: UWB

Improving Spectrum UtilizationImproving Spectrum Utilization• Exploring new spectrum: 60 GHz• Re-cycling spectrum: Cognitive • Underlay spectrum: UWB

Ubiquitous embeddedwireless• Ultra-low cost• Ultra-low power • Small size

Ubiquitous embeddedUbiquitous embeddedwirelesswireless• Ultra-low cost• Ultra-low power • Small size

BWRC Topical Focus

Improving SpectrumUtilization

Improving SpectrumUtilization

Ubiquitous Imbedded Wireless

Ubiquitous Imbedded Wireless

Comm. AlgorithmsSignal Processing

Architectures

Low Power Systems Protocols, Networking

Statistical Design

Circuits:• RF/mm-Wave and • Low power Digital• A/D, D/A

Design Methodology/Flows

Test Beds: BEE, MIMO Prototype Chips

Reconfigurable Computing

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Outline

• BWRC Research Focus and operating Model• Spectrum Utilization, Bob Brodersen, Ali Niknejad

– Exploiting new spectrum: 60 GHz CMOS Radios– Exploiting un-used spectrum: Cognitive radios– Underlay spectrum: UWB

• Low energy sensor networks, Jan Rabaey, Paul Wright• Analog and digital circuits, Bora Nikolic• Reconfigurable computing, John Wawrzynek

1 mm

1.3 mm

World’s First 60 GHz CMOS LNA!

• Developed a design methodology that gives repeatableresults for microwave CMOS design

• Best Paper award at 2004 ISSCC• Challenges: Power, Noise, Antennas, Packaging

11-dB Gain@ 60 GHz

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60 GHz CMOS Front End

• 7 dB conversion gain, 130 nm CMOS• Next generation in fab

Adaptive Beamforming Directivity• High gain in any direction, controlled electronically.• Spatial selectivity for receive gain and attenuate

interferers

Can influence manychannel parameters.

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RF Phase Shifter Architecture

s(t) a0a0

a1

a2

Σ

r(t)

a1

a2

• 130 nm CMOS• Fab complete and in testing• Bonded to LTCC Substrate with patch antennas

4-Way Phase Shifter Chip

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Outline

• BWRC Research Focus and operating Model• Spectrum Utilization, Bob Brodersen, Ali Niknejad

– Exploiting new spectrum: 60 GHz– Exploiting un-used spectrum: Cognitive radios– Underlay spectrum: UWB

• Low energy sensor networks, Jan Rabaey, Paul Wright• Analog and digital circuits, Bora Nikolic• Reconfigurable computing, John Wawrzynek

The Spectrum Shortage….

• All frequency bands up to 60 GHz (and beyond) have FCC allocations for multiple users

• The allocation from 3-6 GHz is typical - seems very crowded….

3 4 5 6 GHz

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Reality…

• Even though the spectra is allocated it is almost unused • Cognitive Radios could allow unlicensed users to share the

spectrum with primary users• FCC has authorized experimental CR in TV-UHF but higher

frequencies are even more attractive

0 1 2 3 4 5 6 GHz

TV-UHFband

Cognitive Radio: What is it? • BWRC Workshop, November 1, 2004

http://bwrc.eecs.berkeley.edu/Research/MCMA/• Definition: “A cognitive radio (CR) is a radio that can

change its transmitter parameters based on interaction with the environment in which it operates”[FCC NPRM � ������, Dec ��th, ����]

• Cognitive radio properties:– Sensing: RF technology that "listens" to huge swaths of

spectrum – Cognition: Ability to identify primary users– Adaptation : Ability to change power levels, frequency

ranges, modulation parameters to best use white spaces and minimize interference to primary users

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Signal Processing for Spectrum Sensing

• Improvement in sensitivity through signal processing gain Matched filter-optimal, maximizes SNR-coherent detector, even demod.-needs pilot, preamble, synch, etc.

Energy detector-sub-optimal, non-coherent-gain proportional to N and T-susceptible to noise and interference-does not differentiate signals

Feature detector-exploits modulated signalstructure i.e. periodicity-cyclostationary approach based on spectral correlation

Special receiver for every Primary User

CR Test Bed System Components

Fiber connection

Power, LO and CLK generation and distributionBEE / BEE2

RF Modem

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Outline

• BWRC Research Focus and operating Model• Spectrum Utilization, Bob Brodersen, Ali Niknejad

– Exploiting new spectrum: 60 GHz– Exploiting un-used spectrum: Cognitive radios– UWB: underlay spectrum

• Low energy sensor networks, Jan Rabaey, Paul Wright• Analog and digital circuits, Bora Nikolic• Reconfigurable computing, John Wawrzynek

The Lure of UWB

Conventional Integrated Narrowband Transceiver:

UWB “Mostly Digital” Radio:

D/A

I

QMIXERLNA

PA

A/D

A/D

DIGITAL:

F SYNTH

ANALOG:

MIXERD/A

D/A

ILNA

PA

A/D

DIGITAL:

ANALOG:

• Low Cost• Simplicity• Integration

• Low Power• High Throughput• Ranging• Unlicensed Operation• Coexistence

UWB Promises:

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Chip Plot:

2.8 x 4.7 mm2 (13.2 mm2) fab complete in testing

Outline

• BWRC Research Focus and operating Model• Spectrum Utilization, Bob Brodersen, Ali Niknejad

– Exploiting new spectrum: 60 GHz– Exploiting un-used spectrum: Cognitive radios– Underlay spectrum: UWB

• Low energy sensor networks, Jan Rabaey, Paul Wright• Analog and digital circuits, Bora Nikolic• Reconfigurable computing, John Wawrzynek

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The Research Agenda

Ultra low power transceiver nodesTX/RX – Mixed signal – Digital – Clocks - Power

Ad-hoc network service layers

Ad-hoc wireless protocol stacks

Dem

andR

esponse

Tire Pressure

Monitoring

Spradios

Consum

erH

ome N

etworks

•• Towards easily deployableTowards easily deployable, , robustrobust, , selfself--configuring ubiquitous configuring ubiquitous wireless networkswireless networks that are that are Energy SelfEnergy Self--SufficientSufficient

•• Energy, cost and size Energy, cost and size optimizationoptimization at all levelsat all levels of abstraction of abstraction •• Explore the limits!Explore the limits!

The “PicoCube”

Advanced packaging the only real answer to mm3 nodes

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Passive 1.9GHz Receiver

(B. Otis, N. Pletcher)

• PRX=200nW• BW-3dB=4MHz• Sensitivity=-38dBm (12dB SNR)• |S11|: -9.3dB

Digitally-Tuned 100µW Oscillator

-115dBc/HzPhase noise@ 1MHz offset

~200kHz(10 bits eff.)

Resolution150MHzTuning Range

1.9GHzNominal frequency

100µWPowerconsumption

0.5VSupplyvoltage

Measured bondwire oscillator performance

0.13µm ST CMOS, (2x2)mm2 area

One bondwire and one integrated version implemented for comparison

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Injection-Locked Transmitter

Input balun

Output balun

Bond wire inductor

CMOS Die1mm

ST 130nm CMOS

Injection-locking devices

Broad & noisy free running spectrum

Clean and stable carrier after locking

Y. H. Chee, A. M. Niknejad, J. Rabaey, “An Ultra-Low Power Injection Locked Transmitter for Wireless Sensor Networks,” 2005 CICC

RF Output

Baseband Data

20µs

50 kbpson-off keying modulated data

Achieves overall TX efficiency of 32% @ 0 dBmoutput power

Low voltage operation

Low Voltage/Low Power SAR ADC

.5VVdd

<5uWPd

6 bitsResolution

1MS/sFs

Use high-metal layers cap to get lower density (mismatch limitation).

(S. Gambini, L. Wang)

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Mixed-Signal Baseband• Chip area ~ 2.0 mm2 in 0.13µm

CMOS • Power consumption

(for data rate ~ 50kbps)– 1V supply, 193 µW

Data Input

Reset 1

Data Output

Integrator_1 Out

(Yanmei Li)

LP Memory Standby – the Potential of ECC

Nor

mal

ized

pow

er p

er b

it

420

340

280

0 0.1 0.2 0.3 0.4

fraction of errors

DRV – Data retention voltage • Worst-case design wasteful• LV-operation needs robustness

SRAM

coded-data

ECC

datain

Optimize

Power per bit = DRV 2encoded bits

useful bits

Results• 5X asymptotic power savings• 2X-5X power-savings with

ECC energy consumptionincluded (long block codes)

(A. Kumar, H. Qin)

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Outline

• BWRC Research Focus and operating Model• Spectrum Utilization, Bob Brodersen, Ali Niknejad

– Exploiting new spectrum: 60 GHz– Exploiting un-used spectrum: Cognitive radios– Underlay spectrum: UWB

• Low energy sensor networks, Jan Rabaey, Paul Wright• Analog and digital circuits, Bora Nikolic• Reconfigurable computing, John Wawrzynek

Background-Calibrated ADC

VinPipelined

ADCAdap.Digital

Filter Dout

S/H

↓n

Σ/∆ADC

Coeff.Update

fclk/n

fclk

Analog Digital

FIR filter

• High speed ADC calibration by high accuracy ADC by adaptive FIR filter (channel equalizer)

• Speed + Accuracy enabled simultaneously• 12 bits, 400MSps, <500mW (analog) in .13µ CMOS• First Si early ‘06

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OPTIMAL POWER – PERFORMANCE TRADEOFF CURVE

Power – Performance Optimization

Cycle time

Pow

er Initial designPower-optimal design

Design within power budget

• How to find the best performance under the power budget

Power budget

Circuit Optimization Framework

Optimizer

(Matlab)Design Variables

Cycle time, PowerStatic timer

(C++)

Models Netlist Optimization Goal

Optimal Design

Plug-ins

Results

Optimization Core

Variables

Radu Zlatanovici

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64-Bit Adder• ST 90nm 7M 1P

technology VDD= 1V• 200ps adder delay• 7 chips tested:

– Fastest: 4.9 GHz• 350 mW @ 4.6 GHz

worst case• Additional measurement

circuitry to study impact of supply noise** With Elad Alon, Valentin

Abramzon, Mark Horowitz (Stanford)1.7

mm

1.6

mm

Radu Zlatanovici, Sean Kao

Outline

• BWRC Research Focus and operating Model• Spectrum Utilization, Bob Brodersen, Ali Niknejad

– Exploiting new spectrum: 60 GHz– Exploiting un-used spectrum: Cognitive radios– Underlay spectrum: UWB

• Low energy sensor networks, Jan Rabaey, Paul Wright• Analog and digital circuits, Bora Nikolic• Reconfigurable computing, John Wawrzynek

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Berkeley Emulation Engine (BEE)• Designed for real-time

hardware emulation but used for a variety of computations.

– Up to 600 Gops (16-bit adds)

• Matlab/Simulink Programming Tools:

Discrete-Time-Block-Diagrams with FSMs– Probably the first successful

convenient programming model for FPGA based computing systems.

– Programming/Design methodology enables automatic FPGA programming and ASIC generation from single specification.

20 Xilinx VirtexE 2000 chips, 16 1MB ZBT SRAM chips.

Completed year 2002

BEE2 Prototype Compute Module

14X17 inch 22 layer PCB

Module also includes I/O for administration and maintenance:

– 10/100 Ethernet

– HDMI / DVI

– USB

1.5-2 TOPS

Completed 12/04.

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BEE2 Analog Interface• Use IBOB to fan-out the serial

Infiniband/Enet connections to parallel LVDS/LVPEL signals

• IBOB can be connected to BEE2 modules or directly to Infiniband/Ethernet switches

• Built-in support to connect to the Mark-V disk array archiver

Applications Areas• Communication systems development

– Architectural exploration for future radio SoC’s – Emulation of SoCs, performance evaluation– Emulate large wireless Ad-Hoc sensor networks– Algorithms for SDR and Cognitive radio

• CAD acceleration– Full Chip Transistor-Level Circuit Simulation (Xilinx)– FPGA Place & Route– OPC / Mask Generation

• High-performance online DSP– SETI Spectroscopy, ATA / SKA Image Formation– Hyper-spectral Image Processing

• Scientific computation and simulation– E & M simulation for antenna design– Fusion simulation– Weather / Climate

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Radio Astronomy Collaboration

Requirements of Radio Astronomy Antenna Array Processing:Massive arithmetic operations per second requirement.“Stream-based” computation model

Usually hard real-time requirementHigh-bandwidth data I/OFew control branches

Low numerical precision requirementsMostly fix-point operationsRarely needs reduced floating point

Past systems have been: Ad hoc, fixed function, designed on a per telescope and per experiment basis, fully synchronous communication.

BEE2 is general purpose, scalable, and packet based, leveraging commodity switches.

BEE2 is gaining momentum as future computing platform for Allen Telescope Array (ATA), the proposed Square Kilometer Array (SKA), and other telescopes.(Image-formation, SETI spectroscopy, etc.)

SETI Spectrometer

BPF4 ch

128 tap

8 Gbps

16 Gbps Report

PFB8K ch

64K tap

CT8K,32K

FFT32K

Power SpectrumThreshold

PFB8K ch

64K tap

CT8K,32K

FFT32K

Power SpectrumThreshold

PFB8K ch

64K tap

CT8K,32K

FFT32K

Power SpectrumThreshold

PFB8K ch

64K tap

CT8K,32K

FFT32K

Power SpectrumThreshold

• Target: 0.7Hz channels over 800MHz 1 billion Channel real-time spectrometer

– Results: • One BEE2 module meets

target and yields 333GOPS (16-bit mults, 32-bit adds), at 150Watts (similar to desk-top computer)

• >100x peak throughput of current Pentium-4 system on integer performance, & >100x better throughput per energy.

– Current implementation is 64K channels.

March workshop in Hat Creek / ATA

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Conclusion• Center in operation for 6 years

– Established public domain research model– Refined industry-academia collaborative research model– Expanded Membership from 7 to 17– 60 Graduate Students– 12 Faculty

• World Class Research Results:– Semi-annual research retreats: January in Monterey, June in Lake Tahoe– Website: http://bwrc.eecs.berkeley.edu/

• Established infrastructure to support world class wireless SOC research– CAD tools and automated design flows – BEE Emulation Engine in use– Laboratory for prototype testing

• Over 80 graduate degrees earned, 65% PhD