Post on 26-Jun-2020
Single Stage Amplifiers
• Basic Concepts • Common Source Stage • Source Follower • Common Gate Stage • Cascode Stage
Hassan Aboushady University of Paris VI
• B. Razavi, “Design of Analog CMOS Integrated Circuits”,
McGraw-Hill, 2001.
References
H. Aboushady University of Paris VI
Single Stage Amplifiers
• Basic Concepts • Common Source Stage • Source Follower • Common Gate Stage • Cascode Stage
Hassan Aboushady University of Paris VI
Basic Concepts I
H. Aboushady University of Paris VI
• Amplification is an essential function in most analog circuits !
• Why do we amplify a signal ?
• The signal is too small to drive a load • To overcome the noise of a subsequent stage • Amplification plays a critical role in feedback systems
In this lecture: • Low frequency behavior of single stage CMOS amplifiers: • Common Source, Common Gate, Source Follower, ...
• Large and small signal analysis. • We begin with a simple model and gradually add 2nd order effects
• Understand basic building blocks for more complex systems.
Approximation of a nonlinear system
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212
210 )(...)()()( xxxtxtxtxty nn ≤≤++++≈ αααα
)()( 10 txty αα +≈
Input-Output Characteristic of a nonlinear system
In a sufficiently narrow range:
where α0 can be considered the operating (bias) point and α1 the small signal gain
Analog Design Octagon
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Single Stage Amplifiers
• Basic Concepts • Common Source Stage • Source Follower • Common Gate Stage • Cascode Stage
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Taking Channel Length Modulation into account
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outDOm VRrVg −=)//(1
inVV =1
)//( DOmin
outv RrgVVA −==
Calculating Av starting from the Small Signal model:
CS Stage with Current-Source Load
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)//( 21 OOmv rrgA −=
• Both transistors operate in the saturation region:
General expression to calculate Av by inspection
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Gm : the transconductance of the circuit when the output is shorted to grounded.
outmRGAv −=
Lemma:
Rout : the output resistance of the circuit when the input voltage is set to zero.
CS with Source Degeneration
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Dmv RGA −=Sm
Dmv Rg
RgA+
−=1
Small Signal model:
Sm
m
in
Dm RVgV
VgVIG
11
1
+==
Sm
mm Rg
gG+
=1
Voltage Gain of Degenerated CS
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)( 1 BSmbmD
outr VgVg
RVI
O+−−=
])([D
Soutmb
D
Soutinm
D
outr R
RVgRRVVg
RVI
O++−−=
D
outRR R
VIISD==
VS
D
SoutS RRVV −=
The current through rO :
SD
outOrout R
RVrIV
O−=
D
SoutO
D
Soutmb
D
SoutinmO
D
outout R
RVrRRVg
RRVVgr
RVV −++−−= ])([
OSmbmOSD
DOm
in
out
rRggrRRRrg
VV
)( ++++−=
Small Signal model including body effect & channel length modulation:
Gm of Degenerated CS
H. Aboushady University of Paris VI
Small Signal model including body effect and channel length modulation:
O
SoutSoutmbSoutinm
O
XXmbmout
rRIRIgRIVg
rVVgVgI
−−+−=
−−=
)()(
1
OSmbmS
Om
in
outm rRggR
rgVIG
])(1[ +++==
Output Resistance of Degenerated CS
H. Aboushady University of Paris VI
SX RIV −=1
XSmbmX
mbmX
IRggIVggI
)()( 1
++=
+−The current flowing in rO :
SXXSmbmXOX RIIRggIrV +++= ])([
SSmbmOX
Xout RRggr
IVR +++== ])(1[
OSOmbmout rRrggR +++= ])(1[
OSOmbmout rRrggR ++≈ )( OSmbmout rRggR ])(1[ ++=
Single Stage Amplifiers
• Basic Concepts • Common Source Stage • Source Follower • Common Gate Stage • Cascode Stage
Hassan Aboushady University of Paris VI
Source Follower Voltage Gain
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Smbm
Sm
in
out
RggRg
VVAv
)(1 ++==
[ ][ ] Soutmboutinm
SBSmbmout
RVgVVgRVgVgV−−=
+=
)(1
mmb gg η=Since:
)1(1η+
≈Av
And for : 1>>SmRg
Small Signal Equivalent Circuit
Single Stage Amplifiers
• Basic Concepts • Common Source Stage • Source Follower • Common Gate Stage • Cascode Stage
Hassan Aboushady University of Paris VI
Common Gate Gain
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01 =+− inSD
out VRRVV
outinSD
outmbm
D
outO VVR
RVVgVg
RVr =+−⎟⎟
⎠
⎞⎜⎜⎝
⎛−−
−11
Small Signal Signal Equivalent Circuit
The current through RS is equal to -Vout / RD :
The current through rO is equal to -Vout / RD - gmV1 - gmbV1 :
outinSD
outin
D
Soutmbm
D
outO VVR
RVV
RRVgg
RVr =+−⎥
⎦
⎤⎢⎣
⎡⎟⎟⎠
⎞⎜⎜⎝
⎛−+−
− )(
Common Gate Gain
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DSOmbmOSD
OmbmvCG R
RrggrRRrggA
)(1)(
++++
++=
DSOmbmOSD
OmvCS R
RrggrRRrgA
)( ++++−=
Common Gate Amplifier:
Degenerated Common Source Amplifier:
Single Stage Amplifiers
• Basic Concepts • Common Source Stage • Source Follower • Common Gate Stage • Cascode Stage
Hassan Aboushady University of Paris VI
Biasing of a Cascode Stage
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The cascade of CS stage and a CG stage is called “cascode”.
M1 : the input device M2 : the cascode device Biasing conditions: • M1 in saturation:
2GSbX VVV −=
12 THinGSb VVVV −≥−
2THXbXout VVVVV −−≥−
12 THGSinb VVVV −+≥
221 THGSTHinout VVVVV −+−≥
• M2 in saturation:
Cascode Stage Characteristics
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Large signal behavior: As Vin goes from zero to VDD For Vin < VTH M1 and M2 are OFF
Vout =VDD
21222 ])(1[ OOOmbmout rrrggR +++=
Output Resistance: • Same common source stage with a degeneration resistor equal to rO1
1222 )( OOmbmout rrggR +≈
• M2 boosts the output impedance of M1 by a factor of gmr02 • Triple cascode difficult biasing at low supply voltage.
↑↑outR
Cascode Stage Voltage Gain
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outmRGAv −=
1mm gG ≈
1222 )( OOmbmout rrggR +≈
11222 )( OmOmbmv rgrggA +≈
Ideal Current Source:
Cascode Current Source:
433122 // OOmOOmout rrgrrgR ≈
( )4331221 // OOmOOmmv rrgrrggA ≈
Folded Cascode
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Simple Folded Cascode
Folded Cascode with biasing
Folded Cascode with NMOS input
Output Resistance of Folded Cascode
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231222 )//]()(1[ OOOOmbmout rrrrggR +++=
1111 ])(1[ OSOmbmout rRrggR +++=
Degenerated Common Source Stage:
Folded Cascode Stage:
M1 M2 RS rO1 // rO3
Voltage Gain of Degenerated CS
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OSmbmOSD
DOm
in
out
rRggrRRRrg
VV
)( ++++−=
OSmbmOSD
OSmbmOSD
OSmbmS
Om
in
out
rRggrRRrRggrRR
rRggRrg
VV
)(])([
])(1[ ++++
+++
+++−=
The output resistance of a degenerated CS stage: OSmbmout rRggR ])(1[ ++=
The Transconductance of a degenerated CS stage:
( )Doutmin
out RRGVV //=
OSmbmS
Om
in
outm rRggR
rgVIG
])(1[ +++==
Estimating Gain by Inspection
H. Aboushady University of Paris VI
Sm
D
Sm
Dmv Rg
RRgRgA
+−=
+−=
/11
Example:
Path Source in the Resistance TotalDrain at theseen Resistance
−=Gain
21 /1/1 mm
Dv gg
RA+
−=
Differential Amplifiers
• Single Ended and Differential Operation • Basic Differential Pair • Common-Mode Response • Differential Pair with MOS loads
Hassan Aboushady University of Paris VI
• B. Razavi, “Design of Analog CMOS Integrated Circuits”,
McGraw-Hill, 2001.
References
H. Aboushady University of Paris VI
Differential Amplifiers
• Single Ended and Differential Operation • Basic Differential Pair • Common-Mode Response • Differential Pair with MOS loads
Hassan Aboushady University of Paris VI
The concept of Half Circuit
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If a fully symmetric differential pair senses differential inputs then the concept of half circuit can be applied.
• A differential change in the inputs Vin1 and Vin2 is absorbed by V1 and V2 leaving VP constant
Application of The Half Circuit Concept
H. Aboushady University of Paris VI
Since VP experiences no change, node P can be considered “ac ground” and the circuit can be decomposed into two separate halves
Dmin
X RgVV
−=1
Dmin
Y RgVV
−=2
Two common source amplifiers:
Dminin
YX RgVVVV
−=−
−
21
The Half Circuit Concept : Example
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Taking into account the output resistance (channel length modulation)
( )11
// ODmin
X rRgVV
−= ( )22
// ODmin
Y rRgVV
−=
Two common source amplifiers:
( )ODminin
YX rRgVVVV //
21
−=−
−
Cascode Differential Pair
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)//( OPONmNv rrgA =
Low gain 10 to 20.
To increase the gain: Cascode Differential Pair
)//( 7551331 OOmOOmmv rrgrrggA =
Current Source Load:
Operational Amplifiers
Hassan Aboushady University of Paris VI
• B. Razavi, “Design of Analog CMOS Integrated Circuits”,
McGraw-Hill, 2001.
References
H. Aboushady University of Paris VI
Operational Amplifier: Performance Parameters
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Gain: the open loop gain of an op-amp determines the precision of the feedback system employing the op-amp
Small Signal Bandwith: Unity-Gain freq., fu, and the 3dB freq., f3-dB.
Large Signal Bandwidth (slew rate): Op-Amp response to large transient signals.
Output Swing:
Linearity: non-linearity can be reduced by using a differential circuit and by increasing the open-loop gain in a feedback system
Noise and Offset: input noise and offset determine the minimum signal level that can be processed with reasonable quality.
Supply Rejection:
Single stage Op-Amps
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)//(0 OPONmN rrgA = 200 ≤A )//[( 220 OPmPONmNmN rgrggA =
)]([2 21 EGSSEGEGDD VVVV ++− )]([2 7531 EGSSEGEGEGEGDD VVVVVV ++++−
Simple: Cascode:
Small Signal Low Frequency Gain
Output Voltage Swing
Single stage Op-Amps
H. Aboushady University of Paris VI
Example: Design this amplifier (find all W/L as well as Vb1, Vb2 and Iref) with the following specifications:
200010nDissipatioPower
3SwingOutput alDifferenti3
0 =
=
=
=
AmW
VVVDD
Assume:
VVV
mLVV
VACVAC
THPTHN
eff
pn
oxp
oxn
7.0,0
5.0
2.0,1.0
/30
/60
11
2
2
===
=
==
=
=
−−
γ
µ
λλ
µµ
µµ
Folded Cascode Circuits
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The input device is replaced by the opposite type.
inoutmout VRgV 1=
More room to choose the different voltage levels.
The Idea:
Same Gain:
Advantage:
Folded Cascode Amplifier
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11 2III SS
SS +=
Biasing Current
Folded Cascode Cascode
SSI
Input Common-Mode
131, THGSbCMin VVVV +−< 131, THGSbCMin VVVV +−>
Folded Cascode Amplifier
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)]([2 9753 EGEGEGEGDD VVVVV +++−
Output Voltage Swing
Small Signal Gain
]//)//([ 977513310 OOmOOOmm rrgrrrggA ≈
Folded Cascode Amplifier
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Effect of Device capacitance on the nondominant pole in telescopic and folded cascode
1133 GDDBSBGStot CCCCC +++=
Folded Cascode Telescopic
55
1133
DBGD
GDDBSBGStot
CCCCCCC
++
+++=
Two-Stage OpAmp
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)//()//( 7553110 OOmOOm rrgrrgA ×≈
Small Signal Gain
)]([2 75 EGEGDD VVV +−
Output Voltage Swing
Frequency Response of Amplifiers
• General Considerations • Miller Effect • Association of Poles with Nodes
• Common Source Stage • Source Follower • Differential Pair
Hassan Aboushady University of Paris VI
• B. Razavi, “Design of Analog CMOS Integrated Circuits”,
McGraw-Hill, 2001.
References
H. Aboushady University of Paris VI
Miller Effect
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• Miller’s Theorem
vAZZ−
=11 12 1 −−
=vA
ZZX
Yv VVA =
• Proof
1ZV
ZVV XYX =
−
X
Y
VVZZ−
=1
1
2ZV
ZVV YXY =
−
Y
X
VVZZ−
=1
2
with we have
Example 1
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FsCZ 1=
)1( ACC Fin +=
AsCZ F
+=
1
1
1
• Calculate the input capacitance Cin:
should be calculated at the frequency of interest. X
Y
VVAv =
To simplify calculations we usually use low frequency value of Av.
Miller’s theorem cannot be used simultaneously to calculate input-output transfer function and the output impedance.
Association of Poles with Nodes
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inS
in
in
inS
inM CsR
sVsC
sCR
sVsV+
=+
=1
)(11)()(
PNinSin
out
CsRCsRA
CsRAs
VV
21
21
11
11)(
+++=
N
outN CsR
sVsV1
1
1)()(
+=
P
outP CsR
sVsV2
2
1)()(
+=
Vout1 Vout2
Association of Poles with Nodes
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PNinSin
out
CsRCsRA
CsRAs
VV
21
21
11
11)(
+++=
Vout1 Vout2
3 poles: each determined by the total capacitance seen from each node to ground multiplied by the total resistance seen at the node to ground
inSCR1
1 =ωNCR1
21
=ωPCR2
31
=ω
Example 2
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• Calculate the pole associated with node X:
The total equivalent capacitance seen from X to ground: )1( ACC FX +=
)1(11
ACRCR FSXSX +
==ωThe pole frequency:
Common Source Stage
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Neglecting channel length modulation and applying the Miller’s theorem on CGD , we have:
( ) GDvGSX CACC −+= 1The total capacitance at node X:
where, Dmv RgA −=
The total capacitance at the output node:
( ) GDDBGDvDBout CCCACC +≈−+= −11
The 1st pole frequency: ( )( )GDDmGSSp CRgCR ++=
11
1ω
The 2nd pole frequency: ( )GDDBDp CCR +=
12ω
Common Source Stage
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The transfer function:
Sources of error (approximation): • we have not considered the existence of zeros in the circuit • the amplifier gain varies with frequency
r0 and any load capacitance can be easily included.
⎟⎟⎠
⎞⎜⎜⎝
⎛+⎟
⎟⎠
⎞⎜⎜⎝
⎛+
−=
21
11)()(
pp
Dm
in
out
ssRg
sVsV
ωω
Common Source : “exact “ Transfer Function
H. Aboushady University of Paris VI
To obtain the exact transfer function:
Applying Kirchoff Current Law (KCL):
( ) 0=−++−
outXGDXGSS
inX VVsCVsCRVV
( ) 01=⎟⎟
⎠
⎞⎜⎜⎝
⎛+++− out
DDBXmXoutGD V
RsCVgVVsC
Common Source : “exact” 1st pole
H. Aboushady University of Paris VI
After some manipulations, we get:
( )( ) ( )[ ] 112 +++++++
−=
sCCRCRCRCRgRsRRRgsC
VV
DBGDDGSSGDSGDDmSDS
DmGD
in
out
ξ
DBGDDBGSGDGS CCCCCC ++=ξwith
Writing the denominator as: 11111
2121
2
11
+⎟⎟⎠
⎞⎜⎜⎝
⎛++=⎟
⎟⎠
⎞⎜⎜⎝
⎛+⎟
⎟⎠
⎞⎜⎜⎝
⎛+= ssssD
pppppp ωωωωωω
Assuming 21 pp ωω <<
( ) ( )DBGDDGSSGDSGDDmSp CCRCRCRCRgR +++++≈
11
1ω
Compare this result with ωin calculated using Miller’s Theorem
Common Source : “exact” 2nd pole
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( )( ) ( )[ ] 112 +++++++
−=
sCCRCRCRCRgRsRRRgsC
VV
DBGDDGSSGDSGDDmSDS
DmGD
in
out
ξ
having 111
2121
2
+⎟⎟⎠
⎞⎜⎜⎝
⎛++= ssD
pppp ωωωω
( ) ( )DBGDDGSSGDSGDDmSp CCRCRCRCRgR +++++≈
11
1ωand
DBGDDBGSGDGS CCCCCC ++=ξwith
12
11
pDSp RR ωξ
ω =then
( ) ( )( )DBGDDBGSGDGSDS
DBGDDGSSGDDmSp CCCCCCRR
CCRCRCRgR++
++++=
12ω
Comparison between “exact” and Miller’s theorem
H. Aboushady University of Paris VI
( ) ( )( )DBGDDBGSGDGSDS
DBGDDGSSGDDmSp CCCCCCRR
CCRCRCRgR++
++++=
12ω
( )( )GDDmGSSp CRgCR ++=
11
1ω
( )GDDBDp CCR +=
12ω
( )( ) ( )DBGDDGDDmGSSp CCRCRgCR ++++=
11
1ω
( ) ( )DBGDS
DGDDmGS CC
RRCRgCif +++>> 1
( )DBGDDBGSGDGSD
GSp CCCCCCR
C++
≈2ω
If
( )DBGDD CCR +
is negligible
exact
exact
Miller
Miller
1st pole:
2nd pole:
Common Source : transfer function zero
H. Aboushady University of Paris VI
After some manipulations, we get:
( )( ) ( )[ ] 112 +++++++
−=
sCCRCRCRCRgRsRRRgsC
VV
DBGDDGSSGDSGDDmSDS
DmGD
in
out
ξ
GD
mz C
g=ω
Stability and Frequency Compensation
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)(1)(
)()(
sHsH
sXsY
β+=
1)( =ωβ jH0180)( −=∠ ωβ jH
1)( −=ωβ jH
0180−Condition for oscillations
Bode Plot & Root Locus
H. Aboushady University of Paris VI
Bode Plot: (1) The slope of the magnitude plot changes by + 20 dB/dec at every zero frequency - 20 dB/dec at every pole frequency (2) For a pole (zero) frequency of ωm , the phase begins to fall (rise) at 0.1ωm , experiences a change - 450 (+ 450) at ωm , and a change of -900 (+900) at 10ωm . Root Locus: ppp js ωσ +=
One-Pole System
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)(1)(
)()(
sHsH
sXsY
β+=
0
0
/1)(
ωsAsH
+=
A single pole cannot contribute to a phase shift greater than 90° the system is unconditionally stable.
We plot and at s=jω
)(sHβ)(sHβ∠
Bode Plot:
Root Locus:
)1( 00 Asp βω +−=
We plot the location of the poles as the loop gain varies
Two-Pole System
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↓β ↓GainChangePhaseNoSystemStableMore
Bode Plot:
Two-Pole System
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Root Locus:
)(1)(
)()(
sHsH
sXsY
β+=)/1)(/1(
)(21
0
pp ssAsH
ωω ++=
021
0
)/1)(/1()()(
AssA
sXsY
pp βωω +++=
2102
21212,1 )1(4)(21)(
21
pppppp As ωωβωωωω +−+±+−=
210212
210
)1()( pppp
pp
AssA
ωωβωω
ωω
++++=
21
221
01 4
)(1
pp
pp
A ωω
ωωβ
−−=
For β = 0 212,1 , pps ωω −−= β ↑
Three-Pole System
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Additional poles and zeros impact the phase much more than the magnitude
Phase Margin
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GX: Gain Crossover PX: Phase Crossover
To ensure stability must drop to unity before crosses -180°.
)(sHβ )(sHβ∠
How far should PX be from GX ? Small Phase margin High Phase margin
Frequency Response:
Step Response:
High peak
underdamped overdamped
Example
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A two-pole feedback system is designed such that and .
1)( 2 =pH ωβ21 pp ωω << What is the phase margin ?
Since reaches -135° at
The phase margin is equal to 45°.
)(sHβ∠ 2pωω =
How much phase margin is adequate ?
H. Aboushady University of Paris VI
)135exp(1)( 1 jH −×=ωβFor PM=45°
)135exp(11)135exp(11
)()(
1°−×+
°−×=
=jj
sXsY
js βω
2/22/212/22/21
)()(
1jj
sXsY
js −−
−−=
=β
ω
βω
3.1)()(
1
== jssX
sY
Frequency Compensation
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Solution 1 Solution 2
Modify )(sHβ∠ Modify )(sHβ
Poles ↓ ⇒ Stages ↓ ⇒ Gain ↓ Reduces bandwidth
Frequency Compensation
Frequency Compensation: - lower the frequency of the dominant pole
increase the load capacitance
How much must be shifted down ? Assume: 1- 2- required PM=45°
NpAp ,, ωω << °=∠ 135)( ,ApH ωβ
outp ,ω
-The load capacitance must be increased by a factor outpoutp ,, '/ωω
-The new dominant pole: outp ,'ω
Op-Amp GBW = 1st non dominant pole
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Is it possible to compensate using Rout ?
The answer is NO !
Loutoutp CR
1, =ω
Although,
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Compensation of 2 stage Op-Amps
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Total capacitance at node E:
CvE CAC )1( 2++
2nd Stage
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( )( )[ ] ( )LGDCLEGDCLmSp CCCRCCCRgR ++++++≈
9991 1
1ω
( )( )[ ] ( )( ) ( )[ ]LELGDCEGDCLS
LGDCLGSSEGDCLmSp CCCCCCCCRR
CCCRCRCCCRgR++++
+++++++=
99
9992
1ω
Common Source Amplifier:
Pole Splitting
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LLp CR
12 ≈ω
Common Source Amplifier:
Pole Splitting
Before compensation:
( )( )991 1
1
GDLmESp CRgCR ++≈ω
After compensation:
( )( )[ ]991 1
1
GDCLmESp CCRgCR +++≈ω
LE
mp CC
g+
≈ 92ω