Automated Generation of Layout and Control

for Quantum Circuits

Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz

University of California, Berkeley

Quantum applications Shor's algorithm

Exponential speedup in

NP-hard factoring

Many computational

blocks, over a million

quantum gates

Interesting Potential

speedups But: Automate design for

large examples like this?

Why quantum CAD now? More and more quantum bits (qubits) realized

DARPA Roadmap predicts 50 qubits by 2012 Ion traps: 30 qubits by 2008

Quantum circuit design done by hand so far

However: Complexity of layout and control

Verification of fault-tolerant properties

Automation (CAD) desirable

Courtesy of Monroe group at U. Mich.

Electrode Control Qubits are atomic ions Suspended in channels

between electrodes

Quantum gates performed

by lasers Only at certain trap locations

Ions shuttled between laser

sites to perform gates

Classical control Gate (laser) ops

Movement (electrode) ops

Quantum Computing with Ion Traps

Gate Location

Qubit Ions

Electrodes

Courtesy of Chuang group, MIT

Ion Trap Physical Layout

Input: Gate level quantum circuit Bit lines

1-qubit gates

2-qubit gates

Output: Layout of channels

Gate locations

Initial locations of qubit ions

Movement/gate schedule

Control for schedule

HHH

Control

q0

q1

q2

q3

q4

q5

q6

q0

q3

q4

q5

q6

q1

q2

Qub

its

Time

Wire channels will be large 10s of microns wide

Gate sites equally large

Also requires laser routing

One layer of traps (no “metal{1,2,3...}”) All planar routing

Reuse wire and gate resources

Ion Trap Technology Constraints

Courtesy of Chuang group, MIT

Place and Route

Evaluate

Movement/Gate

Scheduler

Place and Route

Evaluate

Movement/Gate

Scheduler

Physical Layout FlowHHH

Control

Scheduling Quantum CircuitsGoal: Schedule given circuit on given layout

Gates fire with inputs Look for best gate site Prioritize critical gates Feedback if cannot

schedule

q0

q1

q2

q3

Layout

Circuit

q0

q1 q2

q3

Schedule

q0

q1 q2

q3

Dataflow

Layout Topology

q0

q1

q2

q3

q0

q1 q2

q3

Scheduling Demo

a0

a1a2

a3 a4

a5

Movement/gateScheduler

Time 0: move a0: block 2,4,6,5Time 14: gate laser: block 5Time 114: move a0: block 6,2,3Time 120: move a3: block 6,7Time 125: gate laser: block 6Time 130: gate laser: block 3Time 225: move a0: block 2,1Time 230: move a3: block 6,8Time 231: gate laser: block 1Time 236: gate laser: block 8Time 331: move a0: block 2,0Time 336: move a3: block 6,5

Scheduler Control

Control Control Control Control

LaserControl

MeasurementControl

High-levelControl

Time 0:move q0: block 1,2Time 6: gate laser: block 2 Schedule control

synthesis

Place and Route

Evaluate

Movement/Gate

Scheduler

Physical Layout Flow

Place and Route

Evaluate

Movement/Gate

Scheduler

HHH

MovementControl

P&R Heuristic: Greedy Places minimal gates

Places layout incrementally

Uses scheduler feedback

Empty layout passed to

scheduler

Scheduler feedback to P&R 2 qubits needed for gate

P&R adds gate and

channel resources

Re-schedule

P&R Heuristic: Collapsed Dataflow Gate locations placed in dataflow order

Qubits flow left to right

Initial dataflow geometry folded and sorted

Channels routed to reflect dataflow edges

Too many gate locations, collapse dataflow Using scheduler feedback, identify latency critical edges

Merge critical node pairs

Reroute channels

q0

q1

q2

q3

q0

q1

q2

q3

q0

q1

q2

q3

Experiments Evaluate generated layouts

Area: final rectangular area

Latency: time to implement movement/gate schedule

Benchmarks Quantum error correction/encoding circuits

Circuit Gates Qubits

CSS 7-bit encoder 21 7

Golay 23-bit encoder 116 23

CSS 7-bit error correct 136 21

CSS concatenated encoder 245 49

Results: Golay 23-qubit encodeGreedy P&R Collapsed Dataflow P&R

168 block bounding box area 2457 microsecond latency Good area, few channels

713 block bounding box area 2264 microsecond latency Pipelinable

Results: CSS concatenated encoder

Greedy P&R 936 block bounding box area

4791 microsecond latency

Greedy breaks down

1617 block bounding box area

1828 microsecond latency

More scalable with lots of gates

Collapsed Dataflow P&R

High-level circuit description

Synthesizer

Technology-Independent

Netlist

Technology Mapping

Technology-Dependent

Netlist

Placement andRouting

Geometry-Aware Layout

TechnologyParameter File

Movement/GateScheduling

Fault tolerance

Quantum Circuit CAD:

Future Work Working on full CAD flow for

quantum circuit design Started with physical layout

Better heuristics for layout Leverage ideas from classical CAD

Interoperability with 3rd party tools QuiDDPro, Malignant, CHP

Encourage other research into tools

to plug into this flow

High-level circuit description

Synthesizer

Technology-Independent

Netlist

Technology Mapping

Technology-Dependent

Netlist

TechnologyParameter File

Fault tolerance

Placement andRouting

Geometry-Aware Layout

Movement/GateScheduling

Conclusion Scheduling heuristic for ion trap quantum circuits

Sequences gate and communication ops on arbitrary layout

Synthesizes classical control HDL

Iterative place and route heuristics Simple greedy minimizes gate sites (lasers)

Collapsed dataflow more scalable and potentially good throughput

First steps toward larger CAD flow for quantum computing Provide tools for experimentalists as more qubits implemented

Testbed for new circuit designs for fault tolerance, new algorithms

Questions?

Future Work

Add hierarchical P&R for larger circuits

Fault tolerance layout evaluation metric

Automatic insertion of error correction

circuits

Automatic selection of error correcting

codes

Ion Trap Control Ion trap QC is coordinated

ballistic ion movement and laser

operation

Ballistic corner turn takes 120

clock cycles, many electrodes

Significant control problem

Movement and gates explicitly

controlled already

Use it to multiplex over

gates and channels

Fault Tolerant Circuit Synthesis

Simple logical circuits are complex at the

physical level

FT gates and correction can be automated

Scheduling II

Extract dataflow graph from circuit

Gates fire as soon as input qubits are ready

Gate performed at closest gate site to inputs

Quantum Circuits At-a-glance Qubit = discrete 2-level quantum

system

Circuit model has reversible gates

No wire fanout (no-cloning)

Qubits are superposition of “0” and “1”

Exponential algorithmic speedup

relies on superposition

Superposition fragile, needs a lot of

fault tolerance

Current gate failure rates around

1%

To read out data, must measure qubit

Grid Flow

Ion TrapPhysical Layout

QubitPlacement

Quantum ProgramDescription

SchedulingOperations

Classical Control

Pattern

Better CAD Flow

Fault Tolerance Transformations

Ion TrapPhysical Layout

QubitPlacement

SchedulingOperations

Classical Control

Quantum Program

Grid P&R Problems Scheduled qubit paths are inefficient

Gate usage inefficient, wasted space

Exponential search spaces of layout

tiles, qubit positions, grid size

Knowledge of circuit topology should be used for layout

Develop two heuristics for placement and routing

Prior Work: Grid Layouts

Good grid tiling

Bad grid tiling

4x performance difference!

Varying Grid Structures We evaluated performance of alternate grid

structures

1. Pick tile configuration

2. Create full layout

3. Assign qubit locations

4. Schedule operations

Prior work in layout used regular grid of channels/gate sites

Program dictates grid size, not structure Assign qubit starting positions, let scheduler do rest

Prior Work – Grid Layouts

x

y

Results: CSS 7-qubit encodeGreedy P&R Dataflow P&R

36 block bounding box area 648 microsecond latency Pretty good latency Minimal congestion

126 block bounding box area 795 microsecond latency No latency improvement

Quantum Layout Flow Automate gate placement/routing, scheduling

Ion TrapPlace & Route

Schedule moves &gates

Classical ControlSynthesis

Quantum Circuit Netlist

Classical ControlSynthesis

Quantum Layout Flow Automate gate placement/routing, scheduling

Ion TrapPlace & Route

Schedule moves &gates

Classical ControlSynthesis

Quantum Circuit Netlist

Schedule moves &gates

Quantum Layout Flow Automate gate placement/routing, scheduling

Ion TrapPlace & Route

Schedule moves &gates

Classical ControlSynthesis

Quantum Circuit Netlist

Ion TrapPlace & Route

Developed two P&R heuristics Greedy

Collapsed dataflow

q0

q1

q2

q3

q0

q1

q2

q3

P&R Heuristic: Grouped Dataflow Multiple gates can be tied to single gate location to

minimize communication

Critical paths through dataflow graph are shortened by

mapping multiple gates to single location