Assertion Based Testing

Testing and verification

Does the design function according to the specifications?

Example

Traditional approach

Generate a set of test cases (vectors) Apply to the design.. See if the output is

correct I.e. check addition, see if 2+2 = 4; VHDL assert/report statement built to support

this activity

Coverage

How many test cases does it take to check ever possible input in a design..

Percent Coverage = % of all possible cases actually tested Number of cases

Combinational logic 2#of inputs

(combinatorial explosion)

Sequential logic 2 (#of inputs) x (#of states) (combinatorial nuclear holocaust)

Input/signal timing verification(even harder)

What coverage is enough?– Use designers knowledge, generate functional test.. etc…

This technique is no longer adequate for complex designs

Assertion based testing

Verify a design by testing a set of behaviors derived from specifications

Rather that test 2+2=4, test A+B=R. Specfic behaviors are called PROPERTIES ASSERTIONS are logical statements about

properies (I.e. always true, never true)

Examples

PROPERTIES– P0: (A+B) = R when ALUop = “0001”– P1: (A-B) = R when ALUop = “0010”– P2: ALUop != “1000”

ASSERTIONS– Assert never Property ALUop = “1000”

– Assert implication Property (A+B) = R when ALUop = “0001”– Assert implication Property (A-B) = R when ALUop = “0010”

Testing Assertions

DESIGNUNDER

TEST

TESTCASE

GENERATOR

ASSERTIONCHECKER

Design inputs

Design outputs

clock

Generates a new test case on each clock edge

Tests validity of each assertion on each rising clock edge

Assertions in HDL designer

Open Verification library– Map the library COE1502_OVL into your

project. It is located at I:\1502\COE1502_OVL

– Find the documentation at http://www.cs.pitt.edu/~don/coe1502/Reference/OVL.html

– Each library component implements one type of assertion.

– You will need to write VHDL to implement the properties to be tested

Using OVL in your design

Property written in embedded block

User defined message string set in generic “msg”

Component assert_always instantiated from OVL library

Building a Testbench A testbench is a structured way of building a framework to test

your design

HDL designer creates a new block diagram with the component under test and a new component with the same inputs and outputs but with the directionality of each reversed

Inside the tester component

Test case generator

Assertion checkers Partitioned by functional block in ALU

Outputs toALU inputs

Inputs from ALU outputs

Inside the test case generator

Random Number generators

Fixed 64-bit Component rand64

Variable 1-32 bit component randv

Set seed valueAnd width

Inside the logic assertion tester

Testing signed versus unsigned behaviors

--Antecedent Expression   antecedent_expr <= true when ALUop="1011" else false;    --Consequent Expression   consequent_expr <= true when ( ( A < B) AND  (R = X"0000_0000_0000_0001" )) OR ( ( A >= B) AND

(R= X"0000_0000_0000_0000" )) else false;   

Testing the Shifters

antecedent_expr1 <= true when ALUop="1110" else false;consequent_expr1 <= true when (SHR(A,shamt)) = R else false; antecedent_expr2 <= true when ALUop="1100" else false;consequent_expr2 <= true when (SHL(A,shamt)) = R else false; 

USE ieee.std_logic_unsigned

USE ieee.std_logic_signed