Test and Verification SolutionsCo-Verification for Complex

SoC Designs

Delivering Tailored Solutions for

Hardware Verification

April 2015

Test and Verification Solutions

Christdas(Senior Engineer)

Copyright T&VS Limited | Private & Confidential | Page 2

About Me . . .

9+ yrs of Industry experience in FE Verification

2+ yrs of Academic Experience

Previously worked with Wipro, Intel and IBM

Educational Qualification

B.E - Electronics and Communication

M.Tech – Digital Communication Engg

PhD – VLSI Design (Ongoing)

Currently working as a Consultant for SoCVerification – Test and Verification Solutions, Singapore

Copyright T&VS Limited | Private & Confidential | Page 3

Agenda . . .

Innovation @TVS

Complexity in SoC Design

Enhanced scope of SoC Verification

Motivation for Co-Verification

Advantages of Co-Verification

Summary

Copyright T&VS Limited | Private & Confidential | Page 4

Innovation @ T&VS . . .

T&VS provide specialist hardware verification services and products to the worldwide semiconductor and embedded systems industries

Faster time-to-market

Improved quality/redu

ced product risk

Lower developme

nt costs

Improved product features

Trusted partner

Verification Services

Verification Productivity

Tools

Verification IPVerification

Training

Copyright T&VS Limited | Private & Confidential | Page 5

SoC Complexity . . .

SoC Design is no more just integration of verified IP’s.

SoC Design now includes

Copyright T&VS Limited | Private & Confidential | Page 6

Enhanced Verification Scope . . .

Copyright T&VS Limited | Private & Confidential | Page 7

Hybrid Verification Methodology . . .

Copyright T&VS Limited | Private & Confidential | Page 8

Latest Challenges in SoC Verification

Apart from functional verification and integration checks at SoC level, the following are now taking the centre stage in SoCDesign / Verification

Usecase Verification

Safety Verification

System level stress testing

Copyright T&VS Limited | Private & Confidential | Page 9

Use Case Verification . . .

Customer usecase scenarios

System level integration issues

HW / SW Interactions

System level corner cases

Customer concerns efficiently addressed

Copyright T&VS Limited | Private & Confidential | Page 10

Safety Verification. . .

ISO 26262 Compliant products

ISO 26262 compliant methodology / flow

Customer Assumptions – Verified?

Reliability testing and error injection scenarios

FAIL PROOF SYSTEMS

Copyright T&VS Limited | Private & Confidential | Page 11

System level Verification . . .

Stress testing at System level

HW / SW deadlocks and interactions

Low level device drivers

Emulation / Prototyping

Overall system performance and characterisation

Copyright T&VS Limited | Private & Confidential | Page 12

Traditional Design Cycle

1. High-Level

Design

2. Detail &

Implementation

3. Physical

Integration

•Requirement

Analysis

•Sub-systems

•High-Level

Simulation

•HW/SW

Interface

Hardware

PrototypingHardware

Design &

Simulation

Software

Design

HW/SW

Integration

Copyright T&VS Limited | Private & Confidential | Page 13

Concept of Co-Verification . . .

Software development and debug , performed on (almost) freezed RTL rather than on the first silicon

Efficient reduction in the time to market delay of the product

Scope to fix system level bugs in HW, rather than as a SW patch

Respins efficiently avoided

System performance measured at very early design stage

Copyright T&VS Limited | Private & Confidential | Page 14

Co-Verification for SoC Designs

Co-verification is a productive approach to minimise the overall product development turn-around time. Some significant advantages for SoCDesign are as listed below

Co-verification is helpful for “Application Usecaseverification”

Co-verification environment can also be used for system stress testing

Emulation supports co-verification and has good EDA support

Copyright T&VS Limited | Private & Confidential | Page 15

Conclusion . . .

Co-verification is helpful to tackle growing SOC Design complexity and associated SW development , thereby reducing the time-to-market delays.

Co-verification can be used for “Application UsecaseVerification” which is now significant part of SoC Verification process.

Emulation can be used as a vehicle for hardware/software co-verification – supporting real world data for comprehensive system testing, and a complete software debugging environment.

Copyright T&VS Limited | Private & Confidential | Page 16

Summary . . .

Software content of electronic products is increasing exponentially and is most often the pacing item for product completion. Software simulation alone is not fast enough to test the volume of software being written for today's electronic products. Using acceleration and emulation for hardware/software co-verification takes advantage of the investment made in the emulator for SoC verification to speed software debugging thus shortening product cycles by several months.

Copyright T&VS Limited | Private & Confidential | Page 17

Thank You . . .

Please feel free to drop me a mail for any queries / suggestions

christdas@testandverification.com

Have a good day