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Defect ToleranceDefect Tolerancefor for Yield EnhancementYield Enhancementof of FPGA InterconnectFPGA InterconnectUsing Fine-grain and Using Fine-grain and
Coarse-grain RedundancyCoarse-grain RedundancyAnthony J. YuAnthony J. Yu Guy G.F. LemieuxGuy G.F. Lemieux
September 15, 2005September 15, 2005
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OutlineOutline
Introduction and motivationIntroduction and motivation Previous worksPrevious works New architecturesNew architectures
Coarse-grain redundancy (CGR)Coarse-grain redundancy (CGR) Fine-grain redundancy (FGR)Fine-grain redundancy (FGR)
Experimentation ResultsExperimentation Results ConclusionsConclusions
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Introduction and Introduction and MotivationMotivation
Scaling introduces Scaling introduces new new typestypes of defectsof defects
Smaller feature sizes Smaller feature sizes susceptible to susceptible to smaller smaller defectsdefects
Expected resultsExpected results Defects per chip increasesDefects per chip increases Chip yield declinesChip yield declines
FPGAs are mostly FPGAs are mostly interconnectinterconnect
FPGAs must tolerate FPGAs must tolerate multiple interconnect multiple interconnect defectsdefects to improve yield to improve yield (and $$$)(and $$$)
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General Defect Tolerant General Defect Tolerant TechniquesTechniques
Defect-tolerant techniques minimize Defect-tolerant techniques minimize impact (cost) of manufacturing defectsimpact (cost) of manufacturing defects
FPGA defect-tolerance can be loosely FPGA defect-tolerance can be loosely categorized into three classes:categorized into three classes: Software Redundancy – use CAD tools to map Software Redundancy – use CAD tools to map
around the defectsaround the defects Hardware Redundancy – incorporate spare Hardware Redundancy – incorporate spare
resources to assist in defect correction (eg. resources to assist in defect correction (eg. Spare row/column)Spare row/column)
Run-time Redundancy – protection against Run-time Redundancy – protection against transient faults such as SEUs (eg. TMR)transient faults such as SEUs (eg. TMR)
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Previous work – 1 – XilinxPrevious work – 1 – Xilinx Xilinx’s Defect-Tolerant ApproachXilinx’s Defect-Tolerant Approach
Customer (knowingly) purchases “less that perfect” Customer (knowingly) purchases “less that perfect” partsparts
Customer gives Xilinx configuration bitstreamCustomer gives Xilinx configuration bitstream Xilinx tests FPGA devices against bitstreamXilinx tests FPGA devices against bitstream
Sells FPGA parts that “appear” perfectSells FPGA parts that “appear” perfect Defects avoid the bitstreamDefects avoid the bitstream
Limitation:Limitation: Chips work only with given bitstream – no changes!Chips work only with given bitstream – no changes!
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Previous work – 2 – Previous work – 2 – AlteraAltera
Altera’s Defect-Tolerant ApproachAltera’s Defect-Tolerant Approach Customer purchases “seemingly perfect” partsCustomer purchases “seemingly perfect” parts
Make defective resources inaccessible to Make defective resources inaccessible to useruser
Coarse-grain architectureCoarse-grain architecture Spare row and column in array (like memories)Spare row and column in array (like memories)
Defective row/column must be bypassedDefective row/column must be bypassed Use the spare row/column insteadUse the spare row/column instead
Limitation:Limitation: Does not scale well (multiple defects)Does not scale well (multiple defects)
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ObjectiveObjective ProblemProblem
FPGA yield is on decline because of aggressive FPGA yield is on decline because of aggressive technology scalingtechnology scaling
Proposed SolutionsProposed Solutions Defect-tolerance through redundancyDefect-tolerance through redundancy
Important ObjectivesImportant Objectives Interconnect defects important (dominates Interconnect defects important (dominates
area)area) Tolerate multiple defects (future trend)Tolerate multiple defects (future trend) Preserve timing (no timing re-verification)Preserve timing (no timing re-verification) Fast correction time (production use)Fast correction time (production use)
BackgroundBackground
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Island-style FPGAIsland-style FPGA
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Directional Switch BlockDirectional Switch Block
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Directional Switch BlockDirectional Switch Block
Course-grain Course-grain Redundancy Redundancy
(CGR)(CGR)
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Coarse-grain Coarse-grain Redundancy (CGR)Redundancy (CGR)
Row
Dec
oder
Fault Free
Spare Row
Wire Extensions
Faulty
Defect
Row
Dec
oder
BypassedRow
F. Hatori et al., “Introducing Redundancy in Field Programmable GateArrays,” presented at Custom Integrated Circuits Conference, 1993.
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So…what’s wrong with it?So…what’s wrong with it?
Spare Row and Column
0
0.2
0.4
0.6
0.8
1
1.2
1 10
Number of Defects
Yie
ld
32x32
64x64
128x128
256x256
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Improving yield for CGR –Improving yield for CGR –Adding Adding Multiple GlobalMultiple Global
SparesSpares Add multiple Add multiple
globalglobal spare to spare to traditional CGRtraditional CGR
Global spares can Global spares can be used to repair be used to repair any defective any defective row/column in the row/column in the arrayarray
Wire extensions Wire extensions are now longerare now longer
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Yield Impact of Multiple Global Yield Impact of Multiple Global SparesSpares
Global Spare Rows+Columns (32x32)
0
0.2
0.4
0.6
0.8
1
1.2
1 10Number of Defects
Yield
Baseline2 Global4 Global
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Increasing Area+Delay Increasing Area+Delay OverheadOverhead
1 GLOBAL SPARE
2 GLOBAL SPARES
4 GLOBAL SPARES MAY BE IMPRACTICAL
!!!
NO SPARES
MORE SPARES MORE MUX OVERHEAD IN EVERY SWITCH
ELEMENT
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Improving yield for CGR –Improving yield for CGR –Adding Adding Multiple LocalMultiple Local
SparesSpares Divide FPGA into Divide FPGA into
subdivisionssubdivisions
Each subdivision has Each subdivision has locallocal spare(s)spare(s)
DistributesDistributes spares across spares across chipchip Reduces mux area overheadReduces mux area overhead
(of Global scheme)(of Global scheme)
Limitation:Limitation: Spare(s) can only repair defect Spare(s) can only repair defect
withinwithin the subdivision the subdivision
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Yield Impact of Multiple Local Yield Impact of Multiple Local SparesSpares
(not as good as Global with same # (not as good as Global with same # spares)spares)
Local Spare Rows+Columns (32x32)
0
0.2
0.4
0.6
0.8
1
1.2
1 10Number of Defects
Yield
Baseline2 Global4 Global2 Sub, 1 Spare4 Sub, 1 Spare
Fine-grain Fine-grain Redundancy Redundancy
(FGR)(FGR)
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Our Proposed SolutionOur Proposed SolutionFine-grain Redundancy Fine-grain Redundancy
(FGR) – Defect Avoidance (FGR) – Defect Avoidance by Shiftingby Shifting
DefectSpare
a) Original b) Corrected
+1
+1 -1-1
-1+1
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Defect-tolerant Switch Defect-tolerant Switch BlockBlock
-1 0-2
+1 0+2
-10
-2
+10
+2
-1 0-2
+1 0+2
-10
-2
+10
+2
omux
imux
a) Original b) Defect-tolerant
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HSPICE SchematicHSPICE Schematic
16:1MUX
...
...
3:1MUX
4:1MUX
omuximux
Bypass pathDirectionalmultiplexer
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Switch Implementation Switch Implementation OptionsOptions
• Several detailed implementations are possible• Trade off area / delay / yield(repairability)
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Defect Avoidance –Defect Avoidance –Switch Implementation Switch Implementation
Option 1Option 1Can avoid contention by pre-shifting the red signal… OR…
[ lower area overhead, lower yield improvement ]
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Defect Avoidance –Defect Avoidance –Switch Implementation Switch Implementation
Option 2Option 2…OR … can avoid contention by embedding the IMUX
[ higher area overhead, best yield ]
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Single-length DefectsSingle-length Defects
OMUX
EnhancedSwitch Block
Equivalent Faults
OMUX
EnhancedSwitch Block
Wire Driver
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Double-length DefectsDouble-length Defects
OMUX
EnhancedSwitch Block
Equivalent Faults
OMUX
EnhancedSwitch Block
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Minimum Fault-free Radius Minimum Fault-free Radius (MFFR)(MFFR)
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Experimentation ResultsExperimentation Results
AreaArea DelayDelay Area Delay ProductArea Delay Product YieldYield SummarySummary
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Estimated Area overhead at Estimated Area overhead at equal yield (80%)equal yield (80%)
* CGR-G1 can only tolerate 1-2 defects
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Area Overhead for Varying Area Overhead for Varying Wire LengthWire Length
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Area ResultsArea Results
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Delay ResultsDelay Results
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Area-Delay ProductArea-Delay Product
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Yield – 1Yield – 1Switch Implementation Affects Switch Implementation Affects
Yield Yield
* Assumes all bridging defects
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Comparison between FGR and Comparison between FGR and CGR – FGR Tolerates Tens of CGR – FGR Tolerates Tens of
DefectsDefectsFine-grain Redundancy(Best Yield Architecture)
0
0.2
0.4
0.6
0.8
1
1.2
1 10 100Number of Defects
Yield
CGR
32x32
64x64
128x128
256x256
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Yield for Varying Wire Yield for Varying Wire LengthLength
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Limitations of Study & Limitations of Study & ArchitecturesArchitectures
FGRFGR Does not tolerate defects in the logicDoes not tolerate defects in the logic Cannot tolerate clustered defectsCannot tolerate clustered defects Requires a detailed fault mapRequires a detailed fault map
CGRCGR Assumes that all defects can be Assumes that all defects can be
corrected with a single row/columncorrected with a single row/column Bypass circuitry is approximatedBypass circuitry is approximated
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Summary of FGRSummary of FGR
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ConclusionsConclusions CGR CGR is effective for 1 or 2 defects effective for 1 or 2 defects FGR meets desired objectives:FGR meets desired objectives:
Tolerates Tolerates multiplemultiple randomly distributed randomly distributed defectsdefects
Defect correction Defect correction does not perturb timingdoes not perturb timing Tolerates an Tolerates an increasing numberincreasing number of defects of defects
as array size increasesas array size increases Correction can be applied Correction can be applied quicklyquickly
FGR potentially capable of FGR potentially capable of correcting correcting crosstalkcrosstalk faults, but has not been faults, but has not been exploredexplored
Thank you!Thank you!
anthonyy@ece.ubc.caanthonyy@ece.ubc.ca