Post on 09-Jul-2020
An Emulation Strategy for Artificial Intelligence and Machine Learning Designs
Gabriele Pulini
Product Marketing Manager
Mentor Emulation Division
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SoC design and verification implications
Hardware-emulation based SoC verification approach
— Deterministic (repeatable) verification results
— Hardware emulation scalability
— Virtual verification environment
Veloce for AI Designs2
Agenda
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Artificial Intelligence Fuels All Areas of Business
Veloce for AI Designs3
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AI/ML/DL SoC and Systems Verification
Veloce for AI Designs4
•Predominantly larger designs, 1.5BG to 4BG and growing
•Memory efficiency and architecture exploration
•Power analysis
•High debug productivity
Exhaustive Verification
• Firmware/device drivers
• Ability to run frameworks such as Caffe, Tensorflow etc…
• Custom software stackSoftware
• MLPerf, DAWNBench and other performance benchmarks
• Metrics of importance is TOPS/watt (Tera operations per second/watt)
• Early and flexible algorithmic analysis
Benchmarks and Algorithms
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AI/ML/DL Verification
Extensive verification is needed to address the AI/ML/DL market challenges
Reduced Time To Market with good QoR
Each provider wants to add their “secret sauce”
Reduce Verification and Debug Cost/Time
Need to support variety of design architectures
High
Bandwidth and
Cellular Comm
Image
Processing,
Video &
Compression
Computer
Vision and
Neural
Computing
5 Veloce for AI Designs
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AI/ML customer challenges
Design transistor count is largest (billions) in history of ICs— New storage/memory technologies are
needed
New architectures— TPU, Tensor Processing Unit— NNP, Neural Network Processor— NPE, Neural Processing Engine
Different ways to put silicon together— 2D, 3D stacking, Chiplets, — FGPA fabric, dedicated custom AI logic— Computational Storage Drive (CSD) and
hyperscale data centers
Veloce for AI Designs6
“Chiplets are modular pieces of silicon that can be put together in configurations that allow multi-die processors tailored for specific tasks such as ML or cloud computing.”
Mark PapermasterCTO, Executive VP, AMD
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SoC design and verification implications
Hardware-emulation based SoC verification approach
— Deterministic (repeatable) verification results
— Hardware emulation scalability
— Virtual verification environment
Veloce for AI Designs7
Agenda
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Scalability
VirtualizationDeterminism
Three pillars for AI/ML/DL Verification
Veloce for AI Designs8
All three are core competencies
of the Veloce platform
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Pillar One – Determinism
Veloce for AI Designs9
Determinism— Whether testing hardware or software, you can repeat runs over and
over, probing hardware and single-stepping code until every aspect of your design’s behavior has been checked out. That’s because each compile is semantically equivalent, which leads to convergence. Something that is not possible with prototyping.
Determinism
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Veloce Delivers Complete Determinism
Veloce for AI Designs10
Deterministic Model Building 1
Deterministic Test Execution2
Veloce compiles emulation models with 100% success
Deterministic Problem Reproduction3
Veloce emulation models produce the exact same results from one compile to another
Veloce runtime engine executes tests in a consistent order
Veloce provides repeatable debug methodology for non-deterministic stimulus environments
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Scalability— Veloce emulators are scalable from 40 million to 15 billion gates.
Whatever the size and complexity of your design and models, the Veloce platform is a “right sized” resource for verification. As your design scales up, your emulation platform can scale in capacity without performance compromise to ensure you can complete your verification on schedule.
Pillar Two – Scalability
Veloce for AI Designs11
Scalability
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AI/ML/DL– Wide Variety of Designs from the Edge to the Cloud
Veloce for AI Designs12
CB Insights, 2018
AI Edge Devices— Smaller footprint, low latency,
low power
Google, 2018
AI Cloud (Data Center) Devices— large footprint, high compute
power, high memory bandwidth, power hungry
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Scalable Capacity and Solutions
VisualizationEnterprise
ServerPower
Coverage/Assertions
SW Debug/ HYCON
Fault
DeterministicICE
DFTVirtual Network
Veloce Strato OS
ICESolutions
MemoryTransactor
LibraryVirtual
Solutions
Apps
OS SW
Solutions
HW Platform
Veloce for AI Designs13
Veloce Strato4MVeloce Strato3M
Veloce StratoM
StratoM
Link
Veloce Strato2MVeloce StratoTiL/T
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Veloce for AI Designs14
Virtualization— The complete set of information needed for design verification on the
Veloce emulator can be virtualized. Whether leveraging any of the many ready-built verification blocks or designing your own, you have full visibility and full freedom to control the execution of the verification suite as you debug any issues, and make precise measurements of important system behavior parameters.
Pillar Three – Virtualization
Virtualization
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Emulation Virtualization: AI/ML/DL Frameworks Under Performance Benchmarks
Comodel Host(s)
Applications: Power, DFT, Fault, CoverageVirtuaLAB and VTL protocolsEnable Performance Benchmarks like MLPerf and DAWNBENCH
SW Debug
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AI for Automotive: Electrical and Mechanical Must Be Verified Virtually
Powertrain model Chassis model
Simcenter Prescan
ACCIDENT DATABASE
Simcenter Amesim
ACTUATOR CONTROLSENSOR SIGNALS
AUTO DYNAMIC STATE
16 Veloce for AI Designs
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Three pillars for AI/ML/DL Verification Delivered By Veloce
Scalability
VirtualizationDeterminism
Veloce for AI Designs17
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