Post on 14-Aug-2020
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An Efficient Spectral Graph Sparsification Approach to Scalable Reduction of Large Flip-Chip Power Grids
Xueqian Zhao (MTU)Zhuo Feng (MTU)Cheng Zhuo (Intel)
Design Automation Group
Authors:
Department of Electrical & Computer EngineeringMichigan Technological University
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Large-Scale Power Grids Reductions
Motivations– Modern power delivery networks (PDNs) integrate huge number of
components
– Direct modeling and simulation of large PDNs can be very computationally expensive and even intractable
Challenges in large-scale PDNs modeling and reductions– Reductions of large-scale power grid with massive number of ports become
challenging due to fast growing computational complexity
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Prior PDN reductions methods– 1. Krylov-subspace based model order reduction methods via moment
matching ([1], [2])
– 2. Nodal elimination methods (TICER~[3], [4])
– 3. Multigrid-like reduction methods ([5], [6])
Problem formulation– DC and transient (TR) simulations:
Background & Existing Works
TR
DC
[1].P. Feldmann, et., “Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals”, ICCAD,2004[2].P. Li, et., “Model order reduction of linear networks with massive ports via frequency-dependent port packing”, DAC, 2006[3].B.N. Sheehan, “Realizable reduction of RC networks”, IEEE TCAD, 2007[4].C.S. Amin, et., “Realizable RLCK circuit crunching”, DAC, 2003[5].H. Aca, et., “Power grid reduction based on algebraic mutigrid principles”, DAC, 2003[6].Y. Su, et., “AMOR: an efficient aggregating based model order reduction method for many-terminal interconnect circuits”, DAC, 2012
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Overview of Our Method
Keys steps of our proposed method– Divide-and-conquer power grid reduction and sparsification approach:
Spectral Graph Sparsification
Grid Partition&
Block Reduction
Original Power Grid
Model Stitching
Reduced Power Grid
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Graph Laplacian
Weighted graph A and its Laplacian matrix
1 2
4
3
5
1.52
2
1.51
0.5
3.5 1.5 21.5 4 2 0.5
2 3 10.5 1 3 1.5
2 1.5 3.5
− − − − − − − − − − − − −
1
2
4
3
5
1 2 43 5
( , )
( , ) if ( , )( , ) ( , ) if
otherwise0u v E
w u v u v EA u v w u v u v
∈
− ∈
= ==
∑Grounded resistance
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Block Power Grid Reduction
For a power grid with n nodes and m current sources
If we only keep the port nodes but eliminate all non-port nodes, a much smaller equivalent system can be obtained by Schur complement method
1 111 12 12( )T T
eqG G G L L G− −= −
22TG LL=where
port:
Smaller but much
denser
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An Efficient Port-Merging Scheme
Once the number of ports remains large, the resultant reduced grid can be still costly to use
Port b
Port a
Block i
Left Right
Back
Front
Port c
Port d
Port 1
Port 2
Block i
Port a’ Port dPort 1’
Original block and ports Merge ports based on effective resistance
If < thresR: merge portselse : ports are kept
Port dPort a
Port cPort b
Port 2Port 1
Front Right
Merge a, b and c Merge 1 and 2
XX
X
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Graph sparsification– Cutting-based sparsification
– Only remove less importance edges– Spectral-based sparsification
– Approximate the spectral similarity (e.g. eigenvalue distributions) of original graph by a sparser graph with updated graph edges
Reduced block grid density– Stitched block grids after reduction can also be too expensive to use– Our target is to reduce the grid dimension while maintain the grid density
Reduce Block Grid Density
Reducedimension
(billion -> million)
Sparsify(reduce edges)
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Spectral Graph Sparsification
Sub-graph à is (1+ε)–spectral approximation of A if
( , , )A V E w=
A spectral sparsifier is a sub-graph of the original whose Laplacian quadratic form is approximately the same as that of the original graph on all real vector inputs [1]
Spectral sparsifier:
0ε >
[1]. D.A. Spielman and S. Teng, “Spectral sparsification of graphs,” CoRR, vol. abs/0808.4134, 2008.
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Spectral Graph Sparsification (cont.)
In practical applications, spectral graph sparsifier can be obtained by using sampling method:
Valid samples of each edge are determined by its probability pe
( )effe e Ap w R e=
How to:
0 pe 1
1. generate M random numbers between 0 ~ 12. if K of M have values < pe, the edge is selected K times3. the new weight of edge e in spectral graph:
' ee
e
KwwMp
=
samplesunselected samplesselected samples
ee
e
ppp
=∑
[1]
[1]. I. Koutis, G. L. Miller, and R. Peng, “A fast solver for a class of linear systems,” Commun. ACM, 2012
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Weighted degree metric– Provides trade-offs between the sparsity and the accuracy of
reduced power grid.
– The weighted degree of vertex v in a graph A is defined:
– In a mesh grid, 1 (1 critical edge) ≤ wd(v) ≤ 4 (4 evenly critical edges)
How to Control Sparsification Quality
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1( )max
ii
i
wwd v
w==∑
1( ) ( )v V
awd A wd vn ∈
= ∑v
w1
w2
w4
w3
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How to Control Sparsification Quality (cont.)
Iterative spectral graph sparsification scheme– 1. Iteratively sample edges
– 2. Stop once the awd(Ã) > θ x awd(A)
awdsmp≈1.2 < 0.9×awdorig
M samples
awdsmp≈1.4 < 0.9×awdorig M+m samples
awdorig≈1.7
awdsmp≈1.6 > 0.9×awdorig
M+2m samples
given threshold θ=0.9
Example:
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Graph Scaling Scheme
Total conductance of spectral sparsifier becomes different
Graph scaling (GS) scheme is applied to improve spectral graph approximation w/o increasing extra edges
For reduced block k:
kα is scaling factor
reduced sparsifiedAfter spectral sparsification
After edge scaling
Original edge of reduced gridScaled sampled edges
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Current Redistribution Using Numerical Method
Current sources need to be redistributed according to reduced block grid
portsnon-ports
Original Current Sources Re-distributed Current Sources
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Block Power Grid Model Stitching
Reduced block grids are stitched using recreated block-to-block edges
1 1 2 3iblockg g g g= + +
Total outgoing conductance from block i:
1 1 2jblockg g g= +
Total outgoing conductance from block j:
12 1 2 2 3
2g g gg + +
=
Final conductance for merged edge:
PortOriginal edgeMerged edge
g1g2
g3g4
12
43
56
87
Block i Block j
Before Merging
g2>g3>g1>g4
After Merging1’
4
5’
7Block i Block j8
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Capacitance Redistribution for Transient Analysis
In this work, we propose uniform capacitance redistribution within each reduced block grid
Original block i:
Within each block, maintain the same total capacitance
1
iN
i jj
Ctot c=
=∑
Reduced block i:
Re-assigned Capacitor
Original Capacitor
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Experimental Setup
CKT # unk # Res. # Lay. # C4s # I Max. Vd.
ibmpg3 440,615 724,184 5 461 88,471 182mV
ibmpg4 478,094 779,946 6 650 127,221 3.6mV
ibmpg5 581,472 871,182 3 177 236,600 43mV
ibmpg6 862,417 1,283,371 3 249 315,568 114mV
• # unk: number of unknowns in power grid
• # Res.: number of resistors in power grid
• # Lay.: number of metal layers in power grid
• # C4s: number of C4 bumps in power grid
• # I: number of current sources in power grid
• Max. Vd.: maximum voltage droop in power grid (1.8V voltage supply)
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Experimental Results (1)
Accuracy vs. Number of samples of spectral sparsification
Sparsify? Nsmp Fact. Solve Mem #R Err.
N - 0.26s 0.018s 88MB 1,064k 0.68mV
Y 1600 0.21s 0.016s 47MB 319k 0.8mV
Y 1200 0.20s 0.016s 45MB 282k 0.9mV
Y 800 0.19s 0.015s 43MB 238k 0.9mV
Y 600 0.18s 0.015s 39MB 209k 1.05mV
Y 400 0.16s 0.014s 33MB 175k 1.28mV
Y 200 0.12s 0.012s 25MB 132k 2.3mV
• ibmpg5 for 90% node elimination
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Experimental Results (2)
90% Elimination #blk thresR #N #R Err w/o GS Err w/ GSibmpg3 2116 0.14Ω 44k 158k 1.6mV 1.4mVibmpg4 961 0.30Ω 49k 201k 0.87mV 0.19mVibmpg5 1156 0.10Ω 52k 175k 1.5mV 1.2mVibmpg6 900 0.05Ω 73k 183k 2.8mV 2.4mV
• Accuracy comparison for different reduction ratios w/ spectral sparsification for DC analysis
93%Elimination #blk thresR #N #R Err w/o GS Err w/ GSibmpg3 2116 0.20Ω 32k 129k 2.0mV 1.5mVibmpg4 961 0.40Ω 33k 165k 0.80mV 0.28mVibmpg5 1156 0.20Ω 35k 141k 3.0mV 1.5mVibmpg6 900 0.15Ω 62k 172k 4.6mV 3.0mV
95% Elimination #blk thresR #N #R Err w/o GS Err w/ GSibmpg3 2116 0.32Ω 23k 95k 2.5mV 2.4mVibmpg4 961 0.68Ω 23k 119k 0.70mV 0.52mVibmpg5 1156 0.30Ω 31k 135k 2.9mV 1.7mVibmpg6 900 0.25Ω 43k 148k 6.7mV 3.9mV
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Experimental Results (3)
Reduction time
• Reduction time for 90%, 93% and 95% node elimination of power grids
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Experimental Results (4)
• Accuracy comparison for transient analysis
• transient waveforms comparison of ibmpg5 for 90% node elimination• total capacitance of 5e-7 Farad is distributed at each current sources
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Experimental Results (5)
CKT90% elimination 93% elimination 95% elimination
Full Inc. Full Inc. Full Inc.
ibmpg3 23.5s 2.66s (9X) 21.6s 2.50s (8X) 20.7s 2.40s (8X)
ibmpg4 38.7s 4.40s (9X) 29.5s 3.39s (9X) 25.2s 2.94s (9X)
ibmpg5 26.0s 2.70s (10X) 19.4s 2.17s (9X) 18.4s 2.10s (9X)
ibmpg6 88.0s 9.25s (9x) 71.0s 7.40s (9X) 54.6s 5.98s (9X)
• Runtime analysis between complete power grid reductions and incremental reductions.
• In the incremental analysis, 10% blocks of each benchmark are modified for updated reductions
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Conclusion
Proposed an efficient spectral graph sparsification approach to scalable reduction of large flip-chip power grids
Key Ideas:– 1. Partition the original power grids into massive number of smaller
grid blocks
– 2. Reduce each block by merging outgoing ports and Schurcomplement method
– 3. Sparsify the reduced dense grid blocks using spectral graph sparsification scheme, and at last stitch them together to build the final reduced power grid model.
Our experimental results show that the proposed method can:
– Achieve up to 20X reductions w/o loss of much accuracy in both DC and transient analysis
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THANK YOU!