Post on 08-Jul-2020
A 26Gbps 3D-Integrated Silicon Photonic Receiverin BiCMOS-55nm and PIC25G with -15.2dBm
OMA Sensitivity
Farhad Bozorgi1, Melchiorre Bruccoleri2, Matteo Repossi2, Enrico Temporiti3, Andrea Mazzanti1 and Francesco Svelto1
1University of Pavia, 2STMicroelectronics, 3eSiliconPavia, Italy
farhad.bozorgi@unipv.it
September 25, 2019
ESSCIRC/ DE , Cracow, PolandESS RC 2019 1 of 18
Outline
Introduction Optical Receiver TIA Design Implementation Measurement Performance summary Conclusion References
2 of 18ESSCIRC/ESSDERC 2019, Cracow, PolandFarhad Bozorgi
Introduction – Data Communication
Huge Volumes of data is created each year By varoius breakthrough applications (5G, cloud computing, IOT)
Majority of data take place in DataCenter (DC) They will occupy acres of acres of lands with continued growth of data
Mid-Range optical transceiver in datacenters leveraged in DC• long reach (up to 10km), low channel loss, low cost Higher data-rate (>100Gbps)
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[1,2]
Farhad Bozorgi
Introduction - Why Silicon Photonics?
Bottlenecks of the current technology Limited performances in terms of size and range (up to 100m) High packaging Cost
Role of Silicon Photonics Monolithic integration of optical devices together with electronic
components Reduce cost by going to larger wafer diameter (300mm) Scaling down the form factor Solving interconnect limits (Embedded transceivers on processor memories
and switches)
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[2]
Farhad Bozorgi
Introduction - 3D Assembly
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Maximizes both EIC and PIC design flexibility Realizing the 3D dice assembly through copper pillars
The 3D structure has to be assembled on the substrate of the PIC
[3]
Farhad Bozorgi
PICEIC
Optical Receiver - System Topology
Block diagram of a 3D-Integrated Silicon-Photonic Optical Receiver Design, tape-out and measurements of Analog Front-End is presented
BiCMOSS-55nm for the EIC
ESSCIRC/ DE , Cracow, PolandESS RC 2019 6 of 18Farhad Bozorgi
EICPIC
Board
DC BondwiresUnderfill
Copper Pillars
SMF
Waveguide DH Ge-PD
2D PSGC
PIC
SMF
dem
ux1330 nm
1310 nm
Supply & Digital &
Bias Circuit
DC Bondwires
GSGSG
EIC
Analog Front End
Filtering Caps
Prob
e
Optical PathElectrical Path
5.2 dB Loss
Optical Receiver - AFE
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TIA Limiting Amplifier Buffer
LPFOTA
IinvOUT
Fully Differential resistive Shunt Feedback TIA is proposed Tapered stage amplifiers
to limit the voltage level ECL buffer with emitter degeneration to drive off-chip loads Automatic DC offset cancellation loop
Farhad Bozorgi
TIA Design – Classical TIA
ESSCIRC/ DE , Cracow, PolandESS RC 2019
Trans-impedance limit imposes upper limit for DC gain as: There is stringent compromise:
input-referred noise, BW and transimpedance gain
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𝒁𝒁𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎 = 𝑹𝑹𝑭𝑭
𝑩𝑩𝑩𝑩 =𝟐𝟐𝟎𝟎𝟎𝟎
𝟐𝟐π𝑹𝑹𝑭𝑭𝑪𝑪𝟎𝟎
𝑪𝑪𝟎𝟎 = 𝑪𝑪𝒊𝒊𝒊𝒊 + 𝑪𝑪𝑷𝑷𝑷𝑷
𝒁𝒁𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎 ≤𝟎𝟎𝟎𝟎𝒇𝒇𝟎𝟎
𝟐𝟐π𝑪𝑪𝟎𝟎𝑩𝑩𝑩𝑩𝟐𝟐
𝟎𝟎𝟐𝟐𝒊𝒊,𝒊𝒊𝒊𝒊,𝑺𝑺𝑭𝑭 =𝟒𝟒𝟒𝟒𝟎𝟎𝑹𝑹𝑭𝑭
+𝑽𝑽𝟐𝟐𝒊𝒊,𝒊𝒊𝒊𝒊,𝒄𝒄𝒄𝒄𝒄𝒄𝒄𝒄
𝑹𝑹𝑭𝑭𝟐𝟐𝟏𝟏 + ω𝟐𝟐𝑪𝑪𝟎𝟎𝟐𝟐 +
𝑽𝑽𝟐𝟐𝒊𝒊,𝒊𝒊𝒊𝒊,𝑳𝑳𝟎𝟎
𝒁𝒁𝟎𝟎𝟎𝟎𝟎𝟎 𝟐𝟐Input Referred Noise:
Iin
Cin 𝐴0 𝑓0
+ - + - LACPD
[4]
Farhad Bozorgi
TIA Design – Proposed FD-SF TIA
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𝒁𝒁′𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎 = 𝟐𝟐𝑹𝑹′𝑭𝑭
𝑩𝑩𝑩𝑩′ =𝟏𝟏𝟐𝟐
𝟐𝟐𝟎𝟎𝟎𝟎𝟐𝟐π𝑹𝑹′𝑭𝑭𝑪𝑪′𝟎𝟎
𝑪𝑪′𝟎𝟎 =𝑪𝑪𝒊𝒊𝒊𝒊𝟐𝟐
+ 𝑪𝑪𝑷𝑷𝑷𝑷
𝟎𝟎𝟐𝟐𝒊𝒊,𝒊𝒊𝒊𝒊,𝑺𝑺𝑭𝑭 =𝟒𝟒𝟒𝟒𝟎𝟎𝟐𝟐𝑹𝑹′𝑭𝑭
+𝑽𝑽𝟐𝟐𝒊𝒊,𝒊𝒊𝒊𝒊,𝒄𝒄𝒄𝒄𝒄𝒄𝒄𝒄
𝟐𝟐𝑹𝑹′𝑭𝑭𝟐𝟐 𝟏𝟏 + ω𝟐𝟐𝑪𝑪′𝟎𝟎
𝟐𝟐 +𝑽𝑽𝟐𝟐𝒊𝒊,𝒊𝒊𝒊𝒊,𝑳𝑳𝟎𝟎
𝒁𝒁′𝟎𝟎𝟎𝟎𝟎𝟎 𝟐𝟐Input Referred Noise:
Cin
CB
inNIininP
+ -
Iin
Iin
Iin
Cin
𝐴0 𝑓0
-
+
2+ -
LA+
-CPD
𝟎𝟎𝟐𝟐𝒊𝒊,𝒊𝒊𝒊𝒊,𝑭𝑭𝑷𝑷−𝑺𝑺𝑭𝑭 =𝟒𝟒𝟒𝟒𝟎𝟎𝟐𝟐𝑹𝑹𝑭𝑭
+𝑽𝑽𝟐𝟐𝒊𝒊,𝒊𝒊𝒊𝒊,𝒄𝒄𝒄𝒄𝒄𝒄𝒄𝒄
𝟐𝟐𝑹𝑹𝑭𝑭𝟐𝟐+ 𝑽𝑽𝟐𝟐𝒊𝒊,𝒊𝒊𝒊𝒊,𝒄𝒄𝒄𝒄𝒄𝒄𝒄𝒄
ω𝟐𝟐𝑪𝑪𝟎𝟎𝟐𝟐
𝟒𝟒+𝑽𝑽𝟐𝟐𝒊𝒊,𝒊𝒊𝒊𝒊,𝑳𝑳𝟎𝟎
𝟒𝟒 𝒁𝒁𝟎𝟎𝟎𝟎𝟎𝟎 𝟐𝟐
if 𝑪𝑪𝒊𝒊𝒊𝒊 ≫ 𝑪𝑪𝑷𝑷𝑷𝑷 , then 𝑪𝑪′𝟎𝟎 = 𝑪𝑪𝒊𝒊𝒊𝒊𝟐𝟐
, 𝑹𝑹′𝑭𝑭 = 𝑹𝑹𝑭𝑭, 𝑩𝑩𝑩𝑩′ = 𝑩𝑩𝑩𝑩
Farhad Bozorgi
Implementation
ESSCIRC/ DE , Cracow, PolandESS RC 2019 10 of 18
𝑹𝑹𝑭𝑭 = 𝟏𝟏𝟒𝟒Ω
Minimum 𝑽𝑽𝑪𝑪𝑪𝑪 = 𝟏𝟏.𝟔𝟔𝑽𝑽
𝑪𝑪𝑩𝑩 = 𝟏𝟏𝟎𝟎 𝒑𝒑𝑭𝑭
2mA 7mA 14mA Circuit detail of AFE
Capacitive degeneration technique used for equalization purpose Emitter degeneration in buffer to reduce the capacitive load for precedent stage
Farhad Bozorgi
TIA Design - Simulation
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The Frequency where CB effects
in FD-SF TIA
Simulated 𝒁𝒁𝟎𝟎𝟎𝟎𝟎𝟎 and equivalent Input Referred Noise (IRN): SF TIA vs FD-SF TIA (with same BW)
Farhad Bozorgi
22hp
F
fR CBπ
=
Implementation
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2.5*0.3mm2
Chip Microphotograph and Layout
ESSCIRC/ESSDERC 2019, Cracow, PolandFarhad Bozorgi
Measurement - Setup
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MZM1310nm Laser Attenuator
90/10Splitter
Power Meter
PPG&
BERT
Clock
MZM Driver
DCA
GSGSG Probe
DUT
LightwaveProbe
ESSCIRC/ESSDERC 2019, Cracow, PolandFarhad Bozorgi
Measurement – Output Eye Diagram
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26Gbps @-15.2 dBm OMA 26Gbps @-12 dBm OMA 26Gbps @-9 dBm OMA
32Gbps @-14dBm OMA 32Gbps @-11 dBm OMA 32Gbps @-8 dBm OMA
ESSCIRC/ESSDERC 2019, Cracow, PolandFarhad Bozorgi
Measurement
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Receiver Chain Transfer FunctionMeasurement vs. Simulation with
30GHz BW, 76dBΩ Simulated DC Gain
Bathtub curve @sensitivityfor 26Gbps, 0.18 UI
horizental eye opening
ESSCIRC/ESSDERC 2019, Cracow, PolandFarhad Bozorgi
Sensitivity vs. input OMA
Conclusion
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A 26Gbps 3D-integrated silicon photonics receiver has been presented.
Very low noise performance is demonstrated by leveraging a FD-SF TIA as well as low parasitic cap. in silicon photonic tech.
The sensitivity at the fiber output is aligned with state-of-the-art receivers employing discrete photonics
The lowest sensitivity reported among the published 25Gbps receivers exploiting silicon photonics, to authors’ best knowledge
ESSCIRC/ESSDERC 2019, Cracow, PolandFarhad Bozorgi
References
[1] Plant, David V, et al. "Optical communication systems for datacenter networks." 2017 OFC [2] D. Mahgerefteh and et al., “Techno-Economic Comparison of Silicon Photonics and Multimode VCSELs,” Journal
of Lightwave Technology, vol. 34, no. 2, pp. 233–242, Jan 2016. [3] Temporiti, Enrico, et al. "Insights into silicon photonics Mach–Zehnder-based optical transmitter architectures."
IEEE JSSC 51.12 (2016): 3178-3191. [4] Säckinger, Eduard. Broadband circuits for optical fiber communication. John Wiley & Sons, 2005. [5] T. Takemoto and et al., “A 25-to-28 Gb/s High-Sensitivity (-9.7 dBm) 65 nm CMOS Optical Receiver for Board-
to-Board Interconnects,” IEEE JSSC, vol. 49, no. 10, pp. 2259–2276, Oct 2014. [6] S. Huang and W. Chen, “A 25 Gb/s 1.13 pJ/b -10.8 dBm Input Sensitivity Optical Receiver in 40 nm CMOS,”
IEEE JSSC, vol. 52, no. 3, pp. 747–756, March 2017. [7] H. Andrade and et al., “Monolithically-Integrated 50 Gbps 2pJ/bit Photoreceiver with Cherry-Hooper TIA in
250nm BiCMOS Technology,” OFC March 2019, pp. 1–3. [8] H. Jung and et al., “A 25-Gb/s Monolithic Optical Receiver With Improved Sensitivity and Energy Efficiency,”
IEEE Photonics Technology Letters, vol. 29, no. 17, pp. 1483–1485, Sep. 2017. [9] E. Temporiti and et al., “A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS
technologies,” ESSCIRC, Sep. 2014, pp. 131–134. [10] S. Gudyriev and et al., “Fully-differential, DC-coupled, self-biased, monolithically-integrated optical receiver in
0.25„m photonic BiCMOS Technology for multi-channel fiber links,” IEEE BCTM, Oct 2017, pp.110–113.
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