Post on 04-Jun-2018
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Logic Analyzer
INTRODUCTION TO THE DIGITAL DOMAIN
The advent of digital circuits dramatically changed the concerns of
engineers and technicians working with electronic circuits. Ignoring for a moment
digital signal quality or signal integrity, the issues switched from the world of bias
points and frequency response to the world of logic ones, zeroes, and logic states (see
Fig. a !. This world has been called the "data domain."
#sing off$the$shelf components virtually guarantees correct values of
voltage and current if clocks are kept to moderate speeds (less than %& ' z! and fan$
in)fan$out rules are observed. The ob*ective for circuit verification and test focuses on
questions of proper function and timing. +hile parametric considerations are
simplified, there is a tremendous increase in functional comple ity and the sheer
number of circuit nodes. 'easurements to address these questions and to manage the
increased comple ity are the fort of the - ogic analyzer./ ogic analyzers collect and
display information in the format and languages of digital circuits.
'icroprocessors and microcontrollers are the most common logic$
state machines. 0oftware, written in the unique form of a microprocessor1s instruction
set, provides the direction for these handy state machines. 'ost logic, analyzers can he
configured to format their output as a sequence of microprocessor instructions. This
makes them useful for debugging software. For real$lime or time$critical embedded
controllers, a logic analyzer is an e cellent tool to both trace program flow and measure
event timing.
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a) Asynchronous Mode
:n screen, the asynchronous mode looks very much like an
oscilloscope display. +aveforms are shown, but in contrast to an oscilloscope=s two or
four channels, there are a large number of channels 5 eight to over a hundred. The
signals being probed are recorded either as a -one/ or a - >ero/. ?oltage variation
other than being above or below the specified logic threshold is ignored, *ust as the
physical logic elements would do. Figure < a compares an analog waveform with its
digital equivalent. 4 logical view signal timing is captured. 4s with an oscilloscope,
the logic analyzer in timing mode provides the time base that determines when data
values are clocked into instrument storage. This time base is refereed to as the -internal
clock./ 4 sample logic analyzer display showing waveforms captured in timing mode
is shown in Fig. < b.
?oltsversustime Threshold
ogicvalueversustime &
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Fig. < (a! 4nalog versus digital representations of a signal.b) Synchronous Mode
The synchronous state mode samples signal values into memory on a
clock edge supplied by the system under lest. This signal is referred to as the "e ternal
clock." Aust is a flipflop takes on data values only when it is clocked, the logic analyzer
samples new data values or stales only when directed by the clock signal. 7roupings of
these signals can represent state variables. The logic analyzer display shows the
progression of states represented by these variables. 4 sample logic analyzer display
showing a trace listing of a microprocessors bus cycles (state mode! is shown in Fig. @.
c) Block Diagram
4n understanding of how logic analyzers work can be gotten from
the block diagram in Fig. B. ogic analyzers have si key functions5 the probes, high$
speed memory, the trigger block, the clock generator, the storage qualifier, and the user
interface.
1. Probes . The first function block is the probes. The function of the probes is to make
physical connection with the target circuit under test. To maintain proper operation of
the target circuit, it is vital that the probes not unduly load down the logic signal
of interest or disturb its timing. It is common for these probes to operate as voltage
dividers. 2y dividing down the input signal, voltage comparators in the probe function
are presented with the lowest possible voltage slew rate. igher$speed signals can be
captured with this approach. The voltage comparators transfer form the input signals
into logic values. 3ifferent logic families, i.e., TT , ;6 , or 6':0 have different
voltage threshold, so the comparators must have ad*ustable thresholds.
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2. High-Speed Memory : The second function is high$speed memory, which stores the
sampled logic values. The memory address for a given sample is supplied internally.
Typical memory depth is B&CD or BE sampies. 0eine analyzers can store several
megasamples. #sually the analyzer user is interested in observing the logic signals
around some event. This event is called the "measurement trigger." It will be described
in the ne t functional block. 0amples have a timing or sequence relationship with the
trigger event but are arbitrarily placed in samples memory depending on the
instantaneous value of the internally supplied address. The memory appears to the user
as a continuously looping storage system.
3. Trigger lo!" . The third functional block is the trigger block. Trigger events are a
use tied pattern of logical ones and zeroes on selected input signals. Figure %. shows
how a sample trigger pattern corresponds with timing and state data streams. 0ome
form of logic comparators is used to recognize the pattern of interest. :nce the trigger
event occurs, the storage memory continues to store a selected number of posttrigger
samples. :nce the posttriger store is complete, the measurement is stopped. 2ecause
the storage memory operates as a loop, samples before the trigger event are captured,
representing time before the event. 0ometimes this pretrigger capture is referred to as
"negative time capture." +hen searching for the causes of a malfunctioning logic
circuit, the ability to view events leading up to the problem, i.e., the trigger event,makes the logic analyzer e tremely useful.
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4cquisition Time
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Trigger
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