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Our customer is the global supplier of networking technology solutions.
The two 65nm TSMC library based networking chips are targeted at router devices. Die
size is 15mm x 15mm for one and 14mm x 14mm for the other. Both chips run on
1GHz frequency, are mapped on 65 nm TSMC library and contain 10 metal layers (9
metal layers for signal routing and 10th metal layer for bump cells). There are 14 million
placeable objects. Glue logic in both the chips have been converted into repeater stations.
The customer selected eInfochips based on our proven track record of successfully
managing complex physical design projects involving advanced process technology nodes
and low power design techniques.
eInfochips performed physical design of two networking chips on 65nm technology. We
successfully performed place and route and sign-off services - STA, DRC / LVS
cleanup, RC Extraction, IR Drop analysis etc. while resolving timing violations, crosstalk,
DRC / LVS failures , ECO implementation through automation and manual means. The
overall engagement helped the customer achieve chip tapout on time and with zero
critical bugs. Also customer was able to provide early samples to their end customers.
Networking Chip Physical Design - www.einfochips.com http://www.einfochips.com/case-study/65nm-networking-chip
5/3/2010
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Our customer offers a broad product portfolio, spanning routing, switching, security,
application acceleration, identity policy and control, and management designed to give
customers unmatched performance, greater choice and flexibility while reducing overall
total cost of ownership.
Timing violations at block level
LVS failed for most of the blocks
DRC count was in thousands and the tool was not able to resolve them
automatically
Few blocks had congestion issues and implementing ECO was not easy
eInfochips team worked on the following aspects as a part of the physical design
engagement
Place & Route (P & R), Sign-off (includes IR drop analysis, STA, Calibre
LVS/DRC, RC Extraction etc.) for two networking chips which interact at board
level
Physical design using Calibre, Apache, Synopsis tool chain - Design Compiler, ICCompiler, Astro, Formality, Star-RC etc.
Sign-off flow comprised of:
GDS generation
Calibre DRC/LVS
RC extraction
PT timing
IR Drop Analysis
Noise analysis
Industry: Networking
Technology: 65nm TSMC (10 Metal layers)
Die Size: 15mm x 15mm; 14mm x 14mm
Design Complexity: 14 Million Gates
Frequency: 1 GHz
Networking Chip Physical Design - www.einfochips.com http://www.einfochips.com/case-study/65nm-networking-chip
5/3/2010
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Languages: Perl, TCL, and Make for Scripting
Tools: IC Compiler, Star RCXT, Apache, Calibre, PrimeTime
Flawless execution of a complex project by early detection of design implementation
issues resulted in a stable RTL designeInfochips took complete ownership of delivering GDSII to foundry allowing the
customer to focus on early enabling of their customers
eInfochips enabled the customer to commence production of components ahead of
schedule using an in-house three stage design methodology
Networking Chip Physical Design - www.einfochips.com http://www.einfochips.com/case-study/65nm-networking-chip
5/3/2010