Post on 01-Jan-2016
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1.0 INTRODUCTION
Characteristics of the active electronic components that determine the internal construction and operation of electronic circuitry of a logic gate.
Y = 0
+5V
A = 1 10k
1k
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1.1 Types of logic gatesNOTANDORXOR
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1.1 Types of logic gates (cont.)NANDNORXOR
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1.2 Diode as a voltage controlled switchp-n junction componentTwo type material: p-type & n-typeOperation: forward biased & reverse biasedKnee voltage: 0.7V (Si) n 0.3V (Ge)
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1.2 Diode as a voltage controlled switch (cont.)
Operation 0V – knee voltage
Small current’s flow Beyond knee voltage Negative voltage
Leakage current More negative voltage
Zener voltage
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1.2 Diode as a voltage controlled switch (cont.)Forward biased vs. reverse biased
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1.2 Diode as a voltage controlled switch (cont.)Diode works as a logic ON/OFF switch
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1.2 Diode as a voltage controlled switch (cont.)Voltage range of logic level for TTL digital IC
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1.2 Diode as a voltage controlled switch (cont.)Simple 2-input OR gate
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1.3 Transistor as a voltage controlled switchp-n junction componentTwo type: PNP & NPN
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1.3 Transistor as a voltage controlled switch (cont.)B-E junction as switch
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1.3 Transistor as a voltage controlled switch (cont.)Not gate
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1.4 Diode controls switching speedSpeed limitation when switching diode from ON to
OFF and vice versa Minority-carrier density
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Reverse biased (OFF)
Forward biased (ON)
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1.5 Switching timeRise and fall time
Time taken for a signal to go from LOW to HIGH and vice versa.
Tr and Tf
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1.5 Switching time (cont.)Storage time
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(a)Circuit(b)Input waveform(c) Diode current(d)Diode voltage(e)Minority carrier
(c)
(d)
(e)
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1.5 Switching time (cont.)Propagation delay
Time interval between the application of an input pulse and the occurrence of the resulting output pulse.
Cumulative time delay when gates are cascaded.
Limits the max freq at which a gate can operate.For propagation delay of 40ns; max freq operation is
25MHzFor propagation delay of 25ns; max freq operation
is ???
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1.5 Switching time (cont.)Propagation delay (cont.)
Two types: TPLH
- delay time from
logic 0 to logic 1.TPHL - delay time from
logic 1 to logic 0.Measured at 50% on rising
and falling edges of the input and output.
Total propagation delay?
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1.6 TTL familyTTL Series:
74 Series – First line of standard TTL ICs 74L Series – low-power version 74H Series - high-speed version 74S Series – Schottky TTL, reduce storage time delay 74LS Series – Low-Power Schottky TTL 74AS Series – Advanced Schottky TTL 74ALS Series – Advanced Low-Power Schottky TTL 74F Series – Fast TTL
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1.6 TTL family (cont.)TTL NAND Gate OperationSchottky TTL 74SLow-Power Schottky TTLAdvanced Schottky TTL,
74AS Series (AS-TTL)Current-Sourcing and
Current-Sinking ActionTotem Pole TTLTristate (Three-state) TTL
UNIT 1 – CONSTRUCTION OF LOGIC GATESTUGASAN
1 :PETA
MINDA.TARIKH AKHIR
HANTAR : 12 FEB 2010NO
PLAGIARSM!!!
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1.7 CMOS familyCMOS INVERTER GATE
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1.7 CMOS familyCMOS NAND GATE
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1.7 CMOS familyCMOS TRANSMISSION GATE
Pass signal in both direction. Useful for digital and analog application.
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1.8 Comparison of CMOS and TTL
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TTL CMOS
Noise Margin 0.4V (standard) 1.5V (30% of VDD)Typically 45%
Power dissipation
mW nW
Propagation delay
TPLH is 11ns – 22nsTPHL is 7ns – 15 ns
30 - 50ns
Fan-in Depends on number of unit loads it can
handle. Usually 3.
Depends on number of unit loads it can
handle
Fan-out Typically 10 Typically 50
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1.9 Interfacing TTL and CMOS ICsConnecting the output(s) of one circuit of system to
the input(s) of another circuit that has different electrical characteristics.
Why? Utilize strong points of different logic families. Ex: 74AS used in parts need for highest frequency
741 used in slower parts NMOS for LSI parts of the system.
Two things to consider: Voltage Current
Where? – device data sheets
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1.9 Interfacing TTL and CMOS ICs (cont.)CMOS driving TTL
Input current for CMOS arelow compared to output current TTL no prob.
Input voltage for CMOS arehigher than output voltage
TTL pull-up resistor.
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