Post on 29-Dec-2015
1
SOC Test Architecture Optimizationfor Signal Integrity Faultson Core-External Interconnects
Qiang Xu and Yubin Zhang Krishnendu Chakrabarty
The Chinese University of Hong Kong Duke University
2
Outline 1 Background
2 Motivation
3 Two-D SI test set compaction
4 SOC test architecture optimization
5 Experimental results
6 Conclusion
3
Signal Integrity
Vdd
Vs
ideal signal
signal with acceptable
integrity
4
Signal integrity
Signal integrity is a major concern!
Vdd
Vs
ideal signal
overshoot
excessive delay
5
Behavioral InterconnectSI Fault Models Maximal aggressor (MA) model (Cuviello ICCAD’99)
All aggressors make the same simultaneous transition in the same direction
Victim stay quiescent or makes an opposite transition 6N test vector pairs for N interconnects
Multiple transition (MT) model (Tehranipour TCAD’04) Covers all transitions on victim and multiple transitions on a
ggressors Exploit locality to reduce test pattern count – roughly test vector pairs
222 kN
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BIST for Interconnect SI Test? May cause over-testing or under-testing
Hard to work for arbitrary SOC topology
Core1 Core2
Core3Core4
Core5
victimaggressor
aggressor
Test stimuli loaded from external tester
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Wrapper Cells for Interconnect SI Test
D1 Q1
FF1
01
D2 Q2
FF2
01
TDI/previous cell
wsc
TDO/next cell
wci
D1 Q1
FF1
01
wscTDO/next cell
wco01
TDI/previous cell
SItest
ILS 01
Wrapper Output Cell Wrapper Input Cell
Aggressor/victim
Provide consecutive transitions at driving side Embed integrity loss sensor at receiving side (e.g., Bai
DAC’00; Tehranipour TCAD’04)
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SOC Test Architecture Design
Core1
Core2
w1 w1
Core3
Core5
w2 w2Core4
SOC
in out
Core1 Core2
Core3 Core4 Core5
SOC
in out
w1 w1
w2 w2
Objective: solve the test access problem Test Bus Architecture TestRail Architecture
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SOC Test Architecture Optimization Objective: Minimize Testing Time.
Wrapper design and optimization TAM width for each core Test scheduling
NP-hard Problem
Many Contributions Integer linear programming (ILP) [Jetta’02] Rectangle packing algorithm [ATS’01] TR-Architect algorithm [ITC’02] Lagrange-based algorithm [DAC’03] Graph-based algorithm [Jetta’04] …
Core4
Core5
Core1
Core2
Core3
idle
Testing Time
TA
M W
idth
Prior work focuses on core internal test only!
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Importance of Interconnect SI Test SI test pattern count can be large
Take 32-bit bus with 10 cores as an example Victim interconnect number N=2*10*32=640
(Assume each core sends data to two other cores) 2560 test vector pairs for MA model 163840 test vector pairs for MT model with k=3
SI test using serial external testis expensive Millions of clock cycles for MA model Two orders higher for MT model
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Observation and Motivation Victim is typically affected by a few nearby a
ggressors only Test pattern features lots of don’t-care bits Effective compaction strategy
Parallel external test should be used to reduce interconnect SI testing time TestRail architecture
SOC test architecture needs to be optimized to reduce the total time of both core tests and interconnect tests
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A
F
B C
D E
SOC Test Architecture for SI FaultsAggressor
Victim Victim
TAM1
TAM2
TAM3
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Interconnect SI Test Pattern FormatCore-1 WOC
Core-2 WOC
Core-3 WOC
… Core-n WOC
Bus
P1 ...↑x↓xx
xxx… 0xx…↑
… xx↑… xx1…
P2 …xxxxx x↑x… xx↓…x
… ↓xx… xx1…
P3 …x↑xx↓
x↓x… xxx…x … xxx… xxx…
P4 …xxxx↑
xxx… ↓xx…x
… x↓x… 1xx…
P5 ...↑x↓xx
1xx… xxx…↑
… ↑xx… xxx…
… …
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Vertical Dimension Compaction (Pattern Count Reduction)
Graph approch Vertex Pattern; Edge Compatibility Maximum clique partitioning produce minimum number of co
mpacted test pattern sets High computational time
Greedy heuristic Start from the first pattern and merge with the following comp
atible patterns Low computational time Quality depends on pattern order
Randomize it and do multiple times
1
5 3
4
2
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Interconnect SI test pattern format
Core-1 WOC
Core-2 WOC
Core-3 WOC
… Core-n WOC
Bus
P1 ...↑x↓xx
xxx… 0xx…↑
… xx↑… xx1…
P2 …xxxxx x↑x… xx↓…x
… ↓xx… xx1…
P3 …x↑xx↓
x↓x… xxx…x … xxx… xxx…
P4 …xxxx↑
xxx… ↓xx…x
… x↓x… 1xx…
P5 ...↑x↓xx
1xx… xxx…↑
… ↑xx… xxx…
… …
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Horizontal Dimension Compaction (Pattern Length Reduction) Motivation
Each test pattern involves only a fewcores’ terminals
Approach Bypass the boundaries of those uninvolved
cores cores grouping Tradeoff between control circuit complexity
and test pattern length reduction
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Horizontal Dimension Compaction (Pattern Length Reduction) – Cont. Creating hypergraph
Vertex Core Vertex weight Number of core’s WOCs
Hyper-edge Cores involved in a test pattern Edge weight Number of times
Hypergraph partition Goal: Minimum cut Tool: hMetis
1
27
3
46
5
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Problem Formulation Given
Maximum TAM width Wmax Test set parameters for each core Test set parameters for each group of compacted S
I test sets
Determine Wrapper design for each core TAM resource assigned to each core Test schedule for entire SOC
Goal: Minimize total SOC testing time!
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Impact of TAM Architecture on SI Testing Time
Core1 Core2
Core3 Core4
Core5
Core3 Core2
Core1 Core4 Core5
idle
SI3
SI2
SI3
SI1
SI1 SI2
SI1
idle
TAM1
TAM2
TAM3
TAM1
TAM2
Testing Time
TAM width
TAM width
Testing Time
insocT
sisocT
(a)
(b)
insocT
sisocT
1
5
sicoreT 2
5
sicoreT
1siT
2siT
3siT
5
incoreT
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Complexity of SI Test Core testing time related
to TAMwidth only Can be pre-computed
Interconnect SI testing time involves multiple TAMs Cannot be computed until
TAM architectureis known
Core1 Core2
Core3 Core4
Core5 idle
Tin Tsi
SI3
SI1 SI2
idle
TAM1
TAM2
TAM3
Testing Time
TAM width
Core3 Core2
Core1 Core4 Core5
Tin Tsi
SI2
SI3
SI1SI1
TAM1
TAM2
TAM width
Testing Time
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SOC Test Architecture Optimization for Interconnect SI Faults
Construct an initial TAM design
Modified TR-Architect optimization
Schedule SI Tests
Satisfied?No
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TR-Architect Optimization
C
B
A D
TA
M w
idth
w1
w2
w3
t1t2t3
Test time
Idle time
Idle time
C
B A D
w1
w2
w3
t1t2
Test time
Idle time
Free width
C
B A D
w1
w2
t2
Test time
t1
Idle time
gain
Source: Goel and Marinissen ITC’02
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TR-Architect Optimization – Cont.
C
B
A D
TA
M w
idth
w1
w2
w3
t1t2t3
Test time
Idle time
Idle time
C A
B
D
w2
w1
+ w
3
Idle time
gain
t1t2
Test time
Source: Goel and Marinissen ITC’02
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What’s Different?
There may be multiple bottleneck TAMs Redefine bottleneck TAMs as TAMs, when assigned extra TAM
wires, may reduce SOC total testing time
Core1 Core2
Core3 Core4
Core5 idle
Tin Tsi
SI3
SI1 SI2
idle
TAM1
TAM2
TAM3
Testing Time
TAM width
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What’s Different? – Cont. How to identify bottleneck TAMs?
Search core internal test and all SI tests
How to merge TAMs and distribute free TAM wires? Try all candidates and select the best one
How to schedule SI tests? Rectangle packing
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Experimental Setup
Random test pattern 1 victim and Na (2~6) aggressors At most 2 of Na are out of the victim cores 32 bits bus P (bus is occupied) = 50% 1~Na bus bits are used if bus is occupied
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Experiment Result for 2-D SI Test Set Compaction (SOC p93791)
Ng
Nr = 10,000 Nr = 100,000
Nc Ds ∆Ds(%) Nc Ds ∆Ds (%)
1 271 2885879 / 2468 26281732 /
2 293 2507958 -13.10 2577 22102780 -15.90
4 310 2222363 -22.99 2576 19651865 -25.23
8 331 2119383 -26.56 2690 18863425 -28.23
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Experiment Results for Test Architecture Optimization (p93791, Nr = 10,000)
Wmax T[8] Tg1 Tg2 Tg4 Tg8 Tmin ∆T[8]
(%)
∆Tg(%)
8 4226884 4179655 3979541 4066751 4054977 3979541 -5.85 -4.79
16 2191881 2073979 2056323 2034337 2036416 2034337 -7.19 -1.91
24 2150865 1413121 1373548 1370751 1391513 1370751 -36.27 -3.00
32 1076516 1040041 1050669 1061650 1026305 1026305 -4.66 -1.32
40 1016416 841403 838764 824816 829521 824816 -18.85 -1.97
48 1212780 708625 702850 696281 737059 696281 -42.59 -1.74
56 853904 606648 606572 594544 604312 594544 -30.37 -2.00
64 784973 528843 539587 521242 520286 520286 -33.72 -1.62
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Experiment Results for Test Architecture Optimization (p93791, Nr = 100,000)
Wmax T[8] Tg1 Tg2 Tg4 Tg8 Tmin ∆T[8]
(%)
∆Tg(%)
8 9279984 7157553 6629333 6482537 6308163 6308163 -32.02 -11.87
16 4935934 3650655 3382864 3231137 3170750 3170750 -35.76 -13.15
24 9532785 2459100 2258253 2190633 2187138 2187138 -77.06 -11.06
32 2177213 1882999 1732000 1668109 1650127 1650127 -24.21 -12.37
40 2879472 1523711 1422586 1351591 1338896 1338896 -53.50 -12.13
48 5969285 1256464 1176390 1169794 1160866 1160866 -80.55 -7.61
56 3479319 1071698 1008224 995447 985120 985120 -71.69 -8.08
64 3410388 923350 856743 848786 867541 848786 -75.11 -8.08
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Summary Motivation
SI test becomes more important with shrinking technology feature size
Prior work focus on core internal test only Contribution
2-D test pattern compaction strategy SOC test architecture optimization algorithm
Result Significantly reduce total SOC test time
Future Work Improved test compaction algorithm Mixed InTest & ExTest scheduling algorithm